JPH0219973B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a novel wiring structure and a method for manufacturing the same.

Semiconductor devices such as integrated circuits (IC) are LSI,
It is integrated on a large scale with VLSI, and the wiring layer formed on the surface of the device is currently only two layers at most, but in the future, as devices become more highly integrated, it will become three layers,
There is a tendency to become more and more multi-layered with 5 layers. In a conventional wiring structure, for example, an example of a MOS type semiconductor element is shown in FIG. 1, a gate electrode 2, a source region, and a drain region 3 are provided on a semiconductor substrate 1, and the surface resistance of these regions is reduced. After providing a platinum silicide (PtSi ₂ ) layer 4, a phosphosilicate glass (PSG) film 5 is deposited on it by chemical vapor deposition (CVD).
The electrode window C1 is formed by patterning. Next, an aluminum (Al) wiring layer 6 is deposited by vapor deposition or sputtering, patterned, and then a PSG film 7 is deposited thereon in the same manner.
Patterning is performed to open a connection electrode window C2. Further, an Al wiring layer 8 is deposited thereon and patterned in the same manner as described above. In this way, a method of laminating multiple layers is adopted, and a polycrystalline silicon layer or a metal silicide layer is also used instead of the Al wiring layer, but as shown in the figure, in the conventional wiring structure, the irregularities on the surface are Formation cannot be avoided. That is, since the electrode window C1 and the connection electrode window C2 are coated at the same time as the Al wiring layer coated on the upper surface, the depressions can be made large in the window portions. Therefore, as the number of laminated layers increases in the future, the unevenness will increase and become more severe, making it even more difficult to equalize the thickness of wiring layers and insulating films, and increasing the risk of disconnections and short circuits.

The present invention is aimed at solving such problems, and its features include a first insulating layer of polyacetylene film on a semiconductor substrate including a source and drain whose surfaces are coated with platinum silicide;
The first conductor layer, the insulating layer of the second polyacetylene film, and the polyacetylene film in the portions corresponding to the connection positions with the second conductor layer are selectively made into conductors by introducing conductivity type impurities. The present invention provides a semiconductor device having the following structure and a method for manufacturing the same.

Polyacetylene (( _CH ) can be formed. In addition, polyacetylene has properties as a semiconductor, and contains chlorine (Cl ₂ ), bromine (Br ₂ ), iodine (I ₂ ), fluorine compounds such as arsenic pentafluoride (AsF ₅ ), and iodine chloride (ICl). It works as a P-type semiconductor if it contains iodine compounds, other boron compounds, sulfuric acid (H ₂ SO ₄ ), nitric acid (HNO ₃ ), etc., and it also contains lithium (Li), sodium (Na), potassium (K). It is known that it becomes an N-type semiconductor. Furthermore, polyacetylene that does not contain conductive impurities (non-doped) is an insulator with an electrical conductivity of 10 ^-6 /Ωcm, but polyacetylene that contains conductive impurities (doped) has a metallic conductivity. For example, cis [CH
(AsF ₅ ) _0.064 ] If it has a composition of _x , it has a resistance of 10 ³ /Ωcm or more (electrical resistance of 0.001Ωcm or less). Then, it grows at low temperature (-70℃) to form cis type polyacetylene, which changes to transformer type when heat treated at high temperature (200℃), but when doped, it becomes a conductor. becomes.

The present invention uses such a polyacetylene film as an interlayer insulating layer of multilayer wiring, uses a selectively doped polyacetylene film as a connection electrode, and interposes platinum silicide between the connection electrode and the source/drain region to form an ohmic contact. FIG. 2 shows a sectional view of one embodiment. FIG. 2 shows the same two-layer wiring structure of a _MOS type semiconductor device as in FIG. After that, a non-doped polyacetylene film 11 is grown thereon, and an electrode 11C is selectively formed by implanting, for example, P-type impurity AsF ₅ into the electrode portion.
An Al wiring layer 6 is deposited and patterned, and then a non-doped polyacetylene film 1 is placed on top of it.
2 is grown, a connection electrode 12C is selectively formed in the same manner as in the formation of 11C, and then an upper Al wiring layer 8 is deposited and patterned. The thickness of the polyacetylene films 11 and 12 is, for example, several thousand
If the polyacetylene film of the electrode part is changed into a conductor without opening the electrode window in this way, the concavity at the window part as in the conventional case disappears and becomes flat. Therefore, not only do the dashed lines in the window area disappear, but even when multi-layered (3 or 5 layers), the increase in surface irregularities can be avoided.
The film thickness is easily made uniform, and microfabrication is facilitated, and an increase in disconnections and short circuits does not occur.

Next, to explain the manufacturing method according to the present invention, FIGS. 3 to 5 are process steps. First, as shown in FIG.
After forming a MOS type element, a Ziegler-Natsuta catalyst is applied to its surface and placed in an acetylene gas atmosphere at a low temperature.
A 1000 Å cis-type polyacetylene film 11 is grown. After the growth, the Ziegler-Natsuta catalyst is dissolved and removed with an organic solvent, but the grown polyacetylene film 11
Since it has a structure in which fibers are intertwined, it is easy to remove the Ziegler-Natsuta catalyst attached therebetween, and the polyacetylene film is insoluble in any organic solvent.

Next, as shown in Figure 4, a film thickness is applied to the top surface.
A 1 μm resist film 13 is applied and patterned to expose the polyacetylene film 11 only at the electrode portion, and AsF ₅ ions are implanted from above by ion implantation. Then, the injection voltage is 200KeV, the injection concentration is
If the amount is 10 mol% or more, the implanted portion becomes a conductor 11C. Next, the resist film 13 is dissolved and removed, and the fifth
As shown in the figure, an Al wiring layer 6 is deposited by a vapor deposition method or a sputtering method, and patterned using a lithography technique. Thereafter, a polyacetylene film 12 is grown in the same manner, a connection electrode 12C is formed, and then an Al wiring layer 8 is deposited and patterned.

The above manufacturing method is a method of ion-implanting conductivity type impurities to make polyacetylene a conductor.
In addition, the conductor can be formed by an electrochemical doping method or a diffusion method. Figure 6 is a diagram showing the relationship between AsF ₅ content and electrical conductivity.
If the content is about 10 mol% as shown in the figure, about
An electrical conductivity of 10 ³ /Ωcm was obtained, which is comparable to that of heavily doped polycrystalline Si.

As can be seen from the explanation of the above embodiments, since the present invention does not open the electrodes, the unevenness on the semiconductor surface does not become severe even if the semiconductor surface is multilayered. It is possible to maintain yield and reliability by adding multiple layers. Moreover, since the semiconductor device according to the present invention uses metal wiring such as Al to form the wiring, it has much better electrical conductivity than polycrystalline Si, and the connection electrodes have a much higher electrical conductivity than metal wiring.
Although the specific resistance is high, since the length is only 1 μm or less, the high conductivity of the wiring as a whole will not be deteriorated. Therefore, the present invention is a high-quality semiconductor device that maintains high reliability without disconnections or short circuits as a highly multilayer interconnection, and provides good conductivity, which will contribute to the promotion of large-scale integration in the future. It is.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a conventional semiconductor device, FIG. 2 is a sectional view of a semiconductor device according to the present invention, FIGS. 3 to 5 are sequential diagrams of the manufacturing process, and _FIG . This is a relationship diagram with electrical conductivity. In the figure, 1 is a semiconductor substrate, 6 and 8 are Al wiring layers, 11 and 12 are insulating layers made of polyacetylene film, 11C and 12
C is a conductor made of a polyacetylene film, and 13 is a resist film.

Claims (1)

[Scope of Claims] 1. A first insulating layer of a polyacetylene film, a first conductor layer, and a second conductive layer on a semiconductor substrate including a source and drain whose surfaces are coated with platinum silicide.
consisting of a laminated structure of an insulating layer of a polyacetylene film and a second conductor layer, and a portion corresponding to the source/drain and a connection position between the first conductor layer and the second conductor layer. A semiconductor device characterized in that the polyacetylene film of is made into a conductor by selectively introducing conductive impurities. 2. A step of depositing platinum silicide on the surface corresponding to the source/drain on the semiconductor substrate; a step of forming a first insulating layer of polyacetylene film on the surface of the semiconductor substrate including the source/drain; Source of insulating layer of polyacetylene film
a step of selectively introducing a conductive impurity into a portion corresponding to the drain to make it a conductor; a step of forming a first conductor layer on the first polyacetylene film; and a step of forming the first conductor layer on the first polyacetylene film. forming an insulating layer of a second polyacetylene film on the upper surface of the second polyacetylene film; selectively introducing conductive impurities into the insulating layer of the second polyacetylene film to make it a conductor; A method for manufacturing a semiconductor device, comprising the step of forming a second conductor layer on a film.