JPH0219977B2 - - Google Patents

Info

Publication number
JPH0219977B2
JPH0219977B2 JP57038081A JP3808182A JPH0219977B2 JP H0219977 B2 JPH0219977 B2 JP H0219977B2 JP 57038081 A JP57038081 A JP 57038081A JP 3808182 A JP3808182 A JP 3808182A JP H0219977 B2 JPH0219977 B2 JP H0219977B2
Authority
JP
Japan
Prior art keywords
substrate
electrodes
electrode
holes
periphery
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57038081A
Other languages
Japanese (ja)
Other versions
JPS58155747A (en
Inventor
Masao Muramatsu
Toshio Haga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyodo Printing Co Ltd
Original Assignee
Kyodo Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyodo Printing Co Ltd filed Critical Kyodo Printing Co Ltd
Priority to JP57038081A priority Critical patent/JPS58155747A/en
Publication of JPS58155747A publication Critical patent/JPS58155747A/en
Publication of JPH0219977B2 publication Critical patent/JPH0219977B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06KGRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07745Mounting details of integrated circuit chips
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/699Insulating or insulated package substrates; Interposers; Redistribution layers for flat cards, e.g. credit cards
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Credit Cards Or The Like (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、識別カードなどに用いられるIC基
板を製造する方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing an IC substrate used for identification cards and the like.

〔従来の技術〕[Conventional technology]

従来の識別カード用のIC基板では、第1図に
示す如く、基板1の裏面に設けた裏面電極2に
IC3が接続され、プラスチツクの保護層4で保
護されており、裏面電極2は、外部端子となる表
面電極5とスルーホール6により電気的に接続さ
れていて、このように形成されたIC基板を、カ
ード7に予め設けられた凹部8に、プラスチツク
の接着剤による充填層9により装着されて用いら
れている。
In the conventional IC board for identification cards, as shown in Fig. 1, the back electrode 2 provided on the back side of the board 1 is
The IC 3 is connected and protected by a plastic protective layer 4, and the back electrode 2 is electrically connected to the front electrode 5, which serves as an external terminal, through a through hole 6. , is used by being attached to a recess 8 previously provided in the card 7 with a filling layer 9 made of plastic adhesive.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、このスルーホール6は、カード
デザイン上において見映えが悪く、またIC用電
源(+5V、+25V、GND等)に対するスルーホ
ール6の電流容量のマージンが少な過ぎる欠点が
あつた。さらに識別カードを誤つて衣服と共に洗
濯してしまうなどの際に、洗剤などがスルーホー
ル6の隙間より内部に浸入し、ICまでも損傷す
るおそれがあり、さらに、識別カードに改変を加
えようとする者に、電極の位置を知らせるという
情報を与える、などの欠点を有するものであつ
た。
However, this through hole 6 has the drawback that it looks bad in terms of card design, and the current capacity margin of the through hole 6 with respect to the IC power supply (+5V, +25V, GND, etc.) is too small. Furthermore, if the identification card is washed with clothes by mistake, detergent or the like may seep into the interior through the gap in the through-hole 6 and damage the IC. However, this method has the disadvantage that it provides information such as informing the person who uses the electrode of the position of the electrode.

本発明は、これらの欠点を除き、体裁がよく、
電極の電流容量が大であり、薬剤が浸入するよう
な隙間はなく、また、電極の位置の目印にならな
いように表裏の電極の接続を行つたIC基板の製
法を提供することを目的とするものである。
The present invention eliminates these drawbacks, has a good appearance,
The purpose of the present invention is to provide a method for manufacturing an IC substrate in which the current capacity of the electrodes is large, there are no gaps where chemicals can infiltrate, and the front and back electrodes are connected so as not to serve as a mark of the electrode position. It is something.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、基板素材のIC基板となるべき部分
の周囲に電極の数と同じ数の穴を環状に設け、次
に該基板素材の表裏を、前記穴をおおつて導電体
膜にて被覆し、次に前記穴において、基板の周囲
よりはみ出させて前記表側及び裏側の導電体膜を
切り取ると共に、前記基板の周縁よりはみ生た前
記表側及び裏側の電極のはみ出し部を互に圧着し
て電気的接続を行わしめ、前記基板素材に前記導
電体膜を被覆した直後のプロセスから、前記電気
的接触を行わしめた後のプロセスまでのプロセス
のうち、何れかのプロセスにおいて、前記導電体
膜を複数個の電極に分離し、前記基板の周縁の外
周面をわたつて表裏にまたがつた複数個の電極を
形成することを特徴とするIC基板の製法である。
The present invention provides an annular formation of holes with the same number of electrodes around a portion of a substrate material that is to become an IC substrate, and then covers the front and back surfaces of the substrate material with a conductive film to cover the holes. Next, in the hole, cut out the conductive film on the front side and the back side so as to protrude from the periphery of the substrate, and press the protruding parts of the electrodes on the front side and the back side that protrude from the periphery of the substrate to each other. In any process from a process immediately after making an electrical connection and coating the conductive film on the substrate material to a process after making the electrical contact, This method of manufacturing an IC substrate is characterized in that the electrodes are separated into a plurality of electrodes, and the plurality of electrodes are formed across the outer peripheral surface of the periphery of the substrate and straddle the front and back sides.

〔実施例〕〔Example〕

第2〜4図において、IC基板としては基板素
材であるキヤリアフイルム11の円形の周縁12
の内部が最終的な基板13の領域である。即ち、
基板13の周囲に穴14を電極の数と同じ数だけ
間隔をおいて環状に設け、穴14,14間に形成
した保持部15によつて基板13が、外側のキヤ
リアフイルム11から支えられている。この基板
13の表面及び裏面には複数個の表面電極16及
び裏面電極17が設けられていて、この表面電極
16及び裏面電極17は、銅などの金属膜、即ち
導電体膜の貼付、転写、金属の蒸着、メツキなど
で連続的に設けた後、エツチング、機械的除去な
どにより溝状に隙間を設けて複数個の電極を形成
する。この場合、前記表面電極16、裏面電極1
7ともその外側は、基板13の周縁に達し、各々
の穴14に、表面電極16及び裏面電極17が一
つづつ臨んでいて、裏面中央の電極部18はIC
3を載置する部分となる。
In FIGS. 2 to 4, a circular peripheral edge 12 of a carrier film 11, which is a substrate material, is used as an IC substrate.
The inside of is the area of the final substrate 13. That is,
Holes 14 are provided in a ring shape around the substrate 13 at intervals equal to the number of electrodes, and the substrate 13 is supported from the outer carrier film 11 by a holding portion 15 formed between the holes 14 . There is. A plurality of front surface electrodes 16 and back surface electrodes 17 are provided on the front and back surfaces of this substrate 13, and these front surface electrodes 16 and back surface electrodes 17 are formed by attaching, transferring, or transferring a metal film such as copper, that is, a conductive film. After continuous metal deposition, plating, etc., groove-like gaps are formed by etching, mechanical removal, etc., and a plurality of electrodes are formed. In this case, the front electrode 16, the back electrode 1
The outside of both 7 reaches the periphery of the substrate 13, and one front electrode 16 and one back electrode 17 face each hole 14, and the electrode section 18 at the center of the back surface is connected to the IC.
This is the part where 3 is placed.

次に、第5図に示す如く、表面電極16と裏面
電極17とを無電解メツキなどにより形成した接
続部20により、基板13の周縁12(第2,3
図)の外周面19(第4図)をわたつて電気的に
接続して、その後、電解メツキにより厚盛りを行
い、さらに金メツキにて保護する。
Next, as shown in FIG. 5, the peripheral edge 12 (second and third
(Fig. 4) and is then electrically connected across the outer circumferential surface 19 (Fig. 4), and then thickly plated by electrolytic plating and further protected by gold plating.

次に、保持部15より基板13を切り離し、第
6図に示す如く、電極部18にIC3を装着し、
金線21によりワイヤボンデイングを行つてから
プラスチツクにより保護層4を形成し、これを第
1図に示す如くカード7の凹部8に接着剤の充填
材で装填するのが普通である。
Next, the substrate 13 is separated from the holding part 15, and the IC 3 is attached to the electrode part 18 as shown in FIG.
After wire bonding with a gold wire 21, a protective layer 4 of plastic is formed, and this is usually filled into the recess 8 of the card 7 with an adhesive filler, as shown in FIG.

本発明の実施例の製法の過程では、先ず第7図
に示すように基板素材10の表面と裏面に銅箔用
の接着剤層22を設け、第8図の如く、ICの基
板13となるべき部分の周囲に電極の数と同じ数
の穴14を環状に設け(第2〜3図の穴14と同
様)、次に第9図の如く電極素材としての導電体
膜である銅箔23,24を表、裏に、穴14をお
おつて貼り着けて被覆する。この状態では、基板
13の周縁12の外周面19は絶縁状態にある。
In the manufacturing process of the embodiment of the present invention, first, as shown in FIG. 7, adhesive layers 22 for copper foil are provided on the front and back surfaces of the substrate material 10, and as shown in FIG. 8, an IC substrate 13 is formed. Holes 14 of the same number as the number of electrodes are provided in an annular shape around the area where the electrodes are to be formed (same as the holes 14 in FIGS. 2 and 3), and then copper foil 23, which is a conductive film as an electrode material, is formed as shown in FIG. , 24 on the front and back sides, covering the hole 14 and covering it. In this state, the outer peripheral surface 19 of the peripheral edge 12 of the substrate 13 is in an insulated state.

次に、第10図の如く、基板13の周縁12よ
り少し離れた位置にある刃25と、段部26と、
穴14の外側付近を切る刃27を備えたカツター
28を下降せしめて、穴14の部分の銅箔23,
24を、基板13の周縁12より少しはみ出させ
た状態で切断し、さらにカツター28を下降せし
め段部26により、はみ出した銅箔23と24を
台29に押し付け、超音波振動を与えて銅箔23
と24とを超音波溶接により電気的に接続、或い
は極めて接近せしめる。
Next, as shown in FIG.
The cutter 28 equipped with a blade 27 that cuts near the outside of the hole 14 is lowered to cut the copper foil 23,
The cutter 28 is lowered and the protruding copper foils 23 and 24 are pressed against the stand 29 by the step 26, and ultrasonic vibration is applied to cut the copper foil 23
and 24 are electrically connected by ultrasonic welding, or brought very close to each other.

次に第11図の如く、銅箔23と24接続部或
いは近接部を、無電解メツキにより接続して電気
的接続を行い、さらに電解メツキで厚盛りを行
い、さらに金メツキを施し、このようにして形成
した接続部20により、基板13の周縁12の外
周面19をわたつて表裏にまたがつて表の銅箔2
3とと裏の銅箔24とが電気的に接続される。
Next, as shown in FIG. 11, the connection parts or adjacent parts of the copper foils 23 and 24 are connected by electroless plating to make an electrical connection, and then a thick layer is applied by electrolytic plating, and then gold plating is applied. The connecting portion 20 formed in the above-mentioned manner allows the copper foil 2 on the front side to straddle the front and back sides of the outer peripheral surface 19 of the peripheral edge 12 of the substrate 13.
3 and the copper foil 24 on the back are electrically connected.

次に第12図に示す如くレジスト材30を電極
の形状に応じて配備し、エツチングを行つて、銅
箔を分離し第13図の如く銅箔パターンにより表
面電極16及び裏面電極17を形成する。
Next, as shown in FIG. 12, a resist material 30 is placed according to the shape of the electrode, and etching is performed to separate the copper foil, forming a front electrode 16 and a back electrode 17 with a copper foil pattern as shown in FIG. .

このようにして形成された表面電極16及び裏
面電極17は、基板13の周縁12の外周面19
をわたつて、接続部20により電気的に接続され
ている。
The front electrode 16 and the back electrode 17 formed in this way are formed on the outer peripheral surface 19 of the peripheral edge 12 of the substrate 13.
The terminals are electrically connected by a connecting portion 20 across the terminals.

この実施例でのIC基板は、第6図に示すよう
に裏面電極17の電極部18にIC3を装着し、
金線21によりワイヤボンデイングを行つてから
樹脂で保護層4を被覆してICを密閉封止し、さ
さらに第1図例と同様にこれをカードの凹部に充
填材、例えば接着剤をもつて装着して識別カード
として用いられるものである。
As shown in FIG. 6, the IC board in this embodiment has an IC 3 attached to the electrode part 18 of the back electrode 17,
After wire bonding with the gold wire 21, the protective layer 4 is covered with resin to hermetically seal the IC, and this is then placed in the recess of the card with a filler, such as an adhesive, as in the example in FIG. It is attached and used as an identification card.

この場合、外部端子となる表面電極16には、
スルーホールの如き穴はなく、平坦であり、外見
がよく、また、接続部20の断面積は、幅及び厚
さの選択により十分なる電流容量を確保すること
ができ、薬剤浸入を招く穴がなく、また、目印が
ないので外部端子であるかどうか区別が容易でな
いので、カードの改変をも予防することができ
る。
In this case, the surface electrode 16 serving as an external terminal has
There is no hole such as a through hole, it is flat and has a good appearance, and the cross-sectional area of the connecting part 20 can ensure sufficient current capacity by selecting the width and thickness, and there are no holes that may cause drug infiltration. In addition, since there is no mark, it is not easy to distinguish whether it is an external terminal or not, so it is possible to prevent the card from being tampered with.

エツチングの代わりに機械的に銅箔の一部を除
去して電極を分離するようにしてもよい。この電
極分離のプロセスは、銅箔23,24にて被覆を
行つた(第9部)直後のプロセスから、接続部2
0を形成した(第11図)後のプロセスまでの間
の、何れの段階のプロセスにおいて行つてもよ
い。
Instead of etching, a portion of the copper foil may be mechanically removed to separate the electrodes. This electrode separation process starts from the process immediately after coating with copper foils 23 and 24 (Part 9).
It may be performed at any stage of the process up to the process after forming 0 (FIG. 11).

〔発明の効果〕〔Effect of the invention〕

本発明は、基板素材のIC基板となるべき部分
の周囲に電極の数と同じ数の穴を環状に設け、次
に該基板素材の表裏を、前記穴をおおつて導電体
膜にて被覆し、次に前記穴において、基板の周囲
よりはみ出させて前記表側及び裏側の導電体膜を
切り取ると共に前記基板の周縁よりはみ出た前記
表側及び裏側の電極のはみ出し部を互に圧着して
電気的接続を行わしめ、前記導電体膜を複数個の
電極に分離し、前記基板の周縁の外周面をわたつ
て表裏にまたがつた複数個の電極を形成すること
により、必要な電流容量に対するマージンが十分
とれ、薬剤などが浸入するおそれがなく、また、
外部電極の位置が不明となり改変を防ぐことがで
きるIC基板を簡便に製造することができると共
に、生産性も著しく良好にでき、識別カードなど
においてはカードのデザイン、印刷に与える障害
がなくなり体裁がよいし、またカードの発行会社
や使用会社などを表示する文字や図形を表面電極
を用いて表示する場合、即ち表面電極自体の形を
文字や図形の形とする場合に極めて好適な製品と
し、商品価値を大幅に高められるものである。
The present invention provides an annular formation of holes with the same number of electrodes around a portion of a substrate material that is to become an IC substrate, and then covers the front and back surfaces of the substrate material with a conductive film to cover the holes. Next, in the hole, the conductor films on the front and back sides are cut out so as to protrude from the periphery of the substrate, and the protruding portions of the electrodes on the front and back sides that protrude from the periphery of the substrate are crimped together for electrical connection. By separating the conductor film into a plurality of electrodes and forming the plurality of electrodes extending over the front and back surfaces of the substrate, a sufficient margin for the required current capacity can be obtained. There is no risk of spillage or infiltration of chemicals, and
It is possible to easily manufacture an IC board in which the position of the external electrode is unknown and tampering can be prevented, and the productivity is also significantly improved.For identification cards, etc., there are no obstacles to the design and printing of the card, and the appearance can be improved. In addition, it is an extremely suitable product when characters or figures indicating the issuer or user company of the card are displayed using the surface electrode, that is, when the shape of the surface electrode itself is the shape of the letters or figures. This can significantly increase the product value.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来例の断面図、第2図は平面図、第
3図は裏面図、第4図は第2図の−線断面
図、第5図、第6図は製作過程を示す断面図、第
7図ないし第13図はそれぞれ本発明の実施例に
おける製作過程を示す断面図である。 1,13……基板、2,17……裏面電極、3
……IC、4……保護層、5,16……表面電極、
6……スルーホール、7……カード、8……凹
部、9……充填層、11……キヤリアフイルム、
12……周縁、14……穴、15……保持部、1
8……電極部、19……外周面、20……接続
部、21……金線、22……接着剤層、23,2
4……銅箔、25,27……刃、26……段部、
28……カツター、29……台、30……レジス
ト材。
Figure 1 is a sectional view of the conventional example, Figure 2 is a plan view, Figure 3 is a back view, Figure 4 is a sectional view taken along the - line in Figure 2, and Figures 5 and 6 are cross sections showing the manufacturing process. 7 to 13 are cross-sectional views showing the manufacturing process in an embodiment of the present invention. 1, 13... Substrate, 2, 17... Back electrode, 3
...IC, 4...protective layer, 5,16...surface electrode,
6...Through hole, 7...Card, 8...Recess, 9...Filled layer, 11...Carrier film,
12... Periphery, 14... Hole, 15... Holding part, 1
8... Electrode part, 19... Outer peripheral surface, 20... Connection part, 21... Gold wire, 22... Adhesive layer, 23,2
4...Copper foil, 25, 27...Blade, 26...Step part,
28... cutter, 29... stand, 30... resist material.

Claims (1)

【特許請求の範囲】[Claims] 1 基板素材のIC基板となるべき部分の周囲に
電極の数と同じ数の穴を環状に設け、次に該基板
素材の表裏を、前記穴をおおつて導電体膜にて被
覆し、次に前記穴において、基板の周囲よりはみ
出させて前記表側及び裏側の導電体膜を切り取る
と共に、前記基板の周縁よりはみ出た前記表側及
び裏側の電極のはみ出し部を互に圧着して電気的
接続を行わしめ、前記基板素材に前記導電体膜を
被覆した直後のプロセスから、前記電気的接触を
行わしめた後のプロセスまでのプロセスのうち、
何れかのプロセスにおいて、前記導電体膜を複数
個の電極に分離し、前記基板の周縁の外周面をわ
たつて表裏にまたがつた複数個の電極を形成する
ことを特徴とするIC基板の製法。
1. Holes of the same number as the number of electrodes are provided in a ring around the part of the substrate material that is to become the IC board, then the front and back sides of the substrate material are covered with a conductive film by covering the holes, and then In the holes, the conductive films on the front and back sides are cut so as to protrude from the periphery of the substrate, and the protruding portions of the electrodes on the front and back sides that protrude from the periphery of the substrate are crimped together to establish an electrical connection. From the process immediately after coating the substrate material with the conductor film to the process after making the electrical contact,
A method for manufacturing an IC substrate, characterized in that, in any one of the processes, the conductive film is separated into a plurality of electrodes, and the plurality of electrodes are formed across the outer circumferential surface of the periphery of the substrate and straddle the front and back sides. .
JP57038081A 1982-03-12 1982-03-12 Ic substrate and manufacture thereof Granted JPS58155747A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57038081A JPS58155747A (en) 1982-03-12 1982-03-12 Ic substrate and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57038081A JPS58155747A (en) 1982-03-12 1982-03-12 Ic substrate and manufacture thereof

Publications (2)

Publication Number Publication Date
JPS58155747A JPS58155747A (en) 1983-09-16
JPH0219977B2 true JPH0219977B2 (en) 1990-05-07

Family

ID=12515526

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57038081A Granted JPS58155747A (en) 1982-03-12 1982-03-12 Ic substrate and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS58155747A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0517269Y2 (en) * 1986-05-15 1993-05-10
JPH01108798A (en) * 1987-10-21 1989-04-26 Nec Corp Manufacture of printed wiring board

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5010564A (en) * 1973-05-25 1975-02-03

Also Published As

Publication number Publication date
JPS58155747A (en) 1983-09-16

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