JPH02199841A - Manufacture of mis transistor - Google Patents

Abstract

PURPOSE:To form a MIS transistor whose junction leakage characteristic and the like are excellent by a method wherein a polymerization film composed of a resist material is formed along a cross-sectional shape of a gate electrode, sidewalls composed of the polymerization film are formed on side faces of the gate electrode, impurities are introduced into a semiconductor substrate by making use of the gate electrode and the sidewalls as a mask and a source- drain region is formed. CONSTITUTION:An SiO2 film 12 and a polycrystalline Si film 13 are formed on an Si substrate 11. P<+> is implanted into the Si substrate 11 by making use of them as a mask; an n<-> region 14 is formed. Then, a PMMA film 15 is deposited along a cross-sectional shape of the polycrystalline Si film 13 and the SiO2 film 12. Then, the PMMA film 15 is dry-etched anisotropically; sidewalls 16 composed of the PMMA film 15 are formed on side faces of the polycrystalline Si film 13 and the SiO2 film 12. Then, As<+> is implanted into the Si substrate 11 by making use of the polycrystalline Si film 13, the SiO2 film 12 and the sidewalls 16 as a mask; an n<+> region 17 is formed. The side walls 16 are removed; after that, a heat treatment is executed in order to activate impurities in the n<-> region 14 and the n<+> region 17.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a Mis) transistor in which side walls are formed on the sides of a gate electrode, such as in an LDD structure.

[Summary of the invention]

The present invention provides a manufacturing method for an MIS transistor as described above, in which the sidewalls of the gate electrode are formed with a polymeric film made of a resist material, thereby achieving excellent MIS transistors with excellent junction leakage characteristics, etc.
This makes it possible to manufacture IS transistors.

[Conventional technology]

Mis) In order to form a transistor into an LDD structure or to control the effective gate length with high precision, sidewalls are formed on the sides of the gate electrode and impurities are introduced into the semiconductor substrate to form source/drain regions. In some cases, a method is used in which the gate electrode and sidewalls are used as a mask (for example, Japanese Patent Laid-Open No. 54
-4482 publication), and subordinate 1, S10. It was common to form side walls with membranes.

[Problem to be solved by the invention]

However, if heat treatment for activating impurities for forming source/drain regions is performed with sidewalls formed on the sides of the gate electrode, stress is applied from the sidewalls to the semiconductor substrate.

As a result, crystal defects occur in the semiconductor substrate near the intersection between the surface of the sidewall and the surface of the semiconductor substrate, and junction leakage current increases. This problem becomes more serious as the junction between the source and drain regions becomes shallower.

To deal with this, it may be possible to perform heat treatment after removing the sidewalls. However, if the sidewalls are formed of a Si film, the s + o z IIQ for element isolation, the 5iO1 film as a gate insulating film, etc. will be etched at the same time as the sidewalls, which is not preferable.

Therefore, with the conventional method described above, it is not possible to manufacture a MIS transistor with excellent junction leakage characteristics.

[Means for Solving the Problems] The method for manufacturing an MISI transistor according to the present invention includes a step of forming a gate electrode 13 on a semiconductor VE temporary 11 via a gate electrode 1al1g12, and a polymeric film 15 made of a resist material. The said game!・A step of forming the electrode 13 along the cross-sectional shape, and forming the polymerized T on the side surface of the gate electrode 13.
I! The method includes a step of forming a side wall 16 made of i15, and a step of introducing impurities into the semiconductor substrate 11 using the gate electrode 13 and the side wall 16 as a mask to form a source/drain region 17.

[Effect]

In the method for manufacturing a MISI transistor according to the present invention, impurities for forming source/drain regions 17 are added to a semiconductor substrate 1.
The side wall 16 of the gate electrode 13, which is used as a mask when introducing the gate electrode 1 into the inside of the gate electrode 1, is formed of polymer #15 made of a resist material.
The polymer film 15 made of a resist material has high selectivity with respect to the gate electrode 13, gate insulating film 12, etc. in its removal process.

Therefore, the heat treatment for activating the impurities can be performed after removing the sidewall 16 made of the polymer film 15,
It is possible to prevent crystal defects from occurring in the semiconductor substrate 11 due to stress applied to the semiconductor substrate 11 from the sidewall 16 during heat treatment.

〔Example〕

Hereinafter, an embodiment of the present invention applied to the manufacture of an nMO3) transistor having an LDD structure will be described with reference to FIG.

In this embodiment, first, as shown in FIG. 1A, a Stow film 12, which is a gate insulator, and a polycrystalline Si film 13, which is a gate electrode, are formed on a p-type Si substrate 1i.

Then, using these as a mask, Po ions are implanted into the Sil plate 11 at a concentration of about I x 10 "cm-", thereby forming the n-jJl region 14.

Next, MMA is subjected to a polymerization reaction in plasma, and a PMMA film 15 is deposited on the Si substrate 11, as shown in FIG. 1B. When CVD is performed in this manner, PMMA11!215 is deposited along the cross-sectional shape of the polycrystalline Si films 13 and 5i (12).

Next, Ox,, Nz, N! PMMA in an atmosphere of 11 mag.
By anisotropically dry etching the film 15, the polycrystalline St film 13 and Sing film 1 are etched as shown in FIG. 1c.
A side wall 1G made of PMMA film 15 is formed on the side surface of 2.

Next, using the polycrystalline Si film 13.5iOzJIQ 12 and the sidewall 16 as a mask, the St substrate 11 is 5x1
By implanting ions at a concentration of about 0 Icm-'', an n'' region 17 is formed as shown in FIG. 1D.

As a result, source/drain regions consisting of the n-fil region 14 and the n5w1 region 17 are formed.

Next, as shown in FIG. 1E, the side wall 16 is removed, but since the PMMA forming the side wall 16 is a resist material,
0. Conventional resist removal methods such as plasma ashing can be used.

Therefore, the polycrystalline Si film 13 that is the gate electrode, the Sin film 12 that is the gate insulating film, and the Sing film for element isolation (
(not shown) etc. are not removed at the same time as the side wall 16, and only the side wall 16 can be removed without changing their shape.

Thereafter, in order to activate the impurities in the n- region 14 and the n'' region 17, heat treatment is performed at a temperature of 900° C. or higher in the state shown in FIG. 1E. No crystal defects are generated in 11. After this, the same steps as in the conventional method are performed to complete the nMOS transistor.

nMO3I with LDD structure manufactured in this example as described above
- In transistors, n- region 14 and n4 region 17 and S
i board l! Even if the junction becomes shallow, the increase in junction leakage current is suppressed.

Suppressing the junction leakage current of shallow junctions in this way is
Important for future LJLS 1.

In addition to manufacturing MIS transistors, the present invention can also be applied to the following processes.

FIG. 2 shows a first application example. In this first application example, the AIl wiring 22 on the 5ift film 21, which is the insulating film between the eyebrows,
Further, the Si island peritoneum 23, which is an insulating film between the eyebrows, is formed, and the AI
The contact hole reaching the wiring 22 is 5i (hlA
23.

Incidentally, as the density of devices increases, contact holes are also required to be finer. However, the resist film 24 formed on the SiO 23 for patterning the contact hole also has a limit in resolution, etc., and it is not possible to form an opening smaller than this limit in the resist M424.

Therefore, in this first application example, the aperture 25 of the above limit is used.
is first formed on the resist film 24, and then a side wall 26 similar to that of the above-mentioned embodiment is formed on the inner surface of the opening 25.

Therefore, if a contact hole is formed in the SLO film 23 in this state, the contact ball will become finer than the above limit.

FIG. 3 shows a second application example. In this second application example, a Sing film 27 for an upper layer on one Si5 board and an SiN film 28 which is an anti-oxidation film are formed, and 5 lots of films for element isolation are formed by selective oxidation. .

As is well known, bird's beaks occur in the 5i01 film formed by selective oxidation. Therefore, in order to effectively secure the element formation area, it is necessary to anticipate the occurrence of bird's beak in advance, and
The width from which the N film 28 is removed may be made narrower by that amount, but this width cannot be made narrower than the minimum line width.

Therefore, in this second application example, an opening 25 of about the minimum line width is first formed in the resist film 24 formed on the two SiN films, and then a side wall 26 similar to that of the above-mentioned embodiment is formed inside the opening 25. It is formed on the side.

Therefore, if the SiN film 28 is removed in this state, 5iN
The width from which li28 is removed is even narrower than the minimum line width.

〔Effect of the invention〕

In the method for manufacturing an MIS transistor according to the present invention, it is possible to prevent crystal defects from occurring in the semiconductor substrate during heat treatment for activating impurities for forming source/drain regions. M.I.S.
Transistors can be manufactured.

[Brief explanation of the drawing]

Fig. 1 is a side sectional view sequentially showing one embodiment of the present invention;
3 and 3 are side sectional views showing first and second application examples of the present invention, respectively. In addition, in the symbols used in the drawings, 11.--.--.--.--.--.--Si substrate 12
−−−−1・x−−−3iOz1m13・・・・・・−
・・・−・・・・・・・・・Polycrystalline S+）Model 15・・・
・・−・−・−・・〜・PMMA film 16・−・−・・
・−・−−−m−Side wall 17・・−・−・・・−
...n” 81 bi.

Claims (1)

[Claims] 1. A step of forming a gate electrode on a semiconductor substrate via a gate insulating film; A step of forming a polymer film made of a resist material along the cross-sectional shape of the gate electrode; and a step of introducing impurities into the semiconductor substrate using the gate electrode and the sidewall as a mask to form a source/drain region. Production method. 2. The method of manufacturing a MIS transistor according to claim 1, wherein the heat treatment for activating the impurity is performed after removing the sidewall.