JPH0220024B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a data transmission system in which a group of variable-length data blocks are inserted without gaps between variable-length synchronization codes for transmission, and is a data transmission system with high transmission efficiency. It is related to.

(b) Conventional technology and problems The conventional data transmission method will be explained using diagrams.
FIG. 1 is a diagram showing the configuration of a conventional transmission frame for transmitting a group of variable length data blocks.

In the figure, 1, 2, 3, 4, 5 are synchronization code areas, 6 -
10 is a block size code (hereinafter referred to as BS code) area that indicates the number of bytes of data in a data block, and 11 to 15 are data areas.

In the conventional data transmission system, when transmitting a group of variable length data blocks, each data area 11, 12, 13, 14, 15 and each BS code area 6, 7, 8, 9, 10 are transmitted as shown in FIG. Each synchronization code area 1, 2, 3, 4,
5, and a synchronization code was inserted for transmission. For this reason, the number of synchronization code regions is large, resulting in poor transmission efficiency, and the number of synchronizations required on the receiving side is large, resulting in poor reception efficiency. In particular, as shown in the example of data area 12,
When sending a byte of data, a total of 3 bytes are required, including a 1-byte synchronization code area 2 and a 1-byte BS code area 7, and when sending such 1-byte data continuously, the frame structure There is a drawback that the number of synchronization code regions is extremely large, resulting in very poor transmission efficiency, and the number of times synchronization is required on the receiving side is also very large, resulting in very poor receiving efficiency.

(c) Object of the Invention In view of the above drawbacks, the object of the present invention is to provide a data transmission system with high transmission efficiency and reception efficiency.

(d) Structure of the Invention In order to achieve the above object, the present invention has a means for adding the number of bytes of each data block after inserting a synchronization code, and a means for adding the number of bytes of each data block after inserting a synchronization code, and a means for adding the number of bytes of the synchronization code to the number of bytes of the synchronization code. From the maximum possible number of bytes of a synchronization block (a block consisting of a synchronization code area and a group of data block areas) that does not cause
A means is provided to insert a synchronization code when the value is greater than the maximum number of bytes that can be represented by a data block in the range represented by the BS code, and this means inserts a synchronization code between variable-length period synchronization codes. This method is characterized in that a transmission frame in which a group of variable length data blocks are inserted without gaps is constructed and transmitted.

(e) Embodiment of the Invention An embodiment of the data transmission system of the present invention will be described in detail below with reference to the drawings. FIG. 2 is a configuration diagram of a transmission frame for transmitting a group of variable length data blocks according to an embodiment of the present invention, and FIG. 3 is a block diagram of a transmitting circuit according to an embodiment of the present invention.

Components in FIG. 2 that have the same functions as those in FIG. is a down counter, 25 is a synchronization code insertion circuit, and 26 is a flip-flop (hereinafter referred to as
FF), 27 and 28 are AND circuits, 29 and 3
0 indicates an OR circuit.

First, the main points of the present invention will be explained using FIG. 2.
First, a synchronization code is added to the synchronization code area 1', the number of bytes of the synchronization code is added, and thereafter the number of bytes of the data block group is counted. At the end of counting data blocks, if the count number n is within the range of equation (1) below, the count number is cleared and a synchronization code 2' is inserted.

N _n −m＜n ……(1) where n= _j 〓 ⁱ⁼¹ (n _i +1)+1= _j 〓 ⁱ⁼¹ N _i +1 ……(2) where m is the maximum byte that the data block can take Since the BS code is usually 1 byte, the total number is 65 at most, including 1 bit of the BS code.

N _n is the maximum number of bytes that a synchronization block can take, which is determined within a range that does not cause synchronization, and is usually 256.
It is.

j is the number of data blocks existing in the synchronous block, which is 4 in the case of FIG. 2.

Ni is the number of bytes of each data block, which is the number of bytes of data ni plus the number of bytes of BS code 1.

Also, the synchronization code is a normally used 1 byte. According to this method, when transmitting 1 byte of data, it is only necessary to insert a synchronization code after N _n -m/2 data blocks, resulting in very high transmission efficiency.

Next, a method for inserting a synchronization code will be explained using the transmitting circuit shown in FIG.

At initialization, put one initial clock into the initial setting terminal and set FF26. At this time, the block size signal (hereinafter referred to as BS
When the signal (referred to as a signal) enters the AND circuit 27, one pulse is output from the AND circuit 27, which acts on the synchronization code inserter 25 and connects the data bus 2.
A synchronization code is inserted within. Also, the pulses output from the AND circuit 27 are simultaneously output from the up counter 21.
and resets FF 26 and comparator 22. Also, by inputting the previous BS signal to the write terminal of the down counter 24, the BS signal on the data bus 1 is
The code data n ₁ The number of bytes of the data block N ₁ (n ₁
+1) and counts the system clock (synchronized with the parallel data on data bus 1) that will be input thereafter. At the same time, the up counter 21 also starts counting the system clock. The down counter 24 clocks the system clock.
By taking in Ni (n _i +1) pieces, the count becomes 0 and one output pulse is sent out. This operation continues as long as the BS signal is input. While the down counter 24 continues to output pulses several times,
The up counter 21 continues to count the system clock, and this count number G is compared with the value (N _n - m-1) given in advance to the comparator 22,
When the following _equation (3) is ^satisfied , the output of the _comparator 22 is latched at the H level. When a pulse is output from the down counter 24 after the output of the comparator 22 becomes H level, the pulse is sent to the synchronization code insertion circuit 2 via the AND circuit 28 and the OR circuit 30.
5 and a synchronization code is inserted. At this time, the pulse passed through the AND circuit 28 passes through the OR circuit 29 and resets the up counter 21. When the up counter 21 is reset, the output of the comparator 22 becomes L level. These series of operations continue as long as the data block exists.

Next, the operation of achieving synchronization in the receiving circuit will be explained.

FIG. 4 is a block diagram of the receiving circuit.

In the figure, 31, 32, 42 are FF, 33, 34, 3
9 is a comparator, 35 is a 1-bit delay circuit, 36 is a synchronization code remover, 37 is an incrementer, 38 is a counter, 40 is a selector, 41 is an adder, 43,
44, 45 are AND circuits, 46 to 49 are OR circuits, 50 is a NOT circuit, FF 31, comparator 33, 1-bit delay circuit 35, synchronization code remover 3
6 constitutes a synchronization state determination circuit, and a comparator 34,
Incremeter 37, selector 40, adder 4
1. The FF 42 constitutes a synchronization signal detection timing determination circuit.

Next, the operation will be explained. In the initial state, by inputting one pulse to the initial setting terminal, the FF 31 is set and the adder 41 is reset. By setting FF31,
The comparator 33 is enabled, and the synchronization code of the received signal can be detected. When a received signal as shown in FIG. 2 is input to the data bus 1 in synchronization with the system clock, the comparator 33 compares it with a preset synchronization code and determines the second synchronization code. In the figure, synchronous code area 1'
Detect the synchronization code of At the same time, comparator 33
The synchronization code is removed from the synchronization code remover 36 by one pulse output from the FF31.
is reset and the comparator 33 becomes disabled. This will result in a synchronized state. Furthermore, one pulse outputted from the comparator 33 is processed by the 1-bit (corresponding to 1 bit of the system clock) delayer 35 to convert the n _1- byte data in the BS code area 6 in FIG. n Synchronized with BS code representing ₁ byte,
This is applied to the select 40, 1 is added to the _n1 byte of data by the incrementer, the number of bytes of the data block _N1 ( _n1 + 1) is taken in, and it is applied to the adder 41, and the number of bytes of the data block to be taken from now on is Ni. Add (ni+1). This pulse also enters the write terminal of the FF 32, which latches the number _N1 of bytes of the data block output from the selector 40 and resets the counter 38. Furthermore, since this pulse is synchronized with the BS signal, it is taken out as a BS synchronization signal.
The counter 38 is now reset and the incoming system clock corresponds to each byte of the data block and counts until it equals the number _N1 latched in the FF 32. When they become equal, one pulse is outputted by the action of the comparator 39, which enters the selector 10 via the AND circuit 44, and the number of bytes of the next data block is taken into the FF 32, and at the same time is also taken into the adder 41. be included. Furthermore, this pulse causes the counter 3 to
8 is reset. Also, since this pulse is synchronized with the BS signal, it is taken out as a BS synchronization signal. These series of operations are repeated as long as the BS signal continues. Next, the number of bytes continued to be added by the adder 41 is compared with a predetermined condition (N _n -m) set in advance in a comparator 44, and if it is larger than the predetermined condition, the number of bytes added by the comparator 44 is pulses are output to reset the FF 42.

However, at this point, it is not synchronized with the timing of the next synchronization signal, so FF 31 is not set and therefore comparator 33 is not enabled. FF42
Since the time when the comparator 39 first outputs a pulse after is set is the synchronization time of the synchronization code,
This pulse passes through an AND circuit 43 and an OR circuit 46 to set the FF 31. This allows comparator 3
3 is enabled, it is determined whether the received signal is a synchronization code, and if it is a synchronization signal, it is brought into the synchronization state again and the FF 42 is reset. If it is not a synchronization code, it is assumed to be in an out-of-synchronization state and this state continues until a synchronization code is detected. In this way, it is synchronized and received.

In the case of the present invention, since the synchronization code exists at an interval of N _n -m to N _n bytes, a plurality of data blocks exist between when a synchronization state is determined and when the next synchronization state is determined. Enables efficient reception processing. Of course, when transmitting only 1 byte of data, the reception efficiency becomes extremely high.

(f) Effects of the Invention As explained in detail above, according to the data transmission system of the present invention, the minimum number of N _n −
Since the next synchronization code is inserted after m bytes, the transmission efficiency and reception efficiency can be improved, and this effect is particularly great when transmitting 1 byte of data continuously.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a transmission frame for transmitting a group of variable-length data blocks in a conventional example, FIG. 2 is a configuration diagram of a transmission frame for transmitting a group of variable-length data blocks in an embodiment of the present invention, and FIG. FIG. 4 is a block diagram of a transmitting circuit according to an embodiment of the present invention. FIG. 4 is a block diagram of a receiving circuit according to an embodiment of the present invention. In the figure, 1 to 5, 1', and 2' are synchronization code areas, and 6 to 1
0 is a block size code area, 11 to 15 are data areas, 21 is an up counter, 22, 33, 3
4, 39 are comparators, 23, 37 are incrementers, 24 are down counters, 25 are synchronous code insertion circuits, 26, 31, 32, 42 are flip-flops, 27, 28, 43, 44, 45 are AND circuits, 29 , 30, 46-49 are OR circuits, 35 is a 1-bit delay circuit, 36 is a synchronization code remover, 38
is a counter, 40 is a selector, 41 is an adder, 5
0 indicates a knot circuit.

Claims (1)

[Scope of Claims] 1. In a data transmission system for transmitting a group of variable-length data blocks, means for adding the number of bytes of each data block following the synchronization code after inserting the synchronization code, and combining this sum with the bytes of the synchronization code. When the value added to the number becomes larger than the value obtained by subtracting the maximum number of bytes of a data block that can be represented by a block code from the maximum number of bytes that a synchronization block can have within the range that does not cause synchronization loss, A data transmission system comprising means for inserting a synchronization code, and the means constructs and transmits a transmission frame in which a group of variable length data blocks are inserted without gaps between synchronization codes of variable length periods.