JPH0220079A - Superconductor circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a superconducting circuit, particularly a superconducting circuit configuration in which a predetermined logic is realized by combining a plurality of Josephson junction elements in a multilayer structure. The purpose is to minimize the power phase shift between each gate driven by the current of the corresponding phase and to suppress temporal fluctuations in the voltage level of the superconducting ground plane. at least one comprising a combination of a plurality of Josephson junction elements to a conductive ground plane;
A layered circuit with two gates has a structure in which multiple layers are stacked on a chip, and the superconducting ground planes of each layer are connected to each other via contact portions so that they have a common potential, and the gates of each layer are are arranged at corresponding positions such that the wiring lengths from the power input section formed on the chip are approximately the same, and are shifted from each other by a predetermined phase difference supplied via the power input section. It is configured to be driven by currents of corresponding phases of a multiphase balanced power supply.

[Industrial Field of Application] The present invention relates to a superconducting circuit, and particularly to the configuration of a superconducting circuit in which a predetermined logic is realized by combining a plurality of Josephson junction elements in a multilayer structure.

In recent years, there have been many reports of high-speed operation of integrated circuits using niobium-aluminum oxide-niobium (Nb/alo, /Nb) junctions as Josephson elements. In addition to bonding, interlayer insulating films made of silicon dioxide (SiO□) and resistors made of molybdenum (Mo) are used, and progress has also been made in planarization technology that uses bias sputtering to use SiO□ films as insulating films between the eyebrows. However, it has become possible to fabricate Josephson junctions with multilayer structures.

[Prior Art] In a logic circuit using a Josephson junction element, the element is connected to a multiphase power supply (in many cases, a three-phase sine wave with an offset).
A method of driving using phase power (phase power) is used. The necessity of using the three-phase power supply driving force type will be explained below with reference to FIG.

Figure (a) is a perspective view of the structure of a magnetically coupled Josephson junction element, in which 31 is a silicon (Si) substrate;
32 is the ground plane of Nb, 33 is Nb
34 is a tunnel insulating film of AIO, 35 is a base electrode of
36 is the Nb counter electrode, 36 is the Nb input signal line, 1.1 is the bias current, and IC is the input current for applying a magnetic field to the Josephson junction (the part J indicated by the broken line in the figure). . Note that insulating layers between superconducting films, such as between a ground plane and a base electrode, are omitted from the illustration. FIGS. 3(b) and 3(c) are equivalent representations of a Josephson junction element, and the portion marked with an x in the figure corresponds to the Josephson junction J. Further, 37 is a load resistor, which is not shown in the figure (a), but is used to flow an input current to apply a magnetic field to the junction of the Josephson junction element to be connected in the next stage. It will be done.

As shown in the same figure (b), the input current ■. When is O,
Since the critical current in the Josephson junction J does not change, the Josephson junction element is in a "zero voltage state". In this state, the bias current is ■.

is substantially only at this junction - flow (Il=Ill)
, no current flows through the load resistor 37. On the other hand, the same figure (c)
A predetermined input current 1c is applied to the input signal line 36 as shown in FIG.
, a magnetic field is applied to the Josephson junction J, changing the critical current of the junction and switching the Josephson junction element to a "voltage state". As a result, a very small amount of the current (1) of the bias current I flows through the junction, and most of the current (2) () I+) is shunted to the load resistor 37. This shunted current I2 is used as an input current for applying a magnetic field to the junction J° of the Josephson junction element connected to the next stage.

The Josephson junction element applies a predetermined input current to the input signal line 36 when transitioning from the "zero voltage state" to the "voltage state". However, when transitioning from a "voltage state" to a "zero voltage state," it is not enough to simply set the input current I to 0; the bias current In itself must be reduced to a predetermined value or less. It is necessary to do so. however,
When the bias current decreases, data held in the Josephson junction to which the bias current was supplied is inconveniently lost. To deal with this, it is necessary to provide a data holding circuit such as a latch circuit on the chip to hold the data. However, such a circuit is not desirable because it not only complicates the overall circuit configuration on the chip but also increases the space occupied on the chip.

In view of these circumstances, the above-mentioned three-phase power supply driving force type is adopted. As illustrated in FIG. This is a method for driving a functional block unit (a functional block unit formed by combining elements is called a gate).

For example, as shown in FIG. 5 as an example of the conventional type,
Sine wave currents φ1, φ2 are applied as bias currents to the gates 51, 52, 53, and 54 connected in a chain, respectively.
, φ3, φ1, . . . are supplied.

Referring to the fourth leap, when the bias current φ decreases and the data held in the gate 51 receiving the bias current is about to be lost at time tl, the data is supplied to the gate 52 of the next stage. Since the current bias current φ2 has increased beyond a predetermined amount, the output of the gate 51, that is, the data that is about to be lost, is shifted to the gate 52 and held. Similarly, at point 2, data is shifted from gate 52 to gate 53 and held. Furthermore, at the time t3, the bias current φ1 is applied from the gate 53.
The data is shifted to gate 54 which is supplied with
Retained. Thereafter, the original data is sequentially shifted within the gate in the same manner.

Therefore, by driving the Josephson junction element (gate) with a three-phase power supply, there is no need to provide a latch circuit between the gates. Furthermore, since the total amount of bias current φ, ~φ, supplied to each gate is constant and does not vary over time, the total amount of current flowing into the ground plane where each gate is formed is also constant, and the voltage of the ground plane The level remains constant and stable.

[Problems to be Solved by the Invention] In the conventional three-phase power supply driving force type described above, in order to keep the total amount of current flowing into the ground plane constant and stabilize the voltage level of the ground plane, it is necessary to The phase of bias currents φ1 to φ3 is exactly 12 on the chip.
It is absolutely necessary that they are shifted by 0°.

As shown in Figure 6, the superconducting circuit formed on the chip is kept in liquid helium at a low temperature (e.g. -4.2K) and placed at room temperature when performing gate tests and measurements. It is designed to receive three-phase current from the connected power supply. Conventionally, the phase of each phase was adjusted at the output of the power supply placed at room temperature, or the phase was adjusted on the power supply side to minimize fluctuations in the ground potential of the chip placed in liquid helium. Was. However, this adjustment is only a phase adjustment at the position of the power source input section (pad) formed on the chip. Chips may also be cooled using a refrigerator.

Therefore, as shown by way of example in FIG.
If the lengths of the power supply lines from each pad P1 to P to the corresponding gate 51 to 53 are different within the chip, a phase delay will occur in each current waveform within the chip, so the true It becomes impossible to perform phase matching from outside the chip. In other words, the total amount of current flowing from each gate to the ground pad P0 via the ground plane may vary over time, which causes the problem that the voltage level of the ground plane becomes unstable. This is not desirable because it can sometimes cause malfunctions in the superconducting circuit formed on the ground plane.

The present invention was created in view of the problems in the prior art, and minimizes the power supply phase shift between each gate driven by the current of the corresponding phase of a multiphase power supply, and superconducting ground plane (ground). The purpose of the present invention is to provide a superconducting circuit that can suppress temporal fluctuations in the voltage level of the plane.

[Means for Solving the Problems] In order to solve the problems in the prior art described above, a superconducting circuit according to the present invention includes a superconducting ground plane and a plurality of Josephson junction elements combined with the superconducting ground plane. A circuit with a layered structure including at least one gate configured as a multilayer circuit has a structure in which multiple layers are stacked on a chip, and the superconducting ground planes of each layer have contact portions with each other so that they have a common potential. The gates of each layer are arranged at corresponding positions such that the wiring lengths from the power input section formed on the chip are approximately the same, and the gates are connected through the power input section. They are driven by currents of corresponding phases of a multiphase balanced power supply that are mutually shifted by a predetermined phase difference.

[Function] The gates of each layer stacked on the chip are placed at corresponding positions so that the wiring lengths from the power input section on the chip are approximately the same, so that the power supply to each gate is The phase shift that occurs between the respective drive currents can be minimized. As a result, the sum of the currents of the multiphase balanced power supplies corresponding to the gates of each layer becomes approximately constant, and temporal fluctuations in the voltage level of the superconducting ground plane can be suppressed. This contributes to increasing the reliability of the operation of the superconducting circuit formed on the superconducting ground plane.

(Embodiment) FIG. 1 is an exploded perspective view of the arrangement of gates constituting a superconducting circuit according to an embodiment of the present invention.

The circuit of this example uses a superconducting ground plane (ground plane)
A Josephson circuit with a layer structure having three layers is stacked on a chip, and a Nb/Al0X/Nb Josephson junction as shown in Fig. 3 is used for the junction, and bias sputtering is used to A three-layer Josephson circuit is realized by using a 5i (h film) as an interlayer insulating film.The Josephson circuit in each layer is composed of a combination of multiple gates, and each gate is composed of multiple gates. It is constructed by combining Josephson junction elements.

In FIG. 1, S indicates a Si substrate, that is, a chip;
Power supply pads p, -p, and ground pad P0 are formed around the chip. Power pads P1-P,
are supplied with sinusoidal currents φ1 to φ3 of a three-phase balanced power supply with DC offset, which are phase-shifted by 120° from each other as shown in FIG. 4, respectively.

CP, -GP, and l each represent a Nb ground plane, and Gll to Gffl each represent a gate forming a part of the Josephson circuit of each layer, which is formed for the corresponding ground plane. Further, C3 to C3 indicate contact portions for connecting the ground planes of each layer to each other, and the ground planes GPI to GP of each layer are connected to the ground pads P0 on the chip via the contact portions.
It is connected to the. In the example shown in Figure 1, insulating layers between superconducting films, such as between the base electrode of the Josephson junction element constituting the gate and each ground plane, are omitted to simplify the explanation. .

FIG. 2 schematically shows the gate connection form in FIG. 1.

As shown in the figure, the ground plane GP.

~Games formed respectively for GP3) Gz~G3
1 are the predetermined wiring lengths L-J! from the corresponding power supply pads P, ~P3, respectively. , and are supplied with three-phase balanced pressure sinusoidal currents φ1 to φ having mutually different phases. When arranging each gate G11 to G31, each wiring length I! Care must be taken to ensure that 1 to 13 are the same. As for the signal flow, the output of the gate Gz, which is supplied with the power supply φ, is output from the gate G2, which is supplied with the power supply φ2. Furthermore, the output of the gate Gz+ is input to the gate island, which is supplied with the power supply φ, and the output of the gate Gz+ is input to the gate island, □, which is supplied with the power supply φl. has been done. Thereafter, in the same way, the power supply phase order φ, → φ2 → φ3 → φ1 →...
The gates are connected in a chain according to...

As described above, in this embodiment, a Josephson junction device with a layered structure consisting of one gate and a ground plane corresponding to the gate is constructed by appropriately combining Josephson junction elements having the structure shown in FIG. Son circuit,
The SiO□ film produced by bias sputtering is used as an interlayer insulating film to form three layers using planarization technology, and the gates of each layer are connected to each other so that the wiring length from the power supply pad formed on the chip is approximately the same. In addition, since each gate is driven by a three-phase balanced power supply, it is possible to minimize the phase shift that occurs between the respective currents supplied to each gate within the chip. the result,
The total sum of currents flowing into each ground plane remains approximately constant over time. In other words, temporal fluctuations in the voltage level on the ground plane can be suppressed to a minimum, which can contribute to preventing circuit malfunctions.

Although the above-mentioned embodiment describes the case where each gate is driven by a three-phase balanced power supply, the present invention is not limited thereto, and is also applicable to multiphase power supply driving systems other than three-phase.

〔Effect of the invention〕

As explained above, according to the present invention, the power supply phase shift between the respective gates driven by the currents of corresponding phases of the multiphase power supply is minimized, and temporal fluctuations in the voltage level of the ground plane are suppressed. can do. this is,
This contributes to stable operation of the circuit formed on the ground plane without malfunction.

[Brief explanation of the drawing]

FIG. 1 is an exploded perspective view showing the arrangement of gates constituting a superconducting circuit according to an embodiment of the present invention, FIG. 2 is a diagram schematically showing the connection form of the gates in FIG. 1, and FIG. (a) to (c) are diagrams for explaining the action of the Josephson junction element, Figure 4 is a waveform diagram of the three-phase power supply for driving the gate, and Figure 5 is a schematic diagram of the gate connection form in the conventional type. FIG. 6 is a diagram showing a form of supply of gate driving power, and FIG. 7 is a plan view showing an example of the arrangement form of gates in FIG. 5. (Explanation of symbols) GIl+G! I+G31...Gate, GP+,
Gh, GPi...superconducting ground plane, S...chip, CI+C! +C1...Contact part (on superconducting ground plane), Pl, Pz, P3...Power input part (on chip),! 8, 2□, 2. ...Wiring length, φ1. φ2. φ3...Current of each phase of multiphase balanced power supply. Figure 1 Gate + P1 + P2, P3... Bad Figure 2 A diagram schematically showing the connection form of gates in Figure 1 Figure 4 A diagram schematically showing the connection form of gates in the conventional type Figure 5 Power diagram showing the supply form of gate drive power supply

Claims (1)

[Claims] A superconducting ground plane (GP_1, GP_2, GP_3) and at least one gate (G_1) configured by combining a plurality of Josephson junction elements with respect to the superconducting ground plane.
It has a structure in which a plurality of layered circuits (C_1, G_2_1, G_3_1) are stacked on the chip (S), and the superconducting ground planes of each layer are connected to each other at contact portions (C_1) so that they have a common potential. , C_2, C_3), and the gate of each layer has a wiring length (l_1,
Currents of corresponding phases (φ_1 , φ_2, φ_3).