JPH0220178B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention compresses, for example, a 10-bit pulse code modulation (hereinafter referred to as PCM) signal to 8 bits, or converts 8 bits to 10 bits by polygon processing. The present invention relates to a companding processing circuit for decompressing.

[Technical background of the invention]

A helical scan video tape recorder (hereinafter referred to as
In the so-called 8mm VTR (referred to as VTR),
Recording of PCM audio signals is considered as an option. In this case, the PCM audio signal is recorded on an extension of the video track.
That is, the winding angle of the tape around the cylinder is greater than the angle of one head, a period is provided in which a plurality of heads are in contact with the tape at the same time, and a PCM audio signal is recorded during this period.

Although the audio signal recorded on magnetic tape is 8 bits, the dynamic range equivalent to 10 bits is obtained through companding conversion using fold line processing.

FIG. 3 is a circuit diagram showing the digital processing part of the recording and reproducing system of audio signals recorded in PCM.

In FIG. 3, to first explain the recording system circuit, an analog audio signal applied to a terminal 11 is input to an analog/digital conversion circuit 12,
It is converted into bit digital data. and,
The data is compressed into 8-bit digital data by the 10-bit/8-bit linear compression processing circuit 13. This 8-bit digital data is processed by the recording processing circuit 14 to add an interleaf and an error correction detection code, and then subjected to predetermined modulation according to the tape format. Record this signal Amplifier circuit 1
The signal is amplified at step 5 and recorded on the magnetic tape 17 at the head 16 at an optimum recording current.

Next, to explain the reproduction system circuit, the head 16
The electric signal extracted from the regenerative amplifier circuit 18 is amplified. Then, in the reproduction processing circuit 19,
After being subjected to demodulation, deinterleaving, and error correction, it is extracted as 8-bit digital data. This 8-bit digital data is 8-bit/
The data is returned to 10-bit digital data by the 10-bit polygonal line expansion processing circuit 20. This data is digital/
It is converted into an analog signal by an analog conversion circuit 21 and guided to a terminal 22.

8-bit and 10-bit companding processing is performed as follows. 10-bit digital data can represent numerical information (+511 to -512) in decimal notation. In order to represent this in 8 bits (+127 to -128), the whole is divided into seven ranks and the companding process is performed. The closer the companding ratio is to 0, the lower it is, and the farther it is from 0, the higher it is. The basic compression method is that when a binary number has a large number of digits, the lower digits are truncated to 8 bits. Here, -3 from the minimum value
〜+3 (including 0) is named as 7th rank.

First, compression processing during recording will be explained. 0 rank is -
In the range of 16 to +15 (1111110000 to 0000001111),
The lower 8 bits of the numerical value during this period are simply output,
No processing will be done. Therefore, even with 8 bits, -
16 to +15 (11110000 to 00001111).

+1 Ranko is +16~+63 (0000010000~
0000111111), where the LSB is truncated. If you truncate and output the lower 8 bits,
+16 becomes +8, which is the same data as 0 rank. To prevent this and make full use of 8-bit data, 8 is also added as a correction number. Therefore, an 8-bit digital signal is +16 to +39 (00010000 to
00100111). -1 rank is -17 to -64
(1111101111 to 1111000000), undergoes the same processing as +1 rank except that the correction number is -8. Therefore, the output is −17 to −40 (11101111 to
11011000).

+2 rank is +64~+319 (0001000000~
0100111111), and here the lower two bits are truncated. The number of corrections added is 24, and the resulting 8-bit data output is +40 to +
103 (00101000 to 01100111). -2 rank is in the range of -65 to -320 (1110111111 to 1011000000), and the processing here is the same as the processing for +2 rank except that the correction number is -24. Therefore, the output 8-bit data is -41 to -104 (11010111 to
10011000).

+3 rank is +320~+511 (0101000000~
0111111111), the bits to be truncated are the lower three digits, and the correction number is also large, +64. As a result, the output 8-bit data is +104 to +127
(01101000 to 01111111). -3rd rank is-
In the range of 321 to −512 (1010111111 to 1000000000),
It receives the same processing as +3 rank except that the correction number is -64. The 8-bit data thus output is -
105 to −128 (10010111 to 1000000).

During playback, the reverse processing to that during recording is performed. That is, the correction number is subtracted after carrying. In this case, it is not possible to reproduce the lower bits that have been truncated from the null information, so all 0s are determined and reproduced for the truncated bits.

Next, the conventional compression processing circuit 13 and decompression processing circuit 20 will be explained with reference to FIGS. 4 and 5, respectively.

First, in FIG. 4, serial 10-bit audio PCM data is input from the input terminal 25,
The serial/parallel conversion circuit 26 stores the data as parallel data. Here, the bit string is a
LSB (least significant bit), j is MSB (most significant bit)
and are arranged in digit order.

The upper 6 bits of this 10-bit input data are input to a rank determination circuit 27, and the seven ranks of the input data are determined. According to this judgment result, the selection circuit 28 operates 8-digit switches in conjunction to select 10 digits of the bit string to be output data.
By selecting bits from the bit string of the input data, the above-mentioned process of truncating lower bits is performed. The adder circuit 29 sets a correction number according to the above-mentioned rank determination result, and adds it to the data set to 8 bits by the selection circuit 28. As a result, compressed 8-bit audio PCM data is obtained. This parallel 8-bit data is converted into serial data by the parallel/serial conversion circuit 30, and the LSB " a” is output.

Next, the decompression process will be explained using FIG. The reproduced 8-bit serial data is applied from an input terminal 35 to a serial/parallel conversion circuit 36, where it is converted into parallel data. The upper 5 bits of this 8-bit input data are input to a rank determination circuit 37 to determine the rank. The addition circuit 38 sets a correction number according to the judgment rank, and performs a process of subtracting this from the input data. The selection circuit 39 expands the corrected and added input data by adding bits to obtain 10-bit parallel data. This parallel data is converted into serial data by the parallel/serial conversion circuit 40, and is output from the output terminal 41 from the LSB "a".

[Problems with background technology]

By the way, when comparing the compression processing circuit of FIG. 4 with the decompression processing circuit of FIG. 5, many circuits perform similar functions, as can be seen in the addition circuit 29 and the addition circuit 38, for example. Therefore, it is desirable to have one circuit for each circuit and use it for both compression processing and decompression processing.

However, conventionally, the order of calculation of correction numbers and processing of lower bits in compression processing and decompression processing is reversed, and the latter bit processing is performed by parallel processing of data, so the selection circuit that executes this is Due to the fact that the wiring of the selection circuit 28 and the selection circuit 39 are completely different, it has been impossible to realize companding processing and decompression processing with the same circuit.

[Purpose of the invention]

The present invention has been made to address the above-mentioned circumstances, and an object of the present invention is to provide a companding processing circuit that can perform both compression processing and decompression processing in one circuit.

[Summary of the invention]

The present invention combines correction number arithmetic processing such as addition of correction numbers in compression processing and subtraction of correction numbers in expansion processing, and bit processing such as truncation of lower-order bits in compression processing and addition of lower-order bits in expansion processing. The aim is to realize compression processing and decompression processing in one circuit by setting this before the .

Therefore, the correction number added in the compression process is carried forward in consideration of the lower pit, so that this addition process can be performed before the bit truncation process. Further, by serially performing the above-mentioned bit processing on the data for which the correction number has been calculated, the same circuit can perform bit truncation during compression and bit addition during expansion. That is, a parallel/serial conversion main stage is provided which stores data in parallel after which the correction number has been calculated, and serially outputs the data while shifting it downward. At the time of compression, the data to which the correction number has been added is stored. When expanding,
Data with the same number of bits as the maximum number of bits to be cut off during compression is added to the lower part of the data from which the correction number has been subtracted. Each bit of this additional data has the same binary value, and when outputting the parallel data obtained in this way serially, by setting its LSB according to the rank determination result, the above This realizes bit processing. In this case, the number of lower bits of the parallel data that is the target of LSB selection is one more than the maximum number of truncated bits.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 and FIG. 2 are circuit diagrams showing the configuration of one embodiment, and show a compression processing mode and an expansion processing mode, respectively.

In FIG. 1, first, the compression processing operation during recording will be explained. The input terminal 45 has a 10-bit
PCM signal is serial data (a to j from the bottom)
is entered as . This serial data is converted into parallel data by a 10-bit serial/parallel conversion circuit 46. The rank determination circuit 47 determines the rank of the parallel data using the upper six bits of the parallel data. This determination result is sent to the adder circuit 48 and the LSB selection switch circuit 51.

The adder circuit 48 sets a correction number in order to avoid overlapping of numerical values between ranks due to the above-described truncation of the lower bits, and adds this to the parallel data, according to the above-mentioned determination result. In this case, the correction number to be added is carried in the form of a carry by the number of bits to be truncated, because unlike the conventional circuit described above, this addition process is performed before the truncation process of the lower bits. For example, the correction number for +3 rank is +64, as described above. This 2
When expressed in base numbers, the 7th digit "g" is 1. However, since the lower 3 bits will be discarded later, in the present invention, the above addition process is performed so that 1 is added to the 10th digit "j" which is three digits higher. This is not a problem because cutting off the lower 3 bits in binary system means dividing by 8 in decimal system, so it is equivalent to multiplying the number added after the division by 8 and adding it before the division. . Note that when the numerical value is negative, overflow occurs, so an overflow bit is prepared for the output bits of the adder circuit 48, and a total of 11 bits (from a to
k).

The 11-bit parallel data obtained in this way is sent to the 11-bit parallel/serial converter circuit 5.
It is input to 0. A switch circuit 49 is inserted between the lower three bits of the adder circuit 48 and the lower three bits of the parallel/serial conversion circuit 49. This switch circuit 49 includes three switches 491 to 493, which are shown as mechanical switches for convenience.
has. Each of the switches 491-493 corresponds to the lower three bits of the 11-bit data. In the compression process, each switch 491 to 4
The movable contacts x 93 are all connected to the fixed contact y, and the data of the lower three bits "a" to "c" are input to the parallel/serial conversion circuit 50 via switches 491 to 493, respectively.

The number of switches in the switch circuit 49 corresponds to the maximum number of bits to be truncated in the compression process, in this example, 3 bits to be truncated at ±3 ranks.

stored in the parallel/serial conversion circuit 50
The LSB of the 11-bit parallel data is set appropriately by the LSB selection switch circuit 51, and this LSB
The high-order bit parallel data including the 8-bit compressed PCM signal is serially led to the output terminal 52.

That is, the switch circuit 51, which is shown as a mechanical switch for convenience, has four fixed contacts q ₁ to _{q 4} connected to the lower four bits of the parallel/serial conversion circuit 50. And rank determination circuit 47
The movable contact piece p is connected to any one of the fixed contacts q ₁ to _{q 4} according to the rank determined in , and the bit corresponding to the connected fixed contact is selected as the LSB. For example, when the movable contact p is connected to the fixed contact q ₁ , the compressed PCM signal is
The lower 8 bits of data a to h are output, with a being the LSB. This corresponds to 0-rank processing because the lower bits are truncated to 0, that is, the lower bits are not truncated. When connected to the fixed contact _q2 , the output is 8 bits b to i, and a is truncated. When connected to fixed contact _q3 , the output is 8 bits c to j, with two digits a and b being truncated. For the connection to fixed contact q ₄ , the output is d
~k is 8 bits, and 3 digits 1a~c are truncated. In this way, compression processing is performed by truncating the lower bits of ranks 0, ±1 to ±3, and an 8-bit PCM signal is output from the output terminal 52 as serial data.

In the switch circuit 51, the number of fixed contacts connected to the lower bits is one more than the maximum number of bits to be discarded.

Next, the decompression process during playback will be explained using FIG. In this case, processing is performed in the same flow as the compression processing, except that the processing of each circuit is slightly different from the previous compression processing.

That is, the reproduced 8-bit serial
The PCM signal is inputted from an input terminal 45 to a serial/parallel conversion circuit 46 and converted into 8-bit parallel data. The rank determination circuit 47 then:
The rank of this parallel data is determined using the upper bits of the 8-bit parallel data. The adder circuit 48 sets a correction number according to the determined rank and adds it to the 8-bit parallel data.
The number of corrections in this case is the inverse of the number of corrections added in the compression process (however, the number of corrections without carry). That is, in this expansion process, the addition circuit 48 essentially performs an operation of subtracting the correction number added in the compression process.

In this way, the 8-bit parallel data from which the correction number has been subtracted is input to the upper 8 bits of the 11-bit parallel/serial conversion circuit 50. In addition, each switch 491 of the switch circuit 49
The movable contact pieces x of ~493 are connected to the fixed contact z. Therefore, the lower three bits of the parallel/serial conversion circuit 50 are each set to a binary value, in the case shown, "0".

The LSB selection switch circuit 51 selects one of the lower 4 bits of the 11-bit parallel data thus obtained as the LSB.
It is output from the output terminal 52 as 10-bit serial data. That is, when the determination result of the rank determination circuit 47 is 0 rank, the movable contact p is connected to the fixed contact _q4 , and d is selected as the LSB. In this case, 10-bit decompressed serial data is obtained as "kkkjihgfed" by repeating k three times. For binary numbers, all digits greater than numerical information (for example, "15" is "1111" and up to 4 digits are numerical information) are all "0" when positive, and "1" when negative. be. Therefore, since numerical information is not entered for 6 digits or more in the 0 rank, there is no problem even if the above-mentioned processing is performed. In the ±1 rank, the movable contact p is connected to terminal q ₃ , and “c” is the LSB.
is selected. As a result, "0" is added to the LSB, and 10-bit data "kkjihgfedc" is serially output. Similarly, in the ±2 rank, the movable contact p is connected to the fixed contact q ₂ , and "0" is added to the lower two bits "cb" to make "kjihgfedcb" 10
Bit data is output. In the ±3 rank, the movable contact p is connected to the fixed contact q ₁ , and "0" is added to the lower 3 bits "cba", resulting in "jihgfedcba".
10 bit data is output. In this case, “k”
is truncated, but this is not a problem for the following reasons. In other words, the data of ±3 ranks is
In the compression process, the lower 3 bits are discarded to essentially become 7 bits, and the MSB(k) of the 8-bit data obtained by the compression process does not contain any information, so there is no problem.

In this manner, the switch circuit 51 serially obtains a 10-bit expanded PCM signal by adding the lower bits that were discarded during the compression process during the expansion process.

As described in detail above, according to this embodiment, compression processing and decompression processing can be performed in one circuit, so that the circuit scale can be halved compared to the conventional companding processing circuit.

In addition, since the truncation and addition of lower bits are not processed serially, the circuit configuration is simplified, and the complicated wiring required when performing the above processing in parallel, as seen in the conventional selection circuits 28 and 39, is simplified. do not need.

Furthermore, the number of switches used in the switch circuits 49, 51 is considerably smaller than the number of switches used in the conventional selection circuits 28, 39, and a reduction in the number of elements can be expected as a result.

As a result of the above-mentioned effects, it is expected that the circuit pattern will be simplified and the chip size of the integrated circuit will be reduced, leading to a significant cost reduction when integrating the circuit. In addition, bit processing is performed on the correction number after arithmetic processing, and the latter bit processing is performed by LSB selection processing by the switch circuit 51. Therefore, the structure is such that the correction number is subjected to arithmetic processing after the bit processing. The overall processing time can be shortened compared to . That is, when subtracting a younger positive number after bit processing, the bit processing and parallel/serial conversion processing must be performed independently. In contrast, in this embodiment, parallel/
By performing serial conversion, bit processing can be performed as a result, so time dedicated to bit processing is no longer required, and the overall processing time can be reduced accordingly.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and various other modifications can be made without departing from the gist of the invention.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a companding processing circuit that can be used for both compression processing and decompression processing.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of an embodiment of the present invention, particularly showing the compression processing mode, FIG. 2 is a circuit diagram similarly showing the decompression processing mode, and FIG.
A circuit diagram showing the overall configuration of a conventional PCM processing circuit in mmVTR, Figure 4 is a circuit diagram showing the configuration of the compression processing circuit shown in Figure 3, and Figure 5 is a circuit diagram showing the configuration of the decompression processing circuit. It is. 45...Input terminal, 46...Serial/parallel conversion circuit, 47...Rank determination circuit, 48...
Adder circuit, 49... switch circuit, 50... parallel/serial conversion circuit, 51... LSB selection switch circuit, 52... output terminal.

Claims (1)

[Claims] 1. By dividing the PCM signal into a plurality of ranks according to their levels, and setting the number of lower bits to be cut off according to the ranks and the correction number to prevent numerical overlap between ranks, By processing the above
In the companding processing circuit that compresses the PCM signal and expands the compressed PCM signal, there is a serial/parallel converter that outputs the serially input PCM signal in parallel, and the serial/parallel converter converts the PCM signal into parallel data. This based on the converted PCM signal
A rank determining means for determining the rank of a PCM signal, and a correction number corresponding to the rank determined by this rank determining means, are used for the serial/compression processing during compression processing.
It is added to the PCM signal converted to parallel data by the parallel conversion means, and this PCM signal is added during decompression processing.
An arithmetic means for subtracting from the signal, a parallel/serial conversion means that stores the PCM signal output from this arithmetic means in parallel, and outputs the stored data serially while shifting it downward; and the above during compression processing. output from the calculation means
A PCM signal is input to the parallel/serial conversion means, and during decompression processing, data is output from the calculation means with the same number of bits as the maximum number of bits that can be discarded during compression processing, and the same binary value is set for each bit. an input switching means that adds the lower part of the PCM signal to be input to the parallel/serial converter, and sets the LSB of the serial data output from the parallel/serial converter to one lower bit than the maximum number of bits to be truncated. and LSB selection means for selecting an LSB from among them according to the rank determined by the rank determination means, and configured such that the correction number added in the compression processing is carried in accordance with the number of truncated bits. A companding processing circuit characterized by: