JPH0220183B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a digital clock supply device (DCS) that supplies clocks to digital terminal devices that operate in synchronization with each other, and particularly relates to a digital clock supply device (DCS) that supplies clocks to digital terminal devices that operate in synchronization with each other.
This invention relates to a clock selection method that makes it possible to economically select the input clock dependent destination of a DCS.

(b) Prior art and problems When digital terminal equipment operates in synchronization with each other, a clock is supplied to the digital terminal equipment.
The DCS of the slave station is equipped with a DCS and supplies a clock that is synchronized with the clock of the master station.The DCS of the slave station receives multiple clocks transmitted from the master station via the transmission path, and has a clock selection switching circuit that selects one of them. I have it.

FIG. 1 is a block diagram showing an example of a clock selection switching circuit.

For example, eight 8KHz clocks are input from the transmission line from terminals CLK0 to CLK7, one of them is selected by switch 1, and when this one clock stops due to a failure, it switches to another valid clock. Until then, the signal is sent out from the terminal CLK via the AND circuit 11 which cuts off the circuit so as not to send out noise or the like.

At the same time, from the terminals REC0 to REC7, the 8K
The input abnormality detection results of the Hz clocks are input to eight protection circuits 5, each corresponding to the corresponding clock. The switch 2 operates in conjunction with the switch 1 based on the output of the priority setting circuit 10 which operates as described later, and outputs the input abnormality detection result of the clock selected by the switch 1 and sent from the terminal CLK to the terminal REC. It is sent as alarm information.

The protection circuit 5 sends forward protection and backward protection signals, respectively, based on the result of the clock input abnormality detection result. The forward protection signal has a clock of 8, for example.
If the abnormal state continues for more than a second, it is a signal that is determined to be a complete failure, and a momentary interruption shorter than that is recognized as a failure and is a protection signal that prevents the clock transmission path from being switched.

The rear protection signal is a signal that recognizes recovery when the clock has recovered from an abnormal state, for example, when the clock has been detected for 0.5 seconds or more.

The forward protection signals are each sent to a priority setting circuit 10. The priority setting circuit 10 uses a forward protection signal to set priority when switching the transmission path of the clock determined to be faulty, that is, the clock of the transmission path corresponding to terminals CLK0 to CLK7, to the clock of the transmission path where no fault has occurred. Set the ranking.

Normally, this priority is set in ascending order of the number, so for example, if terminal CLK0 becomes a failure, terminal CLK1 is set to be selected. This selection signal is sent to switch 8 and switches 1 and 2, and switch 1 and 2 operate as described above.

Further, the switch 8 sends the backward protection signal sent from the protection circuit 5 to the AND circuit 11, and as described above, the AND circuit 11 sends out the clock of the transmission line specified by the priority setting circuit 10. The output of the switch 1 is sent to the terminal CLK, and when the backward protection signal notifies the detection of a clock input abnormality, the output of the switch 1 is cut off.

64Hz working signal from terminal N, 64Hz from terminal E
The switch 4, which operates with the control signal input from the terminal ACT, selects the current or standby signal.
Hz is sent to frequency divider 6. The frequency divider 6 then supplies an operation timing signal for the protection circuit 5 to recognize the 8 seconds and 0.5 seconds as described above.

FIG. 2 is a detailed block diagram of the protection circuit 5 shown in FIG. 1.

FIG. 2 shows, for example, the circuit connected to the terminal REC0 as a representative among the eight circuits shown in FIG. A clock input error signal is input to terminal REC0. This signal sets the flip-flop 17, and the forward protection circuit 18 operates to check whether the input abnormality detection signal continues for 8 seconds.

When the output of the flip-flop 17 continues for 8 seconds, the forward protection circuit 18 sets the flip-flop 19, so that the flip-flop 19 is connected to the terminal.
Send forward protection signal from FP. That is, it is sent to the priority setting circuit 10 in FIG.

When the flip-flop 17 is set, the terminal of the flip-flop 17 becomes “0”.
The output of the NOT circuit 20 becomes "1", the backward protection signal is stopped, and the AND circuit 11 of FIG. 1 is turned off. That is, since the switch 1 continues to send out the output of CLK0 for 8 seconds, unnecessary signals such as noise from the output of the switch 1 are prevented from being sent to the terminal CLK due to a clock failure.

When the input abnormality detection signal of terminal REC0 stops,
Since the output of the NOT circuit 15 becomes "1", the backward protection circuit 16 operates and resets the flip-flop 17 if it continues for 0.5 seconds. Therefore, the forward protection circuit 18 is stopped and the flip-flop 19 is also reset. Also, the output of the NOT circuit 20 is “0”
Then, the rear protection signal is sent from the terminal BP, and the AND circuit 11 shown in FIG. 1 is turned on. Therefore, the restored clock is sent out from the terminal CLK.

Frequency divider 6 in Figure 1 sends out from terminal TM.
The 0.5 second operation timing signal is the rear protection circuit 1.
6 and enters the forward protection circuit 18.

Conventionally, this protection circuit 5 is required for each clock transmission path. That is, the terminals REC0~ in Figure 1
As shown in REC7, if you input 8 clocks,
Eight protection circuits 5 are also required. Therefore, eight sets of hardware as shown in Fig. 2 are required, which poses a problem that the amount of hardware is large and is not economical, and there is also a problem that there is no degree of freedom when changing the control method due to the hardware configuration. There is.

(c) Purpose of the invention In order to eliminate the above-mentioned drawbacks, the purpose of the present invention is to simplify the hardware by converting the algorithm and protection conditions for switching the clock transmission path into software, storing it in ROM, and performing multiple processing. , and to provide a clock selection method that is versatile.

(d) Configuration of the Invention The configuration of the present invention is such that an input abnormality detection signal is continuously sent out for a predetermined period of time corresponding to a plurality of clocks to notify that each clock has entered an abnormal state. When the input abnormality detection signal stops being transmitted for a certain period of time within the predetermined time period, the switching signal is transmitted from the main station via multiple transmission paths by blocking the transmission of the switching signal. A switching circuit that controls a switching means for switching the transmission line to select a normal clock from among the clocks that are input, samples the plurality of input abnormality detection signals within the certain period of time, and selects a normal clock from among the input abnormality detection signals. an extraction means for sequentially extracting the input abnormality detection signal one by one, and determining whether or not the input abnormality detection signal extracted by the extraction means continues for the predetermined period in a time-sharing manner corresponding to the number of transmission paths; determining means for transmitting the switching signal when the input abnormality detection signal continues for the predetermined period of time; and means for supplying the switching signal transmitted by the determining means to the switching means in a time-sharing manner;
A plurality of input abnormality detection signals sent out corresponding to the plurality of clocks are taken in in a time-division manner, and a normal clock is selected by one of the judgment means.

(e) Embodiment of the Invention FIG. 3 is a block diagram of a circuit showing an embodiment of the invention, and FIG. 4 is a detailed block diagram of the protection circuit 5 shown in FIG.

In FIG. 3, the same symbols as in FIG. 1 indicate the same functions. The present invention allows one circuit to process the operations of a plurality of protection circuits by operating the protection circuit 5 in a time-division manner.

Input abnormality detection signal input from terminals REC0 to REC7,
The protection circuit 5 is sequentially switched by the multiplexer 3.
The forward protection signal sent from the protection circuit 5 is converted into a parallel signal by the serial/parallel converter 9 and sent to the priority setting circuit 10.

Further, the rear protection signal sent from the protection circuit 5 is converted into a parallel signal by the serial/parallel converter 7 and sent to the switch 8. The other operations are the same as in FIG. 1.

The operation shown in FIG. 4 will be explained. Switching circuit 4 in Figure 3
The 64 Hz signal enters the 1/4 frequency divider 25 of the frequency divider 6 from the terminal B via the 16 Hz signal is sent to the flip-flop 28. Also, this 16Hz signal is divided into a 2Hz signal by a 1/8 frequency divider 26 and then
27 address terminals A0, A1, and A2. That is, by specifying 8 types of addresses using 3 bits, the input abnormality detection signals of the 8 transmission lines sent from the multiplexer 3 shown in FIG.

That is, the multiplexer 3 uses the 16Hz output from the 1/4 frequency divider 25 of the frequency divider 6 to
REC0 to REC7 by switching the 8 transmission lines sequentially.
The state can be written/read in the RAM 27 in response to the input abnormality detection signal that is circulated and sent to the RAM 27.

The flip-flop 28 is composed of eight D flip-flops, and operates at 16Hz.
In order to detect a change in the state of one input abnormality detection signal in the transmission line at 0.5 second intervals, data is read from the RAM 27, held, and sent to the ROM 29. Then, the data processed in ROM29 is transferred to RAM27.
write to. Therefore, the flip-flop 28 is
It holds the previous state processed by the ROM 29 and also serves as a buffer for writing the data processed by the ROM 29 to the RAM 27.

From the terminal CREC, the input abnormality detection signal sent from the multiplexer 3 shown in FIG.

FIG. 5 is a state transition diagram in which the ROM 29 processes the input abnormality detection signal.

The flag bit corresponding to the rear protection signal is FA, and the flag bit corresponding to the forward protection signal is FB.
shall be. When an input abnormality is detected, the flag bit is set to "1", and when normal, it is set to "0". Further, if the current state, that is, the bit indicating whether the input is abnormal or normal, is R, then R
It is assumed that when R is "1", an abnormal input state is occurring, and when R is "0", it is normal.

Under normal conditions, both FA and FB are “0”. When an abnormal input state occurs in a certain transmission line, that is, one of the terminals REC0 to REC7, R becomes "1". Therefore, FA of the corresponding transmission path becomes "1", but FB still remains "0".

When R is in the "1" state for between 0.5 seconds and 8 seconds, FA is kept at "1" and FB is kept at "0". If R recovers and becomes "0" for 0.5 seconds or more, FA returns to "0" and FB also returns to "0" state. However, if R remains in the "1" state for 8 seconds or more, FA becomes "1" and FB also transitions to the "1" state.

If R remains at "0" for less than 0.5 seconds, this state is maintained, and if it continues for more than 0.5 seconds, FA returns to "0" and FB returns to "0". It is something.

The address terminal A1 of the ROM 29 counts 0.5 seconds and sends it from the data terminal Q1 to the data terminal D1 of the RAM 27 and flip-flop 28.
Address terminals A5-A8 count eight seconds and send it to data terminals D4-D7 of RAM 27 and flip-flop 28 from data terminals Q4-Q7.

Further, the address terminal A4 of the ROM 29 sends the previous state of the R bit from the data terminal Q3 to the data terminal D3 of the RAM 27 and flip-flop 28.

The terminal Q2 of the flip-flop 28 sends out the backward protection signal from the terminal BP and also sends it to the address terminal A2 of the ROM 29. The terminal Q8 of the flip-flop 28 is connected to the forward protection signal.
It is sent to BP and also sent to address terminal A9 of ROM29.

The ROM 29 performs the state transition shown in FIG. 5 and sends the above-mentioned signals to the data terminals Q2 and Q8.

(f) Effects of the Invention As explained above, the present invention makes it possible to reduce the number of protection circuits required for the number of transmission lines to one, simplifying the hardware and making it economical, and making it possible to save the contents of the ROM. It is possible to provide a clock selection method that can increase versatility by changing the clock selection method.

[Brief explanation of drawings]

1 is a block diagram showing an example of a clock selection switching circuit, FIG. 2 is a detailed block diagram of the protection circuit 5 shown in FIG. 1, and FIG. 3 is a block diagram of a circuit showing an embodiment of the present invention. 4 is a detailed block diagram of the protection circuit 5 shown in FIG. 3, and FIG. 5 is a state transition diagram in which the ROM 29 processes the input abnormality detection signal. In the figure, 1, 2, 4, 8 are switchers, 3 is a multiplexer, 5 is a protection circuit, 6 is a frequency divider, 7,
9 is a serial/parallel converter, 10 is a priority setting circuit, 1
6 is a backward protection circuit, 17, 19, and 28 are flip-flops, 18 is a forward protection circuit, 25 is a 1/4 frequency divider, 26 is a 1/8 frequency divider, 27 is a RAM, and 29 is a
It is ROM.

Claims (1)

[Claims] 1. A switching signal is activated when an input abnormality detection signal is continuously sent for a predetermined period of time to notify that each clock has entered an abnormal state corresponding to a plurality of clocks. By blocking the transmission of the switching signal when the transmission of the input abnormality detection signal stops for a certain period of time within the predetermined period of time, the clock transmitted from the main station via multiple transmission paths is , in a switching circuit that controls a switching means for switching the transmission line to select a normal clock, the plurality of input abnormality detection signals are sampled within the certain time period, and the input abnormality detection signals are sequentially inputted one by one. an extraction means for extracting the input abnormality detection signal; and determining whether or not the input abnormality detection signal extracted by the extraction means continues for the predetermined period of time in a time-division manner corresponding to the number of transmission paths; determining means for transmitting the switching signal when the determination means continues for the predetermined time; and means for supplying the switching signal transmitted by the determining means to the switching means in a time-sharing manner, and transmitting the switching signal in response to the plurality of clocks. A clock selection method characterized in that a plurality of input abnormality detection signals are received in a time-division manner, and a normal clock is selected by one of the determining means.