JPH02201935A - Logic of circuit provided with cippy prevention - Google Patents

Abstract

PURPOSE: To obtain copy preventing structure, by using a library or a gate array logic cell constituted so as to be provided with an invisible 'dummy' or an 'imitation' input line. CONSTITUTION: A copy preventing structure cell is generated by using additional ion filling operation and operated by using an additional photo resist mask pattern exposing only the channel areas of electrode effect transistors 1 and 7. Additional filling permanently changes the threshold values of the two transistors 1 and 7 outside of the voltage range of signals generated at normal lines A to C. Then, a logic cell does not respond to the logic state of the signal of a line C but generates an output X based on the logic combination of the signals of the lines A and B, to correct the true value table of a NAND cell. As a result the existence of fixed error signals appear more effectively to exclude the ability of function copy.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] This invention relates to a structure and method for preventing functional regeneration of an integrated circuit device. This invention is particularly useful for conventional computers.
Includes integrated circuit logic structures and uses suitable for providing copy protection for application specific integrated circuit (ASIC) type devices configured with aid design tools.

[Conventional technology]

Advances in the design and manufacturing of integrated circuit devices have advanced sufficiently to permit routine functional reproduction of electronic circuits using computer-aided design tools. Techniques for implementing selected electronic functions into integrated circuit devices are commonly known as "cell library" or "gate array" products. The use of this manufacturing technique involves the selective installation and connection of cells with specific internal structures to replicate the functionality of an electronic design, with the latter technique being prescribed to provide the cellular functionality specified by the designer. Substantially the same purpose is accomplished by selectively connecting groups of active electronic devices according to a defined pattern.

The electronic functionality formed by individual cells or groups of connected devices can be easily identified by analysis of integrated circuit products. With the availability of computer-aided design equipment, copying product functionality is relatively simple once cells or functional groups have been identified. Thereafter, remanufacturing of the composite semiconductor product can be easily accomplished using computer-aided design equipment so as not to generate mask workpiece shapes that are at risk of intellectual property liability. Functions such as flip-flops, logic gates and their connections are copied as opposed to transistors and connection layouts.

[Problem that the invention seeks to solve]

As the functionality of individual integrated circuit chip devices increases and includes pre-utilized performance from entire printed circuit board assemblies, the importance of preventing easy functional copying of intellectual property contained in integrated circuits increases. and value are of particular importance. The original designer's concerns are accentuated by the speed and ease with which so-called isometric integrated circuit products are made and sold. Available patents, copyrights, and mask work protections are often unavailable or useless. A dominant goal of original designers is to ensure that copyers are forced to pay reasonable costs in developing functionally equivalent integrated circuits. This makes the costs incurred by subsequent developers somewhat fairer.

[Means for solving problems]

The present invention solves the above problems by providing a copy protection method in which cells of a library or gate Φ array functional group can be designed with application specific integrated circuit design concepts used in the design of integrated circuit logic structures. That is, the invention can be accomplished using library or gate array logic cells configured with invisible "dummy" or "fake" input lines.

Dummy or spurious inputs can be detected when they occur occasionally, apparently contradicting the true value table output of the logic represented by the cell. Copying the functional logic explicitly defined in a cell, as conventionally interpreted by attempting to reproduce the functionality of the original integrated circuit, occasionally generates incorrect logic output states, which can occur intermittently and without delay. will generate an error.

A feature of this technique is that cells with bogus inputs are indistinguishable from properly operating cells and sometimes produce incorrect output states. The resulting logic errors are much more difficult to identify individually than the binary states generated by a device that is consistently at an incorrect level.

The copy protection structure and procedure of the present invention also introduces intermittent errors into the logic as a means to prevent copying of the entire functionality of an application specific integrated circuit.

Therefore, the copyer is forced to analyze and understand the design to the extent that the original designer did.

According to one structural embodiment of the invention, a composite gate, such as a three-way NAND or NOR cell, is constructed with complementary transistors responsive to one input modified by selective injection. A disabled transistor eliminates the influence of its input line by defining the logic state of the cell's output. Although such a cell is visible as a three-way logic gate, the state of the input line that is actually changed does not affect the logic state of the output. But such obvious logic-
The copy version of the cell is influenced by the binary state of the corresponding input line. Therefore, a copy that is apparently equivalent to the original cell
The cells are not functionally identical, and sometimes differences appear in the state of the true value table, and sometimes failures occur in the copied integrated circuit device.

〔Example〕

Functional copying of cell library and gate array integrated circuit products is a major problem for their original designers.

Current methods for preventing direct copying of integrated circuit functionality rely on selectively including individual transistors with improved operating characteristics to confuse copyers for application specific integrated circuits (ASICs). was not valid. An example of such a customer design is U.S. Patent No. 4.583.0.
No. 11, in which the inverter transistor pair is selectively modified and provided as an input to the logic.

The input to the logic is thus fixed in its state at a binary level. The purpose of its configuration is to provide logic logic by including specially modified transistors at its inputs.
It is a misrepresentation of one person's power on the gate.

A predominant problem for designers of ASIC products is functional copying, where groups of electronic devices are copied in cell functions or blocks without particular reference to transistors. This invention incorporates copy protection technology inside the cell and
To allow input to a cell to occur somewhere in an ASIC device and to continue operating without any influence. By changing a cell's output rather than its input, microprobing the input signal to the cell will not identify anomalies unless the input-output logic is comprehensively analyzed. Logic comparisons with such microprobes are made even more difficult by ensuring that anomalous logic states occur occasionally.

Let us now consider a NAND gate constructed to make reverse engineering its functional design decidedly more difficult. A three-person version of such a Nando Gate cell is shown in FIG. p-channel fist transistors l, 2 and 3
and n-channel transistors 4, 6, and 7 are operating in the conventional manner, the NAND voltage between inputs A, B, and 6 is
The output X in the logic relationship is shown in the true value table (■) below.

Table X=A-B-C The present invention contemplates that the cell library or gate array function library from which logic gates are drawn includes modified NAND cells. This copy-protected structure cell is created using an additional ion implantation operation. The implantation is performed using an additional photoresist mask pattern exposing only the channel regions of field effect transistors l and 7. The additional implant permanently changes the threshold of the two transistors 1.7 outside the voltage range of the signals normally occurring on lines A, B and C.

The channel region of field effect transistor 1.7 of the NAND cell of FIG.
Receive additional implantation of type dopant. Thereby, the logic cell does not respond to the logic state of the signal on line C, but is based solely on the logic combination of the signals on lines A and B, and outputs
occurs. When such a change is made, the true value table of the NAND cell is modified as shown in the table (■) below.

Table ■ X=A −B 0 1 l 1+1
00 ttt.

Comparing the true value table E and ■, it can be seen that only one set of logic states is different. The presence of a constant error signal for continuous logic cell gates appears more valid and, in fact, the incorporation of shortcomings into logic cell structures (intermittent effects sensed at the cell output) is very difficult to identify by analysis. It is. Microprobe evaluation is complicated by the fact that all logic states must be forced onto the gate's input lines before truth table mismatches can be identified.

Similarly, a copyer may interpret an intermittent error as a replicating defect in the copying device or a manufacturing defect in the original device.

Also, after thorough microprobing and logic simulation, one would only see it as a puzzling structure. As the number of logic cells in a source device and its input connections increases, the complexity of copying by cell functions increases exponentially.

Initial considerations suggest that the then-current ASIC devices for io, ooo gates constructed with this invention would effectively preclude the ability to copy functions in the manner currently practiced.

As an example of this phenomenon, we will take a logic gate with five force lines. The gate generates one error output state from 32 potential inputs. Obviously, the identification of such occasional errors can be done using microprobes or logic.
This poses a major challenge when done through simulation.

The effectiveness of intermittent errors can be emphasized by connecting spurious or occasional occurrences of signals to the functional inputs of the logic gate cells of the original ASIC design.

Thereby, the copied device is merged with design flaws that are rarely detected during normal development testing.

FIG. 2 shows a Noah circuit with inputs A, B and C and output
The application of the invention to logic cells is shown. Complementary transistor pair 8 using p-type dopant
, 9 to render them inactive for normal voltage level input signals on line C. The true value table will have one error output in one of eight possible input combinations.

The method of the invention is preferably implemented in a computer-aided design system in which the original designer defines the desired logic and selectively connects a set of fictitious connections to the inoperable inputs of the defined logic cells. insert. In documenting the special cell, incorporate its connections into the system. The desired goal is to make connections that appear superficially relevant to the operation of this circuit, but in reality create an error condition in the copied ASIC device that is not always desired. .

The addition of such copy-protected logic cells during manufacturing;
Requires a masking operation using a mask to expose the transistor channel regions selected for disable implantation. Implants of this magnitude should shift the threshold of the transistor above normal operating voltage levels, but must remain below dose levels detectable by visible or blot analysis. Additionally, if the integrated circuit product includes a ROM along with a mask, the implant mask used for the ROM can be used to implement the copy protection techniques of this invention.

This invention is a cell library or gate array ASI
It can find its application in the design of C, which design and simulation usually do not give the circuit designer the opportunity to make custom reconfigurations of the transistors. The installation and connection of copy-protected cells or gate array groups can be accomplished at the integrated circuit mask work level without the intervention of special integrated circuit device design experts.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram of a NAND cell with selectively modified complementary transistors, Figure 2 is a schematic diagram of a NOR cell with selectively modified complementary transistors, and Figure 3 is a diagram of a NAND cell with selectively modified complementary transistors. FIG. 2 is a circuit diagram of an application-specific integrated circuit having an integrated circuit and its connecting lines; In the figure, 1.2 and 3... p-channel transistors, 4, 6, and 7... n-channel transistors. Application agent Isao Saito

Claims (14)

[Claims] (1) An integrated circuit logic block comprised of a plurality of active devices of a Boolean logic architecture residing between multiple input and output lines, the integrated circuit logic block providing selective modification of the truth table represented by the logic block. An integrated circuit logic block device including active devices that are selectively deactivated. 2. An integrated circuit logic block according to claim 1, wherein the logic block is a functional group of active devices and forms a library or gate array cell for an integrated circuit of application characteristics. Device. 3. The integrated circuit logic block device of claim 2, wherein said active device is a field effect transistor. 4. The integrated circuit logic block device of claim 3, wherein said active devices are arranged in complementary pairs. 5. The integrated circuit logic block device of claim 4, wherein selected complementary pairs of devices are selectively disabled. (6) The logic block device according to claim 1, wherein the logic block is OR or NOR logic. (7) The logic block device according to claim 1, wherein the logic block is AND or NAND logic. (8) The logic block device according to claim 5, wherein the logic block is a NOR logic. (9) The logic block device according to claim 5, wherein the logic block is a NAND logic. 10. The logic block device of claim 5, wherein said selected complementary pair is disabled for a commonly performed implantation of a single dopant type in the channel region of said field effect transistor. . (11) A method for preventing functional regeneration of an application-specific integrated circuit of the cell library or gate array type, the method comprising: including in said library of logic elements, and including in the manufacturing sequence an additional photolithographic process to form an additional photoresist mask pattern based on said supplemental implant pattern, to form an application specific integrated circuit in the presence of a patterned photoresist mask. A method for preventing regeneration of an integrated circuit comprising steps of implanting during manufacturing to permanently disable selected field effect transistors. 12. The method of claim 11, wherein the differentiated logic blocks are NOR gates. (13) The differentiated logic block is a NAND
12. The method of claim 11, wherein the gate is a gate. 14. The method of claim 11, wherein the library of logic elements includes complementary field effect transistors, and wherein the photoresist mask pattern includes a pair of complementary field effect transistors.