JPH02202064A - Layout of vdmos pattern - Google Patents

Abstract

PURPOSE:To enable an intense electric field to be hardly applied onto a gate oxide film at a turn-OFF time so as to improve a basic cell in dielectric breakdown strength by a method wherein basic cells are arranged in rows in such a manner that they are displaced by one half the length of a side of a basic cell. CONSTITUTION:Basic cells are arranged not in a simple checkered pattern but in rows being displaced by one half pitch to constitute a transistor of low ON-resistance. When the transistor is turned OFF and the potential difference between a drain and a source is made to increase, a depletion layer 1 spread inside a P<-> layer and an N<-> layer spreads gradually to grow finally to be a depletion layer 2. That is, an upper limit of the intensity of an electric field applied to a gate oxide film appears at g and h inside the depletion layer formed at an aggregate point of three basic cells. But, even if the potential difference between the drain and the source is made to increase further, the upper limit of the intensity of the electric field applied to the gate insulating film decreases, because the distance between (g) and (h) is short. By this setup, an intense electric field is prevented from being applied onto a gate oxide film when a transistor is turned OFF and the transistor can be improved in dielectric breakdown strength.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a vertical double diffusion MO5FET (hereinafter referred to as "VDMO").
The present invention relates to a pattern layout method for VDMO8 (referred to as 8J), and particularly to a pattern layout method for VDMO8 that can improve the dielectric strength.

[Conventional technology]

The structure of VDMO8 is already generally known.

Many products using this are also commercially available. A specific example is rS IPMO8J manufactured by Siemens of West Germany.

The outline of the structure and cell shape of the rS I PMO8J are described in detail on pages 53 to 58 of "Power FET - From Basics to Circuit Design" by Hiroshi Yamazaki (published by Maruzen in 1988). To explain the main points here, the structure is basically planar, with an embedded source of nl,
The oxide film covering it and the silicon gate above it are all arranged laterally.

FIGS. 6(a) to 6(f) show a typical manufacturing process and structure of VDMO8. FIG. 5A shows the process of selecting a silicon substrate, in which a crystal orientation plane that provides the maximum transmission coefficient and minimum on-resistance is selected. Figure (b) shows the process for producing the shrimp layer, and figure (Q) shows the situation in which the first deep boron impurity diffusion is performed after oxidation, masking, and etching. Here, it is necessary to pay attention to the fact that boron spreads under the oxide film (FIG. 2(d)).

Following this, extremely rapid phosphorus diffusion is performed as shown in FIG. 2(e). Careful control here results in a double diffusion state. Finally, as shown in FIG. 3(f), the oxide film is deformed and electrodes are formed to complete the VDMOS.

[Problem to be solved by the invention]

In a VDMOS having the above structure, when the gate oxide film is made thinner in order to lower the input inversion voltage, the dielectric breakdown voltage of the oxide film is also reduced accordingly. Therefore, there is a trade-off between lowering the input inversion voltage and keeping the low voltage of the transistor high. That is, conventional VDMOS
However, when the thickness of the gate oxide film is made thinner in order to lower the input inversion voltage of the transistor, there is a problem in that dielectric breakdown is likely to occur due to the strong electric field applied to the gate oxide film when the transistor is turned off.

The present invention has been made in view of the above-mentioned circumstances, and its purpose is to solve the above-mentioned problems in the conventional technology and to increase the dielectric strength voltage by making it difficult for the above-mentioned strong electric field to be applied to the gate oxide film. An object of the present invention is to provide a VDMOS pattern layout method that can be improved.

[Means to solve the problem]

The above object of the present invention is achieved by a VDMOS pattern layout method characterized in that when VDMOS basic cells are arranged to form a transistor, the basic cells are arranged side by side with a shift of 172, which is one side length of the basic cells. be done.

[Effect]

In the VDMOS pattern layout method according to the present invention, when VDMOS basic cells are arranged to form a transistor, the main cells are shifted by 1/2 of the side length and arranged side by side, so that gate oxidation occurs when off. It becomes possible to make it difficult for the strong electric field applied to the film to be applied to the gate oxide film, thereby improving the dielectric breakdown voltage.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 shows the cross-sectional structure of the VDMOS. ■
By arranging basic cells, a transistor with low on-resistance is realized. FIG. 3 (upper half) is a partially enlarged view of FIG. 2. When the potential difference between the drain and source increases when the transistor is off, depletion spreads in the P- layer and the N- layer. A situation is shown in which layer 1 gradually expands and finally becomes a depletion layer 2.

When looking at the spread of the depletion layer described above from a two-dimensional perspective, it is as follows. That is, FIG. 4(a) shows the shape of a conventional gate electrode, in which basic cells separated by broken lines are arranged in a grid pattern. In this case, the depletion layer 1 grows as shown in FIG. 4(b), and the depletion layer 2 grows as shown in FIG. 4(c).

On the other hand, FIG. 1(a) shows the shape of a gate electrode according to an embodiment of the present invention, and the basic cells separated by broken lines do not have a simple substrate shape but a half-pitch shift. It is arranged as follows. In this case, the depletion layer 1 grows as shown in FIG. 1(b), and the depletion layer 2 grows as shown in FIG. 1(c).

Comparing the two using Figure 4 (Q) and Figure 1 (c),
The part where a high voltage is applied to the gate oxide film when the depletion layer grows, that is, the part 1i c in FIG. 3 (upper half)
It will be understood that the portion d is smaller in FIG. 1C, that is, in the gate electrode according to the embodiment of the present invention.
This will be explained in detail below.

FIG. 3 (lower half) shows the electric field intensity applied to the gate oxide film at a position corresponding to FIG. 3 (upper half). Here, the electric field strength is determined by the drain potential-source potential depletion layer distance. This electric field strength is equal to c' in the state of depletion layer 2.
It reaches a maximum at the position = d', and decreases thereafter because the increase in the depletion layer thickness becomes large.

Next, FIGS. 5(a) and 5(b) correspond to FIG. 4(c) and FIG. 1(c), respectively. The horizontal axis in the diagram, which indicates the electric field strength applied to the gate oxide film and the upper limit of the electric field strength applied to the gate oxide film when a voltage is further applied, indicates the position, and the horizontal axis indicates the position, respectively. This corresponds to the position shown in FIG. 1(c) and FIG. 1(c). In the case of Fig. 4 (Q), the upper limit of the electric field strength applied to the gate oxide film appears in the depletion layer formed at the gathering point of the four basic cells (positions 11e and f in the figure). . Here, if the potential difference between the drain and the drain is further increased, the upper limit of the electric field strength applied to the gate oxide film increases to the value indicated by MAX in the figure, as shown in FIG. 5(a).

On the other hand, in the case of FIG. 1(c) according to this embodiment, there is a gate oxide film in the depletion layer formed at the assembly point of three basic cells (positions @g and h in the figure). An upper limit to the electric field strength will appear. Here, even if the potential difference between the drain and the source is increased, the distance between g and h is shorter than the distance between e'' and f, so as shown in FIG. 5(b), the voltage applied to the gate oxide film The upper limit of the electric field strength is the fifth
Compared to the conventional case shown in Figure (a), (MAX,
) will fall to the value shown.

After all, in the case of the above embodiment, there is no need to particularly change the device manufacturing process; by changing the arrangement shape of the gate, the shape of the depletion layer when it grows can be controlled, and the electric field applied to the gate oxide film can be controlled. This makes it possible to keep the upper limit of strength low. As a result, the thickness of the gate oxide film required to obtain the same transistor breakdown voltage can be made thinner, and the effect is that it becomes possible to obtain a high breakdown voltage VDMO8 with a lower input inversion voltage and easier to handle. be.

The above embodiment is shown as an example of the present invention,
It goes without saying that the present invention should not be limited to this.

〔Effect of the invention〕

As described above in detail, according to the present invention, 70MO8
A 70MO8 pattern layout method that can improve dielectric strength by arranging basic cells to form a transistor, by arranging the basic cells in parallel with a shift of 1/2 of the side length of the basic cells. This has the remarkable effect of realizing the following.

[Brief explanation of the drawing]

FIGS. 1(a) to (c) are diagrams showing the shape of the gate electrode and the growth situation of the depletion layer according to an embodiment of the present invention; FIG.
A diagram showing the cross-sectional structure of VDMO8, Figure 3 is 70 in Figure 2.
A partially enlarged view of MO8 and a diagram showing the state of the electric field strength applied to the gate oxide film at the corresponding position, Figure 4 (a) ~
(c) is a diagram showing the shape of the conventional gate electrode and the growth situation of the depletion layer, and Figures 5 (a) and (b) are the electric field strength applied to the gate oxide film in the embodiment and the conventional example, and the voltage applied. FIGS. 6(a) to 6(f) are diagrams showing a typical manufacturing process and structure of a VDMOS. ■Two-base water cell, ■: Transistor. (a) Figure (Part 1), Figure (Part 2) (b) Figure ■ Figure (Part 3) (c) Figure (Part 1) (a) Figure (Part 2) (b) Figure (Part 3) (c) Figure (Part 1) (a) Figure (Part 2) (c)

Claims (1)

[Claims] (1) A VDMOS characterized in that when basic cells of a high voltage double-diffused MOSFET (VDMOS) are arranged to form a transistor, the basic cells are arranged side by side with a difference of 1/2 of the side length of the basic cells. pattern layout method.