JPH02203536A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to make a large window and to facilitate the manufacture of a semiconductor device by a method wherein after a gate electrode is separated by first and second insulating thin films, third insulating thin films are provided and the third insulating thin films on the gate electrode are etched to form contact windows. CONSTITUTION:An n<+>-polysilicon film 4 and a CVD oxide film 5, which is a first insulative thin film, are formed on a silicon substrate 1 provided with an element isolation region and a gate oxide film 3. Then, after the conductor film 4 and the film 5 are etched using a resist 6 provided at a gate electrode region as a mask and the resist 6 is removed, a second insulative thin film (a CVD oxide film) 7 is formed. Moreover, arsenic is ion-implanted to form third insulative thin films (a BPSG film and a CVD oxide film) 9 and 10 on the whole surface, in which n<+>-regions 8 are formed. Moreover, a resist 11 is formed in the vicinities of contact formation parts and the films 9 and 10 are etched to form contact windows. Thereby, as the formation of the contact windows is performed in a self-alignment manner to a gate electrode 4' and a window can be made large, the manufacture of a semiconductor device is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to forming a contact window in a fine semiconductor element.

2. Description of the Related Art As semiconductor devices become more highly integrated, elements are becoming increasingly finer. In order to achieve miniaturization of this element, it is necessary to form fine contact windows for wiring used in the element.

Therefore, in conventional semiconductor device manufacturing methods, this is achieved by forming fine photoresist pattern windows. As shown in FIG.
In this step, a gate oxide film 103 and poly 51104, which is a gate electrode wiring material, are formed. Then, a resist 105 is formed at a position where a gate electrode wiring is to be formed using a photophosphorography technique.

Next, as shown in FIG. 5B, the poly 51104 is anisotropically etched using the resist 105 as an etching mask to obtain a gate wiring 104''. After removing the resist 105, a CVD oxide film is formed on the entire surface. The CVD oxide film was anisotropically etched by dry etching and the same (
A sidewall spacer 106' of C) is formed, and an n4 region IO7 is formed in the contact portion by ion implantation or the like. Next, as shown in FIG. 4(d), a CVD oxide film 108 such as PSG (IJ-doped glass) or BPSG (boron-phosphorous doped glass) is formed and heat treated to smooth the surface.

Then, a resist 103 is formed by removing the resist in the contact forming portion using photophosphorography technology. After etching the CVD oxidation [%108] using the resist 109 as an etching mask to expose the surface of the n-region 107 of the contact portion, an AI wiring 110 is formed as shown in (e), and a MOSFET transistor is formed. The idea was to form source and drain wiring contacts.

Problems to be Solved by the Invention However, the conventional manufacturing method shown in FIG. 5 still has problems as described below.

(1) When the contact portion of the resist 109 shown in FIG. 5(d) becomes less than 1 μm, it becomes very difficult to form the contact window of the resist 109 with high precision.
It is much more difficult to open a window smaller than San. Also, if the contact spreads too much, the gate electrode! 04'
and the AI wiring 110 come into contact with each other, and the MOSFET no longer functions as a MOSFET.

(2) Since the resist 109 is formed using mask alignment using photophosphorography technology, it is usually 0°2 to 0.0°.
A misalignment of about 5 μm will occur. In order to prevent defects due to this misalignment, a margin of alignment is required. Providing an alignment margin increases the area occupied by each element, making it difficult to miniaturize and highly integrate the elements.

Means for Solving the Problems The present invention provides a step of forming a conductive thin film to serve as a gate electrode on at least the entire surface of one principal surface of a semiconductor substrate on which an element isolation region and a gate oxide film are formed, and a step of forming a conductive thin film on the conductive thin film. a step of forming a first insulating thin film in a region where a gate electrode is to be formed; a step of forming a first photoresist in a region where a gate electrode is to be formed; and a step of forming a first insulating thin film using the first photoresist as an etching mask.
a step of etching the insulating thin film and a conductive thin film, a step of removing the first photoresist, a step of forming a second insulating thin film on the entire surface, and a step of forming the second insulating thin film. , a step of etching the second insulating thin film in a desired manner, a step of forming a high impurity concentration region in the contact portion by ion implantation, and a third step of etching the second insulating thin film on the entire surface.
a step of forming a second photoresist in a region near the contact formation portion without considering the margin between the gate electrode and the contact formation portion; and a step of forming the second photoresist. etching the third insulating thin film by a desired amount as an etching mask;
This method includes a step of removing the second photoresist and a step of forming wiring.

Effect of the present invention With the above structure, after the gate electrode is insulated and separated by the first insulating thin film and the second insulating thin film on the gate electrode wiring, the third insulating thin film is formed, and the third insulating thin film is formed on the gate electrode. By etching part (or all) of the third insulating thin film to form a contact window, the contact part can be formed in self-alignment with the gate electrode, so the opening in the resist when forming the contact can be made minute. It is not necessary and can be easily formed.

Furthermore, even if misalignment occurs in mask alignment during resist formation during contact formation, the insulation between the gate electrode and the wiring is not affected, so no alignment margin is required, and the element can be miniaturized.

Moreover, this enables high integration.

EXAMPLES Below, a method for manufacturing a semiconductor device according to the present invention will be explained based on the drawings.

(First Example) FIG. 1 is a process cross-sectional view for explaining the first example of the method for manufacturing a semiconductor device according to the first invention, in which an oxide film 2 is formed in the inter-element insulation isolation region. After that, MOSFET gate oxidation [3 formed P-type (100) silicon (S+)
As shown in FIG. 1(A), a phosphorus-doped N3 polysilicon layer 4 is placed on a substrate 1 as a conductive thin film that will become a gate electrode.
300 nm thick and CVD as the first insulating thin film.
An oxide film 5 is formed to a thickness of 300 nm.

Then, a resist 8 as a first resist is formed using a photophosphorography technique on a region where a gate electrode is to be formed. Next, as shown in (B), using the resist 6 as an etching mask, C is etched by dry etching or the like.
After anisotropically etching the VD oxide film 5 and anisotropically etching the N4 polysilicon 4 to form a gate electrode 4', the resist 6 is removed and a CVD oxide film is formed on the entire surface as a second insulating thin film. 7! 00 to 300 nm. Next, as shown in (C), the CVD oxide film 7 is anisotropically etched by dry etching or the like to form a sidewall spacer 7'', and then arsenic (As) is introduced by ion implantation or the like to form the n4 region 8. Next, as shown in (D), a third insulating thin film of carbon having low thermal fluidity is formed on the entire surface.
A 200 nm thick VD oxide M9 and a 300 nm thick CVD oxide film (BPSG film) 10 containing boron (B) and phosphorus (P) as an insulating thin film with high thermal fluidity are formed.

Next, as shown in (E), heat treatment was performed in a foggy atmosphere at 800°C or higher to form a BPSG film. After reducing the film flow to zero and smoothing the surface to make it easier to form the wiring to be formed later, the area other than the contact formation area and the vicinity of the gate electrode 4I where the contact will be formed, that is, the area above the gate electrode and the contact area is removed. Next, a chill cyst 11 is formed as a second resist using a photolithography technique. At this time, the opening portion of the resist is wider than the contact portion and there is no need to make minute holes in the resist.Next, as shown in (F), the BPSGIO and the CVD oxide film 9 are anisotropically etched by dry etching or the like. At this time, some of the BPSG film lO
The CVD oxide film 9 remains near the sidewall spacer 7'. As a result, one end of the contact surface of the n♦ region 8 is determined in self-alignment with the gate electrode 4'. Next, the same (
As shown in G), after removing the resist 11 and removing the natural oxide film naturally formed on the surface of the n◆ region 8 by wet etching or the like, an A1 thin film I2 for forming wiring,
A resist 13 is formed on the AI wiring formation region. next,
As shown in (■), the AI thin film I2 is etched using the resist I3 as an etching mask, and then the resist 13 is removed to form contacts for the source and drain regions of the MOSFET.

(Second Embodiment) FIG. 2 is a process cross-sectional view for explaining the second embodiment of the method for manufacturing a semiconductor device of the present invention, and is similar to FIG. After forming in the same manner as C),
As shown in FIG. 2 (D'), a BPSG film 1 is formed as a third insulating thin film on the entire surface as an insulating thin film with high thermal fluidity.
2 membrane type 2. Next, as shown in the same figure (E'),
After performing heat treatment in the above-mentioned foggy atmosphere to flow the BPSG film 1O and smooth the surface to make subsequent wiring formation easier, resist is applied to areas other than the contact formation area and the vicinity of the gate electrode 4'' where the contact will be formed. !■ Form.

At this time, the opening in the resist is wider than the contact portion and there is no need to make minute holes in the resist. Hereinafter, after etching the BPSG film 0 in substantially the same manner as in the first embodiment,
The same (■') is obtained by forming the I wiring 12'.

(Third Embodiment) FIG. 3 is a process cross-sectional view for explaining the third embodiment of the method for manufacturing a semiconductor device of the present invention, and is similar to FIG. After forming in the same manner as C),
CV as the third insulating thin film as shown in Figure 3 (1)
After forming the D oxide film 8, a resist 1] is formed in areas other than the contact forming area and the vicinity of the gate electrode 4' where the contact is to be formed. This also does not require minute holes in the resist, as in the first and second embodiments described above.After etching the CvD oxide film θ in almost the same manner as in the first embodiment, the AI wiring 12 is etched. ' to form the same (K)
get.

(Fourth Embodiment) FIG. 4 is a process sectional view for explaining a fourth embodiment of the method for manufacturing a semiconductor device of the present invention, and is a process cross-sectional view for explaining a fourth embodiment of the method for manufacturing a semiconductor device of the present invention. After forming in the same manner as D),
Heat treated in a foggy atmosphere at 800℃ or higher
Make the surface smooth by flowing roWX. Next, as shown in FIG. 4(L), a resist 11 is formed in areas other than the contact forming area. Resist this time! ■ is gate electrode 4
Since it is not necessary to completely cover the ``area, but only a portion is exposed, it is possible to make a hole wider than the actual contact area.Thereafter, the BPSG@10 and the CVD oxide film 9 were etched in almost the same manner as in the first embodiment. A rear A1 wiring 12'' is formed to obtain the same (N).

The first to fourth embodiments have been described using a BPSG film as an insulating film with high thermal fluidity.
You may also use a film such as As explained in the first to fourth embodiments above, even if a fine contact is required, a resist opening for forming a contact window can be formed on the gate electrode, and the fine resist Drilling becomes unnecessary. Furthermore, since the gate electrode 4' and the contact portion are determined in a self-aligned manner, there is no need to take an alignment margin during mask alignment.

Effects of the Invention As described above, according to the method of manufacturing a semiconductor device of the present invention, the following effects can be obtained.

(1) Since the gate electrode is covered by the first insulating thin film and the second insulating thin film, the resist opening for contact formation may be located above the gate electrode, and even when forming fine contacts, the resist opening Because the opening of the window only needs to be large,
Forming resist holes for contacts becomes easier.

(2) Furthermore, since the contact can be formed in a self-aligned manner with respect to the gate electrode, there is no need for a margin for mask alignment between the contact portion and the gate electrode, and the element can be formed finely.

[Brief explanation of the drawing]

FIG. 1 is a process cross-sectional view for explaining the first embodiment of the semiconductor device manufacturing method of the present invention, and FIG. 2 is a process cross-sectional view for explaining the second embodiment of the semiconductor device manufacturing method of the present invention. 3 is a process sectional view for explaining the third embodiment of the method for manufacturing a semiconductor device of the present invention, and FIG. 4 is a process cross-sectional view for explaining the fourth embodiment of the method for manufacturing a semiconductor device of the present invention. FIG. 5 is a process cross-sectional view showing an example of a conventional method for manufacturing a semiconductor device. 1... Silicon substrate, 8... Resist (first resist), 2... Oxide film, 7... CVD oxide film (second insulating thin film), 3...・Gate oxide film, 7
9...Side wall spacer, 4...n◆Polysilicon, 8...n4 region, 4'...Gate electrode, 9...CVD oxide film (third insulating film) thin film),
5...CVD oxide film (first insulating thin film), lO.
...BPSG film (insulating thin film with high thermal fluidity). Agent's name: Patent attorney Shigetaka Awano Formula % Name of the invention Relationship to the case of a person amending the manufacturing method of a semiconductor device Address Name Representative Patent applicant 1006 Kadoma, Kadoma-shi, Osaka (582) Matsushita Electric Industrial Co., Ltd. Akio Tanii 4 Agent address: Matsushita Electric Industrial Co., Ltd., 1006 Oaza Kadoma, Kadoma City, Osaka 571 (Sho-no-4) 2 Figure (Part 2) Figure 2 Figure 3) l Indication of the case 2 Name of the invention Manufacture of semiconductor devices Method 3 Person making an amendment Address related to the case Name Representative Patent Applicant 1006 Oaza Kadoma, Kadoma City, Osaka (582) Matsushita Electric Industrial Co., Ltd. Akio Tanii 4 Agent Address 571 Osaka Prefecture 6, Matsushita Electric Industrial Co., Ltd., 1006 Kadoma, Kadoma City, Contents of amendment (1) "Figure 2 (D)" on page 10, line 5 of the specification
Correct it as "Figure 2 (D)". (2) Correct r (E') J on page 10, line 8 of the same book to r (E) J. (3) Same book, page 10, line 16 (7) r (H 勺)
Correct it as r(H)J.

Claims (3)

[Claims] (1) Forming a conductive thin film to serve as a gate electrode on at least the entire surface of one principal surface of the semiconductor substrate on which the element isolation region and the gate oxide film are formed, and forming a first insulating thin film on the conductive thin film. a step of forming a first photoresist in a region where a gate electrode is to be formed;
etching the first insulating thin film and the conductive thin film using the photoresist as an etching mask; removing the first photoresist; forming a second insulating thin film on the entire surface; a step of anisotropically etching the second insulating thin film by a desired amount; and a step of forming a high impurity concentration region in the contact portion by ion implantation or the like;
a step of forming a third insulating thin film on the entire surface; a step of forming a second photoresist in a region other than the vicinity of the contact forming portion without considering the margin between the gate electrode and the contact forming portion; A method for manufacturing a semiconductor device comprising: etching the third insulating thin film by a desired amount using the photoresist No. 2 as an etching mask; removing the second photoresist; and forming wiring. (2) After forming a third insulating thin film with low thermal fluidity, an insulating thin film with high thermal fluidity is formed, and the insulating thin film with high thermal fluidity is made to flow by heat treatment. A method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is formed by: (3) The semiconductor device according to claim 1, wherein the third insulating thin film is formed by using an insulating thin film with high thermal fluidity and causing the third insulating thin film to flow through heat treatment. Production method.