JPH02203565A - Semiconductor device and its manufacture - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit and a method for manufacturing the same.

[Conventional technology]

When manufacturing large-scale integrated circuits, there is a growing need for interconnection techniques that connect diffusion layers and gate electrodes of different conductivities to each other while preventing interdiffusion of impurities that determine their respective conductivity types. This technique is necessary for reducing the memory cell area of an integrated circuit such as a CMOS memory cell. In other words, when using the conventional method of connecting the source and drain regions and gate electrodes of PMOS and NMOS, in which a connection hole is opened on a diffusion layer or gate electrode and the connection is made with a metal wiring layer, even higher integration is possible. Have difficulty.

One proposal for this purpose is described in Japanese Patent Laid-Open No. 62-257749. This involves exposing the source and drain regions and the surface of the gate electrode made of polysilicon, depositing titanium on the entire surface, heat-treating it in a nitrogen atmosphere to form titanium nitride, and shaping the titanium nitride film into a predetermined shape. In this method, the source and drain regions and gate electrodes are interconnected by patterning. Titanium nitride is a conductor exhibiting metallic conduction and is also an effective material as a barrier to atomic diffusion. Therefore, even in the subsequent heat treatment process, the dopants (for example, boron) in the source and drain do not enter the gate electrode, and the dopants in the gate electrode (for example, phosphorus) do not enter the source and drain sides. It becomes possible to ohmically connect the drain and gate electrodes.

[Problem to be solved by the invention]

The above-mentioned conventional technology employs a method of heat-treating titanium in a nitrogen atmosphere when forming titanium nitride. Therefore, on silicon, titanium silicide is formed at the interface with silicon, and titanium nitride is formed thereon. Further, only titanium nitride is formed on the field oxide film and the oxide film of the sidewall of the gate electrode. Therefore, if the heat treatment in a nitrogen atmosphere is insufficient (such as when the heat treatment cannot be prolonged), titanium nitride is formed only on the surface of the titanium on the oxide film, and unreacted cutin remains inside. In addition, if the field oxide film or sidewall that separates the diffusion layer and gate electrode is short, titanium silicide will creep up, and there is a high risk that the diffusion layer and gate electrode will be connected by titanium silicide. does not easily serve as a diffusion barrier, and dopants exhibiting opposite conductivity types interdiffuse in the source, drain, and gate electrodes to form a PN junction, and therefore cannot form an ohmic connection.

The purpose of the present invention is to reliably act as a diffusion barrier even in cases where there are some restrictions on heat treatment or in sufficiently fine structures.
An object of the present invention is to provide a method for ohmic connection between layers of different conductivity types.

(Means for solving problems) The above objective is achieved by the following means.

The first step is to use a new material to replace titanium nitride, which is formed by heat treatment in a nitrogen atmosphere. After experimentally examining various materials including titanium-based materials, we found that tungsten-based materials are effective as diffusion barriers. That is, unlike titanium silicide, tungsten silicide, which is formed by depositing tungsten on silicon by sputtering or the like and turning it into silicide through heat treatment, can serve as a diffusion barrier for impurities. In addition, silicide, which is tungsten with other high-melting point metals added, is also effective as a diffusion barrier. For example, silicide of an alloy of Ti and W can be mentioned.

Next, the structure is such that the silicide is completely formed between layers of different conductivity types. MO explained earlier
As an example of the connection between the source, drain and gate electrode of S,
The structure is such that the above tungsten silicide is formed on the source and drain.

By covering the area directly above the region doped with impurities with a tungsten-based silicide film having diffusion barrier properties, diffusion of impurities to other layers is suppressed.

Furthermore, the above structure can be formed as follows.

First, after providing one MOS, the diffusion layers of the source and drain regions of the MOS and the surface of the gate electrode made of polysilicon are exposed. That is, tungsten or its alloy is deposited over the entire surface by a zero-order sputtering method that removes an insulating film such as a silicon oxide film. Thereafter, tungsten on silicon and polysilicon is converted into silicide by annealing in an inert gas such as argon. At this time, portions other than those on the silicon, such as on the oxide film, remain as unreacted tungsten. Therefore, only the necessary portions between the source, drain, and gate electrodes are masked, and other unreacted tungsten is selectively removed with respect to the tungsten silicide.

In the manner described above, a diffusion barrier can be formed between layers of different conductivity types to connect them.

[Effect]

As a diffusion barrier material to replace titanium nitride, a structure in which tungsten or a reaction product (silicide) of an alloy containing tungsten and silicon is formed on a layer doped with impurities can be used as a connecting layer between layers of different conductivity types. Even if the tungsten silicide itself does not have diffusion barrier properties, the diffusion of impurities in silicon is suppressed by the tungsten silicide during the subsequent heat treatment process. Furthermore, since silicide and silicon can make ohmic contact, it is possible to make ohmic connection between layers of different conductivity types using a fine pattern.

What is important here is the diffusion barrier effect of tungsten-based silicide. In general, silicide deposited by sputtering using a sintered alloy target or the like allows impurities to diffuse quickly. According to our experiments, the diffusion coefficient of tungsten silicide is 104 times that of silicon. However, silicide, which is obtained by depositing tungsten on silicon and converting it by heat treatment, can serve as a diffusion barrier as described above. Although no clear conclusion has yet been reached regarding the reason for this, it is thought that it largely depends on its density and crystallinity. In other words, it is considered to be a material in which impurity diffusion is extremely slow. Furthermore, the barrier effect of impurity diffusion against a certain heat treatment is greater when the tungsten is tungsten before the heat treatment and is converted to tungsten silicide by the heat treatment than when it is already converted to tungsten silicide.

This seems to be because silicon diffuses into tungsten and causes a silicide reaction, which prevents impurity diffusion.

Due to the above-described effects, an impurity diffusion barrier can be formed using tungsten-containing silicide or a silicide reaction, and fine ohmic connections between layers of different conductivity types can be made.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1st
The figure is a cross-sectional view illustrating a method of manufacturing a CMOS memory cell according to the present invention.

First, as shown in FIG. 1A, on the main surface of the silicon substrate 1,
A type well region 2 and a P type wafer region 3 are formed.

Next, a field oxide film 4 is provided to isolate the two well regions, and then a gate oxide film 5 is formed on both well regions by thermal oxidation.Next, a polysilicon film is deposited on the entire surface using the CVD method. 5. Phosphorus is thermally diffused into the polysilicon film to form a high concentration n-type polysilicon film (n+ polysilicon film). Thereafter, the n+ polysilicon film is processed into a predetermined shape using photoetching technology, and a gate electrode that spans the n-well region 2, the p-well region 3, and both well regions is formed. , 77°777.

Next, as shown in FIG. 1B, boron ions are implanted into the entire surface of the n-well region 2 to form source and drain regions 8 made of a low concentration P-type layer (p- layer), and then the p-well region 3
A low concentration n-type layer (n- layer) is formed by ion-implanting phosphorus into the entire surface of the
Source and drain regions 9 are formed. Thereafter, a silicon oxide film (SiO2 film) is deposited on the entire surface by CVD, and the 5ift film is etched by anisotropic dry etching using, for example, an etching gas containing CHFa as the main component. The side wall 10.11 of 5102 is formed on the side surface of 777.

Next, as shown in FIG. 1C, boron ions are implanted into the n-well region at a dose of 5×10 "am-" (7) at 30 KeV to form source and drain regions 12 made of a highly concentrated P-type layer (P soil layer). establish. Further, on the P-well region side, arsenic is ion-implanted at 80 KeV with a dose of 2 x 10''(!1-''2) to form source and drain regions 13 made of a highly concentrated n-type layer (n-soil layer). After that, source and drain regions 12, 13 and gate electrodes 7, 77 are formed.
．． The surface of 777 is cleaned and tungsten (W) is deposited by sputtering. Next, heat treatment is performed at about 600°C in an inert gas such as argon, and the Si of the source and drain 12.13 and the gate electrode 7,77°777 are heated.
Tungsten silicides 14 and 15 are formed by reacting the upper polysilicon with W. At this time, the 5iOz side wall 11
The W above remains unreacted and remains W2C.

It remains as 17.

Next, as shown in the first diagram, Si was first applied to the entire surface by CVD.
Deposit O2 and then apply a gate voltage t across both wells.
! A SiO2 mask 18 is left by photolithography so as to mask the unreacted W27 on the side wall 10 of the i 777, and the gate electrode 77 of the MOS is further removed by aqua regia treatment.
Unreacted W16 on the side wall 10 of the reactor is removed. Another 900
By heat-treating at a temperature of ℃ or higher, the sheet resistance of WSi2 is reduced and the n-soil layer and p-soil layer are activated. ). With the above steps, the main steps of the CMOS memory cell are completed.

As is clear from the first diagram, the CMOS memory cell manufactured by the process described above has a gate electrode 777 and a P+
Connections with the source, drain 12 and n+ source and drain 13 are made with WSiz14°W17 and WSiz15, and even in the heat treatment above 900°C, doping impurities in the source, drain 12, 13 and gate electrode 777 ( boron, phosphorus, arsenic) is WSiz
WSiz 14 and 15 are prevented from diffusing and do not penetrate into the opposing layer, and since WSiz 14 and 15 are in contact with the high concentration layer, ohmic contact is made, so that the source and drain regions 12 and 13 and gate electrode 7
77 low resistance ohmic local connections are possible.

Figures 2 and 3 show CM obtained by the above manufacturing method.
2 is a circuit configuration diagram showing one bit of an OS memory cell and its plane pattern. As shown in Figure 3, the gate electrode and n
10 diffusion layers (nMOS source, drain) and P 10 diffusion layers
a (source drain of 2MOS) is covered with WSiz and connected therebetween with W17.

Next, another embodiment of the present invention will be described with reference to FIG. Fourth
Similar to FIG. 1, this figure is a sectional view showing a manufacturing method when the present invention is applied to a C:MOS type memory cell.

First, in FIG. 4A, source and drain regions 12.1
The steps up to the formation of No. 3 are the same as those of the first embodiment. Thereafter, the Si surfaces of the source and drain regions 12 and 13 and the polysilicon surfaces of the gate electrodes 7, 77.degree. 777 are cleaned to avoid any oxide film, and W19 is deposited on the entire surface by sputtering. Next, the gate electrode 777 and the sidewall 11 are covered, and the source and drain regions 12.1 are further formed.
It is processed by photo-etching so as to cover part of 3 and remove the other part.

Next, as shown in FIG. 4B, heat treatment is performed in an inert gas such as argon to convert W19 on a portion of the source and drain 12.13 and the gate electrode 777 into WSiz14.15. At this time, the W on the 5iOz sidewall 11 remains unreacted.6 or more is the main process of the CMOS memory cell.

The effect of this embodiment is the same as that of the first embodiment.
The diffusion barrier effect of WSiz14 and WSiz15 and the connection between them by W17 make local wiring possible, but the unique effect of this example is that since W19 has been processed in advance, the heat treatment for silicidation of W19 is easy. One advantage is that the process can be simplified because it only needs to be done once (it only needs to be done after depositing the interlayer insulating film between the wiring layer).

In the case of this embodiment, WS is provided on the gate electrodes 7 and 77.
There is a drawback that iz is not formed and the resistance of the electrode increases when polysilicon is used alone.

In contrast, as shown in FIG. 5, WSiz20/Polysilicon 7 was formed by depositing WSiz on polysilicon in advance by sputtering and simultaneously processing a two-layer film of WSiz and polysilicon. Alternatively, a structure using the gate electrode of 77) may be used.

Furthermore, the method of the embodiment shown in FIG. 4 is particularly effective when a so-called creep-up phenomenon occurs in which Si diffuses into W during the heat treatment for silicidation and also silicides the W on the 5iOz sidewall. Figure 6 shows an example of such a case.The film thickness of the gate electrode 7゜77.777 is thin and the Si0g sidewall is short, so that the WSiz of the source and drain and the WSiz on the gate electrode are connected due to creeping. This is a case of putting it away.

As shown in FIG. 6A, W2O is applied to the entire surface and processed.

Through subsequent heat treatment, W2O is converted to WSiz by the underlying silicon or polysilicon, but this WSi
z comrades are connected and W on the S i Oz side wall 11 is also the 6th
As shown in Figure B, < W S i z changes. in this case,
The performance of the local connection between the source and drain 12, 13 and the gate electrode 777 remains unchanged.

Furthermore, another embodiment of the present invention will be explained with reference to FIG. FIG. 7 is also a sectional view showing a method of manufacturing a CMOS type memory cell according to the present invention.

FIG. 7A shows a state in which polysilicon 21 is deposited on the entire surface by CVD after forming source and drain regions 8 and 9 consisting of a P- layer and an n- layer, respectively, in the same manner as in the embodiment shown in FIG. show.

Next, as shown in FIG. 7B, the polysilicon 21 is selectively etched, leaving only the polysilicon 22 above the source and drain 8.9. This selective etching method includes, for example, 198 International Electron Devices Meeting Technical Digest, pages 32 to 35 (1987 International Electron Devices Meeting Technical Digest, pages 32 to 35).
al Electron DevicesMeetin
g Technical Digest pp 32-
35), the gate electrodes 7, 77
．． The phosphorus in 777 is diffused into the polysilicon above it, and this phosphorus-doped polysilicon is used as the source and drain 8.
．． The non-doped polysilicon on 9 may be selectively etched by plasma etching or the like.

As shown in FIG. 7C and FIG. 7, the source and drain 12.
WSiz formed by the reaction of polysilicon 22 and W on 3
23, W is formed on the SiOz sidewall, and WSiz15 is formed on the polysilicon gate electrode 777, thereby forming a connection between layers of different conductivity types.

The feature of this embodiment is that WSiz 23 is formed on the source and drain 12 and 13 using polysilicon, which is advantageous for making the source and drain shallow junctions.

FIG. 8 is a sectional view showing a CMOS type memory cell process in still another embodiment of the present invention.

First, as shown in FIG. 8A, a gate oxide film is left under the gate electrode 88.77, and a gate electrode and 5iOz forming side walls 10 and 11;
More sauce.

After providing the drains 12 and 13, W2O is applied over the entire surface. At this time, the gate electrode 88,888°77.777
The dopant is changed by ion implantation or the like, and gate electrodes 88 and 888 are implanted with boron to make them P-type gate electrodes, and gate electrodes 77 and 777 are doped with phosphorus to make them N-type gate electrodes.

Next, as shown in FIG. 8B, WSiz1 is formed on the sources and drains 12 and 13 by heat treatment in an inert gas such as argon.
4, unreacted W16, 17 on the side wall 10.11,
Furthermore, WS is placed on the gate electrode 88,888°77.777
form iz. Afterwards, the side wall 10.1 is treated with aqua regia.
The unreacted W 16° 17 on top of the wafer 1 is removed to form the shape shown in FIG.

In this embodiment, the connections between the source and drain 12.13 and the gate electrodes 888 and 777 are made using a P soil layer 24. and n-layer 9 and polysilicon gate electrode 7
They are connected by an n-soil layer 25 formed by diffusion of phosphorus from 77. Here, between the gate electrodes 888 and 777 is Pn
Although a junction is formed, ohmink contact is maintained by the upper part of the gate electrode WSiz15. With such a structure, all unreacted W on the sidewalls 10 and 11 can be removed, and a patterning process that leaves W on the sidewalls 11 is not necessary, and the source and drain regions 12 and 13 can be used for patterning. It is possible to make the memory cell smaller without taking any mask alignment margin, and further miniaturization of the memory cell is possible.

FIG. 9 is a sectional view showing the main manufacturing steps of a CMOS type memory cell showing another embodiment of the present invention.

First, as shown in FIG. 9, W19 is deposited through the same manufacturing process as in the embodiment shown in FIG. 8, and the gate electrode 888. and 7
Processing is performed so that W19 remains only on the boundary of 77. After that, W19 was converted to WSiz15 by silicide heat treatment.
cause a reaction.

In this embodiment as well, the connection between the source, drain and gate electrode is P-! 8 and P soil layer 24, or n- layer 9 and n+M25
I am by. This embodiment uses a WS similar to the embodiment shown in FIG.
This is a countermeasure for the case where iz climbs onto the side walls 10 and 11.

In the embodiments described above, Wsi is used as a diffusion barrier.
Although the explanation was made using W, other high melting point metals such as Mo
, a reaction film with silicon of an alloy to which Ta, Ti, etc. are added (
silicide film) may also be used.

Furthermore, in the above embodiments, W or an alloy thereof is used when depositing, and it can be seen that silicidation naturally occurs with heat treatment.

Furthermore, although the above embodiments have all been explained using CMOS type memory cells as an example, they can also be applied to other CMO3 type devices, bipolar type devices, or composite semiconductor integrated circuit devices in which 0MOS and bipolar elements are provided on the same substrate. However, the effects of the present invention can also be achieved.

〔Effect of the invention〕

According to the present invention, an impurity diffusion barrier can be formed by the silicide of the alloy film containing W and W. Therefore, if the silicide is interposed between different types of multilayer layers, mutual diffusion of each doping impurity can be prevented, and each It is possible to prevent the formation of a Pn junction that degrades the performance of the layer. Furthermore, ohmic connection is possible with silicide. Therefore, fine connections can be made between layers of different conductivity types without going up to a metal wiring layer such as AQ, and as a result, high integration and high performance of semiconductor integrated circuit devices can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a cross section of a CMOS type memory cell according to an embodiment of the present invention in the order of manufacturing steps, FIG. 2 is a circuit configuration diagram for one bit of a CMO3 type O3 recell, and FIG. 3 is a method of the method shown in FIG. 1. 4, 5, 6, and 7 are plan views showing examples of plane patterns of CMOS memory cells manufactured by
FIGS. 8 and 9 are cross-sectional views illustrating the main manufacturing steps of a CMOS type memory cell according to another embodiment of the present invention. 7.77.777...Polysilicon gate electrode. 10, L L-8i Oz ORN, 12.13-
Source, drain region, 14.15...WSiz,
16゜Figure Figure Figure SS Figure Figure Figure Figure 6 Figure 8 Figure 7 Figure 9

Claims (1)

[Claims] 1. In an electrical connection between a layer of one conductivity type and a layer of a conductivity type opposite to the one conductivity type layer, a reaction product of tungsten and silicon is added to the composition or structure of the electrical connection material. An electrical connection structure between two conductivity type layers, characterized in that it is a part of an object. 2. An electrical connection structure between two conductivity type layers, characterized in that a reaction product of tungsten and silicon is interposed between one conductivity type layer and a conductivity type layer opposite to the one conductivity type layer. 3. a layer of one conductivity type on a substrate; a layer of conductivity type opposite to the layer of one conductivity type separated from the layer of one conductivity type by an insulator;
A conductor provided between the reaction product of tungsten and silicon on the one conductivity type layer, the reaction product of tungsten and silicon on the opposite conductivity type layer, and the two reaction products of tungsten and silicon. A local electrical connection structure characterized by having: 4. A plurality of MOS transistors are provided on the substrate, and the M
The silicon surface of the source and drain regions of the OS type transistor and the polysilicon surface of the gate electrode of the MOS type transistor are exposed, tungsten is deposited and heat treated in an inert gas, and the silicon surface of the source and drain regions is exposed. A method for manufacturing an integrated circuit device, comprising the steps of forming a reaction product of tungsten and silicon on the gate electrode, masking only a predetermined region, and removing other unreacted tungsten. 5. An SRAM integrated circuit device comprising 6 MOS type memory cells including the local electrical connection structure according to claim 3. 6. A CMOS integrated circuit device comprising the local electrical connection structure according to claim 3. 7. In electrical connection between one conductivity type layer and a conductivity type layer opposite to the one conductivity type layer, a reaction product of silicon and an alloy consisting of tungsten and another metal element is used as the electrical connection material. An electrical connection structure between two conductivity type layers, characterized in that it is a part of an object or a structure.