JPH02204832A - Instruction control system - Google Patents

Abstract

PURPOSE:To contrive the decrease of the total quantity of an instruction code by generating an operand address included in control information by accumulating the address of an address part at every repetition in accordance with designation of an increase/decrease designating part and increasing/decreasing it at every prescribed number. CONSTITUTION:This system is provided with a prescribed address part for designating the address of an operand to an instruction code, a frequency designating part and an increase/decrease designating part. In this state, a control mechanism 23 generates control information generated from the instruction code repeatedly by the number of times determined by the designation of the frequency designating part, supplies it to an arithmetic mechanism 22, and generates an operand address included in this control information by accumulating the address of the address part at every its repetition in accordance with the designation of the increase/decrease designating part and increasing/ decreasing it at every prescribed number. Accordingly, the operation of the number of times equivalent for the execution by conventional plural instruction codes can be executed by one instruction code. In such a manner, the decrease of a necessary memory quantity of the instruction code can be contrived.

Description

[Detailed Description of the Invention] [Summary] An instruction that can reduce the total amount of memory for instruction codes required for required processing regarding the arithmetic instructions of a processing unit in a computer that is composed of arithmetic units with a relatively short bit width. A processing device for the purpose of a control system, which has a control mechanism that reads an instruction code from a memory and supplies control information according to the instruction code to an arithmetic mechanism, and the arithmetic mechanism that executes a predetermined operation using the supplied control information. , the instruction code is provided with a predetermined address section, a number specification section, and an increase/decrease specification section, and the control mechanism repeatedly generates the control information a number of times determined by the specification of the number specification section, and executes the operation. The operand address supplied to the mechanism and included in the control information is generated by accumulating the address in the address part by a predetermined number at each repetition according to the designation of the increase/decrease designation part.

[Industrial application field]

The present invention provides an instruction control method for arithmetic instructions that can reduce the total amount of memory for arithmetic instructions, especially instruction codes necessary for performing required processing, in a processing unit configured with an arithmetic unit with a relatively short bit width in a computer. Regarding.

[Conventional technology]

2. Description of the Related Art There is a so-called parallel computer that configures a computer with relatively high performance using a relatively small processing device by dividing required processing among a large number of processing devices and having those processing devices execute the processing in parallel.

One method for configuring each processing device that makes up such a parallel computer is to use a processing device that processes operations with a relatively short word length, for example, 1 bit length. When processing data with a word length such as 8 bits or 32 bits, it is necessary to complete the calculation for the required word length by repeating the calculation for each bit, for example.

To do this, when processing W-bit word data, for example, as shown in the processing flow in FIG. A repeating program using a loop as shown in FIG. 4(b) is created to perform the required 1-bit operation W times. Note that each step in the figure corresponds to approximately one instruction, OPI and OP2 shown in each step represent the operation of the instruction that performs the required operation, and the first bit is used to refer to the previous operation result, etc. Generally, it is assumed that there is a different process for the second and subsequent bits.

In addition, in FIG. 4 (5), Step I is the setting of the number of calculations (W) for repetition control, Step 2 is the calculation of the first bit, and Steps 3 to 5 are the calculations for the second and subsequent bits. In order to repeat the 1-bit operation, step 3 processes a subtraction instruction that reduces the number of operations by 1, step 4 processes a branch instruction to identify the remaining number of operations and terminates, and step 5 processes the 1-bit operation and the next operand. Processes instructions that advance the address to.

FIG. 5 is a block diagram showing an example of the configuration of a processing device that executes the above processing, and includes a code memory 10 that stores instruction codes, and an arithmetic mechanism 1 that executes operations according to the instruction codes.
2, and the code memory 10 according to the instruction address to be held.
The control unit 11 sequentially reads out instruction codes from and supplies them to the arithmetic unit 12, and controls the next instruction address by incrementing the instruction address and branching instructions.

The arithmetic mechanism 12 has an operation code (indicated by OP in the figure) of the instruction register 13 for each predetermined width (for example, 1 bit) data input from the instruction registers 13, 1, inl, and in2 that hold one instruction code. It has an arithmetic unit 14 that executes various operations according to the following, a register group 15 that holds a plurality of data of the predetermined width, and an external memory 16 that stores the data.

Many instruction codes for arithmetic instructions are, for example, instruction register 1.
As shown in FIG. 3, the 02 part of each predetermined bit length and each baud (a, b,
c section and a memory address section that specifies the external memory 16, reads the data of the register specified by the port 3 section and the port 5 section from the register group I5, inputs it to inl and in2 of the arithmetic unit 14, and inputs it to the arithmetic unit 14. The basic format is to store the data of the operation result output from port 14 in the register specified by port C part of register group 15. For example, by specifying part 02, memory address part The data in the external memory 16 specified by is used as an operand.

[Problem to be solved by the invention]

As is clear from the above processing flow, the length of the instruction code of each 1-bit operation instruction is determined by the length of the instruction code. In terms of bits, the total number of bits of the instruction code is (a) in Figure 4: b=w10, and (b): o2>2L.

It takes.

The object of the present invention is to provide an instruction control method that can reduce the total amount of instruction codes in such processing.

[Means to solve the problem]

FIG. 1 is a block diagram showing the configuration of the present invention.

The figure shows the configuration of a processing device, in which 20 is a code memory that stores instruction codes, 21 is an instruction register that holds instruction codes read from the code memory 20, 22 is an arithmetic mechanism that executes arithmetic instructions, and 23 is a code memory that stores instruction codes. A control unit 24 that reads into the instruction register 2I and supplies control information generated from the instruction code of the instruction register 21 to the arithmetic mechanism 22.
It is a system consisting of 211 systems.

[For production]

a code memory 20 that holds an instruction code; a control mechanism 23 that reads the instruction code from the code memory 20 and supplies control information according to the instruction code to the arithmetic mechanism 22;
In a processing device having an arithmetic mechanism 22 that executes a predetermined operation based on the supplied control information, the instruction code includes a predetermined address section that specifies the address of the operand, a number specification section, and an increase/decrease specification section. establish.

The control mechanism 23 repeatedly generates the above-mentioned control information generated from the instruction code a number of times determined by the designation of the number of times specifying section, supplies it to the arithmetic mechanism 22, and increases or decreases the address of the address section of the operand address included in this control information. According to the designation of the designation section, the number is accumulated and increased or decreased by a predetermined number each time it is repeated.

This control method allows one instruction code to perform the same number of operations as conventional multiple instruction codes, thereby reducing the amount of memory required for the instruction code.

〔Example〕

The instruction code according to the present invention specifies an increase/decrease in the 02 part, the boat 3 part, the boat 5 part, the boat C part, and the memory address part, as in the conventional example, as detailed in the instruction register 21 in FIG. (ud) Division and number of times specification (times)
section will be added. Furthermore, if necessary, the 02 part shall include a cr bit.

The control section 24 of the control mechanism 23 holds an instruction address as in the past, and when one instruction code is read from the code memory 20 using the instruction address, the instruction register 2
Hold at 1.

The instruction register 21 holds a register 30 holding a 02 part, a port 3 part, a boat 5 part, a port C part, and a memory address part, and includes counters 31 to 34 having functions of adding and subtracting a predetermined value (for example, 1), and a ud part. , a counter 36 that holds a times section and has a -1 function.

The control unit 24 passes the 02 part of the register 30 out of the contents of the instruction code held in the register 21 via the CR change unit 7, and outputs the contents of the counters 31 to 34 as control information to the arithmetic mechanism 22. When the instruction codes are first read out, they are passed to the arithmetic unit 22 without changing the contents.

The arithmetic mechanism 22 has, for example, the same configuration as the conventional arithmetic mechanism 12, and executes arithmetic operations in the same manner as in the past by setting control information supplied by the control mechanism 22 in the instruction register 13.

The contents of the ud part and times part of the instruction code are stored in the control unit 2.
4 reads from register 35 and counter 36 and tim
The control information is transferred to the arithmetic mechanism 22 by repeating the number of times specified in the es section. However, in this case, the counters 31 to 34 are controlled, and for example, the counter 3 is
Increase each content of 1 to 34 by 1 or decrease by 1. The direction of increase/decrease is determined by the ud section.

Through this control, the same control information as in the case of executing conventional arithmetic instructions by the number of repetitions is sequentially transferred to the arithmetic unit 22.

FIG. 2 is a process flow chart showing the above-mentioned control by the control unit 24. Starting from process step 40, an instruction code is read from the code memory and set in the instruction register 21, and in process step 41, the first control information is transferred. Then,
If the count value of the counter 36 is greater than 1 in processing step 42, the ud in the register 35 is identified in processing step 43, and if the increase/decrease designation value is 1, it is determined to be an increase, and if it is 0, it is determined to be a decrease. For example, in processing step 44, counters 31 to 34 are controlled to
The address of the section and the memory address section are incremented by 1, and the counter 36 is controlled to increment the number of times by 1, and the updated control information is passed to the arithmetic mechanism in processing step 4I.

If the ud part is designated to decrease, the addresses of the counters 31 to 34 are incremented by 1, and the counter 36 is always incremented by 1, as shown in process step 45, and the process proceeds to process step 41.
By repeating the above control at an appropriate timing synchronized with the arithmetic mechanism 22 until the number of times becomes 1 in processing step 42, if times of the original instruction code is W, then
When the control information is rotated at W rotation speed and the count value of the counter 36 reaches 1, the process returns to step 40 and the next instruction code is read out as described above.

In the above control, the contents of part 02 to be transferred as control information are controlled by the cr change change part 7, and according to the specified operation code, the value of the cr bit is passed through as is in the case of a logical operation, and the value of the cr bit is passed through as is in the case of an arithmetic operation. In this case, only the first control information is set as the specified value, and the second and subsequent control information are forcibly set to c.
The r bit is set to 0 and sent to the arithmetic unit 22.

The arithmetic mechanism 22 holds a carry of the immediately previous arithmetic result,
If the value of the cr bit is O, the value of the held carry is added to the operation, and if the value of the Cr bit is 1, the held carry is ignored in the operation, and as a result of the above, the instruction that uses the carry does not use it. To enable instruction control information to be generated from one instruction code.

FIG. 3(a) is an example of an instruction to add each W bit data at address X and y of the register and store it at address 2. Control information and register 35 transferred to
The specified increase/decrease value and the contents of the count value of the counter 36 are
Shown in Figure (b). In this way, W-bit addition can be specified with one instruction code.

Estimating the amount of instruction code required by the q control method above, the amount required for the conventional case explained in FIG. 4(a) is as follows:
For a program with N processing, the average data length of each processing target is W bits, and D
I=NLOW. - In the case of the Riki invention, the cr bit, t, is increased according to the invention for each instruction code.
The lengths of imes part and ud part are respectively L Crs Lt
, Lu4, the required amount of D bits is DN (Lo + Lc-+ LL + Lud). Therefore, when W=1, the amount of conventional instruction codes required is naturally smaller.

In the case of W≧2, DI-D=NL* (W-1) -N (Lc, +Lt +t, u, t)=NL, (W-
2) +N (LO< t, c, 10Lt + Lo) 1. Now, divide Lo into the operation code part L 69 excluding cr and the other L am, t, , = L,,
+ Lad, and since Lc, = L, , = 1, D
ID=NLO(W-2) +N ((L, p-2)+ (L, t-Lt)).

It can be considered that L, that is, the address part, is not shorter than Lu, that is, the times part, and since there are usually eight or more types of operation codes, Lo, ≧3, so under this condition, the right side of the above equation is always positive. That is, >D, and therefore the amount of instruction code required by the scheme of the present invention is always smaller. The required it o t bits in the case of FIG. 4(b) are [1z==2 NLII, therefore, -D is W=2 in the above equation of o and -D.
The result is the same as in the case of

Although the instructions for 1-bit arithmetic operations have been described above, the same control system can be applied to arithmetic instructions for which a word of 2 bits or more is processed as a unit. In that case as well, the above comparison formula holds true in the same way, and it is clear from the above calculation that the present invention is effective in processing two or more words.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, it is possible to reduce the total amount of memory for instruction codes required for required processing in computer arithmetic instructions, thereby significantly improving the economy and performance of the computer system. It has industrial effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the present invention, FIG. 2 is an explanatory diagram of the processing of the control unit of the present invention, FIG. 3 is an explanatory diagram of an example of an instruction code of the present invention, and FIG. 4 is a diagram of conventional instructions. FIG. 5, which is an explanatory diagram of processing, is a block diagram showing an example of a conventional configuration. In the figure, 10 and 20 are °code memory', 11.24 is a control unit,
12.22 is an arithmetic mechanism, 13.21 is an instruction register, 14 is an arithmetic unit, 15 is a register group, 16 is an external memory, 23 is a control system, 30 and 35 are registers, 31 to 34.36 are counters, 37 is cr
An explanatory diagram of the processing of the control unit of the present invention (rEJ et al.) Fig. 3 An explanatory diagram of an example of the instruction code of the present invention Fig. 1 A block diagram of the remaining configuration of the present invention Fig. 1 An explanatory diagram of the processing by conventional instructions No. 4 figure

Claims (1)

[Scope of Claims] A control mechanism (23) that reads an instruction code from a memory (20) and supplies control information according to the instruction code (21) to an arithmetic mechanism, and executes a predetermined operation using the supplied control information. In the processing device having the arithmetic mechanism (22), the instruction code includes a predetermined address part, a number-of-times designation part,
an increase/decrease designation section, the control mechanism (23) repeatedly generates the control information a number of times determined by the number of times designation section, and the control mechanism (23) repeatedly generates the control information a number of times determined by the number of times designation section.
22), and generates the operand address included in the control information by cumulatively incrementing and decrementing the address in the address part by a predetermined number at each repetition according to the specification of the increase/decrease designation part. A command control method characterized by: