JPH02205131A - Phase matching circuit - Google Patents

Abstract

PURPOSE:To reduce delay in output data by performing phase matching by changing the temporal position of a time slot which stores the forefront instructing information of input data, and correcting the forefront instructing information corresponding to the change of the temporal position. CONSTITUTION:The input data DIN inputted from a write side is separated to data D1 and the forefront instructing information D2 by a forefront instructing information detection circuit 4. The data D1 of one frame is stored in a temporal memory circuit 2. Meanwhile, the forefront instructing information D2 is inputted to a forefront instructing information correction circuit 5. When a frame pulse G according to the instruction of a readout side is outputted to the temporal memory circuit 2 and the forefront instructing information correction circuit 5, the data D1 is outputted from the temporal memory circuit 2 to a forefront instructing information insertion circuit 6, and also, the forefront instruction information D3 corrected corresponding to the frame pulse G is outputted from the forefront instructing information correction circuit 5 to the forefront instructing information insertion circuit 6, and it is inserted to the data D1, and read out as the output data DOUT to the readout side.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement of a phase matching circuit that matches the phases of data input from several directions and outputs the same.

[Conventional technology]

FIG. 3 is a block diagram of a conventional phase matching circuit, and FIG. 2(a) shows an input monitor DI input to the phase matching circuit.
2 (cC shows the field data D. UT output from this phase matching circuit.

First, the structure of input data DIN will be explained.

As shown in FIG. 2(a), the input data DIN includes time slots TSI to TS7 constituting one frame, and a time slot TD for storing start position information indicating the position of time slot jTs1, that is, the start position of the frame. It is composed of. Note that, as shown in FIG. 2(a), the time slot TO is the time slot TS
It is inserted between 1 and TS7, and its insertion position is not limited.

Next, a conventional phase matching circuit will be explained with reference to FIG. Reference numeral 1 denotes a leading detection circuit that detects leading position information included in input data DIN inputted from the writing side (not shown) and outputs a frame pulse F for identifying the frame indicated by this leading position information. Reference numeral 2 denotes a temporary storage circuit that stores data for one frame, ie, time slots TSI-T87 and TD, in accordance with the frame pulse F. Reference numeral 3 denotes a head instruction circuit that outputs a frame pulse G according to an instruction from the reading side (not shown). Next, the operation will be explained. The head detection circuit 1, which receives the input data DIN from the writing side, outputs a monitor frame pulse F when it detects the time slot TD. According to this frame pulse F, the temporary storage circuit 2 stores data for one frame. Further, the head instruction circuit 3 outputs a frame pulse G according to an instruction from the reading side. According to this frame pulse G, the temporary storage circuit 2 reads data for one frame and reads out the data DO1J.
Output as T to the reading side.

[Problem to be solved by the invention]

Therefore, a plurality of input data DIN having different phases are inputted, and the phases of the time slots (TO) for storing the start position information indicating the start position of the frame of the input data DIN are matched to output data D. When trying to obtain υ1,
Time slot of input data D with the most phase delay) TD
In order to match the phase of the time slot TO of the other input data DIN with the phase of the other input data DIN, it is necessary to always delay and output the frame of the other input data DIN by the phase difference between the two time slots TD. There were deficiencies. For example, if the phase difference between the two time slots (TO) is three time slots, the input data that is one phase ahead is DIN is output data D that is always delayed by three time slots. U? I had to output it as .

[Means to solve the problem]

The phase matching circuit of this invention has the following means.

(a) A head indication information detection circuit that inputs data having head indication information indicating the head position of the data and separates and outputs this head indication information and a data section other than this head indication information, Can) From the reading side (C) A temporary storage circuit that inputs and stores the data portion from the head instruction information detection circuit and outputs this data portion according to the output instruction signal; (d) A temporary storage circuit that outputs the data portion according to the output instruction signal; a leading instruction information correction circuit that corrects and outputs the leading instruction information input from the instruction information detection circuit in accordance with an output instruction signal; (e) data that is corrected by the leading instruction information correction circuit and outputs the nine leading instruction information from the temporary storage circuit; Leading instruction information insertion circuit that inserts into the section and outputs it.

[Effect]

The temporal position of the time slot in which the head indication information of the input data is stored is changed to help align the phase of this time slot, and the head indication information is modified in accordance with the change in the time position.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention,
The same reference numerals as in FIG. 3 indicate corresponding parts.

4 inputs input data DIN to time slots TSI to TS7.
This is a head instruction information detection circuit that separates and outputs data D1 for one frame corresponding to data slot TD and head instruction information D2 corresponding to data slot TD.

Reference numeral 5 denotes a start instruction information detection circuit that corrects the start instruction information D2 inputted from the start instruction information detection circuit 4 according to the frame pulse (output instruction signal) G inputted from the start instruction circuit 3, and outputs the start instruction information D3. Reference numeral 6 denotes a head indication information insertion circuit which inserts the head indication information 03 outputted from the head indication information correction circuit 5 into one frame of data D1 outputted from the temporary storage circuit 2 and outputs it to the reading side.

Before explaining the operation here, the head instruction information will be described. As shown in FIG. 2(a), the leading instruction information includes the time slot TD and time slot TSI in which this leading instruction information is stored.

That is, it indicates the relative position to the beginning position of the frame, and the time slot may be inserted at any position. Also, output data D. LITO phase alignment is achieved by aligning the time positions of time slots) TD, and each time slot) TSI to T8.
There is no need to align for 70 hours. Therefore, in order to match the phases, it is only necessary to change the position of the time slot TD and to modify the head instruction information of this time slot TD.

Next, the operation will be explained.

Input data DIN input from the writing side is detected by the head instruction information detection circuit 4 in time slots) TS1 to TS7.
11C@The corresponding data DI and time slot) TDK are separated into the corresponding leading instruction information D2. Data D1 for one frame is stored in the temporary storage circuit 2. On the other hand, the head indication information D2 is input to the head indication information correction circuit 5. When the frame pulse G according to the instruction on the reading side is output to the temporary storage circuit 2 and the head instruction information correction circuit 5, data DI is output from the temporary storage circuit 2 to the head instruction information insertion circuit 6. Along with this, the head indication information correction circuit 5 to the head indication information insertion circuit 6K.

Leading instruction information 03 modified according to frame pulse G
is output, inserted into the data D1, and read out on the reading side as output data Dot, 〒.

FIG. 2(b) shows output data in this embodiment.

As can be seen from Figure 2), the delay at the beginning of the data frame is equal to the time slot TD.

In other words, it corresponds to one time slot. On the other hand, the second
In the conventional example shown in FIG. 3C, the leading position of the data frame must be delayed by the phase difference of the input data (in this example, by three time slots).

〔Effect of the invention〕

As explained above, the phase adjustment circuit of the present invention adjusts the phase of the time slot by changing the time position of the time slot that stores the head indication circuit, and also modifies the head indication information in accordance with the change in the time position. This has the effect that the delay of the Tagata data output from this phase matching circuit can be shortened compared to the conventional method.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a timing diagram of input/output data in the same embodiment and a conventional example, and FIG. 3 is a block diagram showing a conventional example. 2...Temporary memory circuit, 3...Start instruction circuit, 4
...Taste/head instruction information detection circuit, 5@...Top instruction information detection circuit, 6...Top instruction information insertion circuit, DIN
...Input data, DOVT...Output data, D
l...Data, D2...Start instruction information, D3...
...-Corrected head instruction information, G...frame pulse (output instruction signal).

Claims (1)

[Scope of Claims] A head indication information detection circuit that inputs data having head indication information indicating the head position of data, and separates and outputs this head indication information and a data section other than this head indication information; a head instruction circuit that outputs an output instruction signal in accordance with an instruction from the side; and a temporary memory that inputs and stores the data portion from the head instruction information detection circuit and outputs the data portion in accordance with the output instruction signal. a start instruction information correction circuit that corrects and outputs the start instruction information inputted from the start instruction information detection circuit in accordance with the output instruction signal; 1. A phase matching circuit comprising a head instruction information insertion circuit that inserts into and outputs the data section output from the temporary storage circuit.