JPH02205351A - Resin seal type semiconductor device - Google Patents

Resin seal type semiconductor device

Info

Publication number
JPH02205351A
JPH02205351A JP1026218A JP2621889A JPH02205351A JP H02205351 A JPH02205351 A JP H02205351A JP 1026218 A JP1026218 A JP 1026218A JP 2621889 A JP2621889 A JP 2621889A JP H02205351 A JPH02205351 A JP H02205351A
Authority
JP
Japan
Prior art keywords
stage
lead frame
semiconductor device
resin
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1026218A
Other languages
Japanese (ja)
Other versions
JP2506429B2 (en
Inventor
Masanori Yoshimoto
吉本　正則
Yuzo Hamanaka
雄三 濱中
Kazumi Ebihara
蛯原　一美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyushu Fujitsu Electronics Ltd
Fujitsu Ltd
Original Assignee
Kyushu Fujitsu Electronics Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyushu Fujitsu Electronics Ltd, Fujitsu Ltd filed Critical Kyushu Fujitsu Electronics Ltd
Priority to JP1026218A priority Critical patent/JP2506429B2/en
Publication of JPH02205351A publication Critical patent/JPH02205351A/en
Application granted granted Critical
Publication of JP2506429B2 publication Critical patent/JP2506429B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔概　要〕 樹脂封止型半導体装置に関し、 プリント基板等外部回路への装着時におけるパッケージ
モールドのクランク発生を防止することを目的とし、 リードフレームのステージ上に半導体チップを搭載し、
該半導体チップ上の複数の電極と該各電極に対応して上
記ステージの周囲に配置された該リードフレームの配線
電極との間をワイヤボンディングし、上記半導体チップ
とワイヤボンディング部分を上記ステージと共に樹脂封
止した樹脂封止型半導体装置であって、上記リードフレ
ームのステージが、半導体チップ搭載面の裏面に散在配
置した複数の突起および該ステージの周囲に沿い該突起
と等しい高さの閉ループをなす壁を備えて構成する。[Detailed Description of the Invention] [Summary] Regarding a resin-sealed semiconductor device, the semiconductor chip is placed on the stage of a lead frame for the purpose of preventing cranking of the package mold when it is attached to an external circuit such as a printed circuit board. Equipped with
Wire bonding is performed between the plurality of electrodes on the semiconductor chip and wiring electrodes of the lead frame arranged around the stage corresponding to each electrode, and the semiconductor chip and the wire bonding portion are bonded to resin together with the stage. A resin-sealed semiconductor device, wherein the stage of the lead frame has a plurality of protrusions scattered on the back side of the semiconductor chip mounting surface and a closed loop having the same height as the protrusions along the periphery of the stage. Construct with walls.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置に係り、特にプリント基板等外部回
路への装着時におけるパッケージモールドのクラック発
生を防止して特性の向上と生産性の向上を図った樹脂封
止型半導体装置に関する。The present invention relates to a semiconductor device, and more particularly to a resin-sealed semiconductor device that prevents cracks in a package mold when attached to an external circuit such as a printed circuit board, thereby improving characteristics and productivity.

〔従来の技術〕[Conventional technology]

第２図は従来の樹脂封止型半導体装置の一例を示す図で
あり、（Ａ）は全体の構成断面図をまた（Ｂ）はステー
ジ単体の形成工程を裏面側から見た状態で示す図、（Ｃ
）はステージのメツキ工程を示す図である。FIG. 2 is a diagram showing an example of a conventional resin-sealed semiconductor device, in which (A) is a cross-sectional view of the overall configuration, and (B) is a diagram showing the formation process of a single stage as seen from the back side. , (C
) is a diagram showing the stage plating process.

図（Ａ）で半導体チップ２は、例えば厚さ０．１ｍｍで
その表面の少なくともステージ４ａを含む所定領域に銀
（Ａｇ）メツキ３が施された４２７０イ合金等よりなる
リードフレーム４の該ステージ４ａ上に、銀ペースト等
で接着固定されている。In Figure (A), the semiconductor chip 2 is mounted on a lead frame 4 made of a 4270-alloy or the like having a thickness of 0.1 mm and having a silver (Ag) plating 3 on a predetermined area including at least the stage 4a on its surface. It is adhesively fixed onto 4a with silver paste or the like.

そこで、上記半導体チップ２上の複数の電極とステージ
４ａの周囲に上記各電極に対応して配置したリードフレ
ーム４の配線電極とをワイヤ５でボンディング接続した
後、少なくとも上記半導体チップ２を含むステージ４ａ
と上記ワイヤ５が完全に覆われるようにエポキシ系樹脂
６等で封止して樹脂封止型半導体装置１を構成している
。Therefore, after bonding the plurality of electrodes on the semiconductor chip 2 and the wiring electrodes of the lead frame 4 arranged around the stage 4a corresponding to the respective electrodes using the wires 5, the stage including at least the semiconductor chip 2 is 4a
The resin-sealed semiconductor device 1 is constructed by sealing with an epoxy resin 6 or the like so that the wires 5 are completely covered.

かかる樹脂封止型半導体装置１をプリント基板等の外部
回路に搭載するには、該樹脂封止型半導体装置１の外部
に露出している上記リードフレーム４の配線電極部分を
上記の外部回路に半田等の手段で接続固定するが、この
接続時には通常約２００°Ｃ程度まで加熱される。In order to mount this resin-sealed semiconductor device 1 on an external circuit such as a printed circuit board, the wiring electrode portion of the lead frame 4 exposed to the outside of the resin-sealed semiconductor device 1 is connected to the external circuit. The connection is fixed by means such as soldering, but the connection is usually heated to about 200°C.

この際、リードフレーム４の材料と封止樹脂材６の間特
にステージ４８部分では熱膨張係数の差によって発生す
る界面部分での内部応力が該界面部分を剥離させたり封
止樹脂材６にクラックを生ずるが、上記リードフレーム
４のステージ４ａの封止樹脂材６と接する面が平坦な場
合には特にこの傾向が強くなることが知られている。At this time, internal stress at the interface between the material of the lead frame 4 and the sealing resin material 6, particularly at the stage 48 portion, occurs due to the difference in thermal expansion coefficients, causing the interface portion to peel off or cracking in the sealing resin material 6. However, it is known that this tendency becomes particularly strong when the surface of the lead frame 4 in contact with the sealing resin material 6 of the stage 4a is flat.

そこでこれを防止するため、−ａには上記ステージ４ａ
の封止樹脂材６と接する面に図示の如き微小な突起４ｂ
が生ずるように該リードフレーム４を加工して凹凸を付
与するようにしている。Therefore, in order to prevent this, -a has the above-mentioned stage 4a.
A minute protrusion 4b as shown in the figure is formed on the surface in contact with the sealing resin material 6.
The lead frame 4 is processed to provide unevenness so that the unevenness is generated.

この微小な凹凸を付与する方法を説明する図（Ｂ）は、
理解し易くするために図（Ａ）におけるリードフレーム
４を裏面側から見た状態で表わしており、（１）は成形
したままのリードフレーム４のステージ４ａ近傍を示し
また（２）は凹凸を付けた状態を示している。Diagram (B) illustrating the method of providing this minute unevenness is
For ease of understanding, the lead frame 4 in Figure (A) is shown as seen from the back side, and (1) shows the vicinity of the stage 4a of the lead frame 4 as formed, and (2) shows the unevenness. It shows the attached state.

図（１）で成形したままのリードフレーム４は、はぼ中
央部に５〜１０ｍｍ角のステージ４ａと該ステージ４ａ
を保持する例えば２個の保持部４ｃおよび該ステージ４
ａを取り囲んでその周囲に放射状に形成した複数の配線
電極４ｄとで構成されている。The as-molded lead frame 4 shown in FIG.
For example, two holding parts 4c and the stage 4 that hold the
It is composed of a plurality of wiring electrodes 4d surrounding a and radially formed around it.

ここで該リードフレーム４の片面に、ステージ４ａより
多少大きい例えば図の一点鎖線で示す領域Ｓの部分を通
常のエツチング手段を用いて該リードフレーム４の厚さ
の５０〜６０％程度例えば０．０５〜０．０６ｍ５＋位
の範囲にエツチング除去するが、この際複数（図では９
個）の円形状の突起４ｂが残るように該エツチング処理
を施して図（２）に示す状態としている。Here, on one side of the lead frame 4, for example, a region S, which is slightly larger than the stage 4a and indicated by the dashed line in the figure, is etched by about 50 to 60% of the thickness of the lead frame 4, for example, by using a normal etching means. Etching is performed in the range of 0.05 to 0.06 m5+, but at this time, multiple
The etching process is performed so that the circular protrusions 4b (2) remain, resulting in the state shown in FIG. 2 (2).

次いで、該ステージ４ａの平坦面部分すなわち図（Ｂ）
の裏面側に図（Ａ）で説明した半導体チップ２を導通を
保って接着固定するため、少なくとも該ステージ４ａの
平坦面部分を含むリードフレーム４の所定領域に銀（Ａ
ｇ）メツキ処理を施す。Next, the flat surface portion of the stage 4a, that is, FIG.
In order to adhesively fix the semiconductor chip 2 described in FIG.
g) Perform plating treatment.

図（Ｃ）はメツキ処理工程を説明する図であり、図（Ｂ
）をｃ−ｃ’で切断した断面を上下反転させて正規の方
向になるように示している。Figure (C) is a diagram explaining the plating process, and Figure (B
) taken along c-c' is shown upside down so that it is in the normal direction.

図で、■は図（Ｂ）の（１）に対応しまた■は図（Ｂ）
の（２）に対応するものである。In the figure, ■ corresponds to (1) in figure (B), and ■ corresponds to figure (B).
This corresponds to (2).

ここで■に示す如く該ステージ４ａの突起４ｂ側の全面
に平坦なマスク７を添着被覆した後、通常の方法で銀メ
ツキ処理を施すが、図（Ｂ）で説明した如く複数の突起
４ｂは散在するように配置されているためメツキ処理液
が各突起間に流入し、結果的に図■に示す如く銀メツキ
層３はマスク７が密着している突起４ｂの先端面を除く
全面に形成されることになる。Here, after applying a flat mask 7 to the entire surface of the protrusion 4b side of the stage 4a as shown in (2), a silver plating process is performed in the usual manner. Since they are arranged in a scattered manner, the plating processing liquid flows between each protrusion, and as a result, as shown in Fig. will be done.

一方、この銀メツキ層は封止樹脂材料との密着性が芳し
くない。On the other hand, this silver plating layer has poor adhesion to the sealing resin material.

従ってかかる構成になる樹脂封止型半導体装置では、プ
リント基板等の外部回路に装着する際の熱によって封止
樹脂材料との間の剥離やクランクの発生を完全に防止す
ることができず、特性および生産性の向上を阻害する要
因となっている。Therefore, in a resin-sealed semiconductor device having such a configuration, it is not possible to completely prevent the peeling from the sealing resin material and the occurrence of cranks due to the heat generated when mounting it on an external circuit such as a printed circuit board, and the characteristics and is a factor that hinders productivity improvement.

なお封止樹脂材料と接する面にメツキ層３が形成されな
いようにするには上記マスク７を該ステージ４ａの凹凸
に合わせて加工しなければならず、価格的に得策でない
。In order to prevent the plating layer 3 from being formed on the surface in contact with the sealing resin material, the mask 7 must be processed to match the irregularities of the stage 4a, which is not a good idea in terms of cost.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来の樹脂封止型半導体装置では、プリント基板等の外
部回路に装着する際の熱による封止樹脂材料の剥離やク
ラックの発生を完全に防止することができないと言う問
題があった。Conventional resin-sealed semiconductor devices have a problem in that it is not possible to completely prevent the sealing resin material from peeling off or cracking due to heat when mounted on an external circuit such as a printed circuit board.

〔課題を解決するための手段〕[Means to solve the problem]

上記問題点は、リードフレームのステージ上に半導体チ
ップを搭載し、該半導体チップ上の複数の電極と該各電
極に対応して上記ステージの周囲に配置された該リード
フレームの配線電極との間をワイヤボンディングし、上
記半導体チップとワイヤボンディング部分を上記ステー
ジと共に樹脂封止した樹脂封止型半導体装置であって、
上記リードフレームのステージが、半導体チップ搭載面
の裏面に散在配置した複数の突起および該ステージの周
囲に沿い該突起と等しい高さの閉ループをなす壁を備え
てなる樹脂封止型半導体装置によって解決される。The above problem arises when a semiconductor chip is mounted on a stage of a lead frame, and between a plurality of electrodes on the semiconductor chip and wiring electrodes of the lead frame arranged around the stage corresponding to each electrode. A resin-sealed semiconductor device in which the semiconductor chip and the wire-bonded portion are resin-sealed together with the stage,
The solution is achieved by a resin-sealed semiconductor device in which the stage of the lead frame has a plurality of protrusions scattered on the back side of the semiconductor chip mounting surface, and a wall forming a closed loop with the same height as the protrusions along the periphery of the stage. be done.

〔作　用〕[For production]

封止樹脂材料の剥離やクランクの発生を防止するには、
クランク発生防止用の微小突起形成面側のステージ全面
が銀メツキされないことが必要である。To prevent peeling and cranking of the sealing resin material,
It is necessary that the entire surface of the stage on the side where the microprotrusions for preventing crank occurrence are formed is not silver plated.

本発明では、凹凸形成面側のステージ周囲を突起の高さ
と等しい閉ループをなす壁で完全に囲むように該ステー
ジを形成している。In the present invention, the stage is formed so that the periphery of the stage on the uneven surface side is completely surrounded by a wall forming a closed loop having the same height as the protrusion.

従って、該凹凸形成面を平坦なマスクでカバーしてもメ
ツキ処理液がマスクとステージの間に流入せず該凹凸形
成面がメツキされないことから、外部回路に装着する際
にも剥離やクランクの発生のない樹脂封止型半導体装置
を得ることができる。Therefore, even if the uneven surface is covered with a flat mask, the plating processing liquid will not flow between the mask and the stage and the uneven surface will not be plated. A resin-sealed semiconductor device without generation can be obtained.

〔実施例〕〔Example〕

第１図は本発明になる樹脂封止型半導体装置の一例を示
す図であり、（ａ）は全体の構成断面図をまた（ｂ）は
ステージ単体の形成工程を示す図、（Ｃ）はステージの
メツキ工程を示す図である。FIG. 1 is a diagram showing an example of a resin-sealed semiconductor device according to the present invention, in which (a) is a cross-sectional view of the entire configuration, (b) is a diagram showing the formation process of a single stage, and (c) is a diagram showing an example of a resin-sealed semiconductor device according to the present invention. It is a figure which shows the plating process of a stage.

図（ａ）で半導体チップ２は、第２図同様の方法でリー
ドフレーム１１のステージｌｌａ上に銀ペースト等で接
着固定しである。In FIG. 2A, a semiconductor chip 2 is adhesively fixed onto a stage lla of a lead frame 11 using silver paste or the like in the same manner as in FIG.

また該半導体チップ２上の複数の電極と該各電極に対応
する上記リードフレーム１１の配線電極とがワイヤ５で
ボンディング接続された後、エポキシ系樹脂６等で封止
して樹脂封止型半導体装置１０が構成されていることは
第２図と同様である。Further, after the plurality of electrodes on the semiconductor chip 2 and the wiring electrodes of the lead frame 11 corresponding to the respective electrodes are connected by bonding with the wires 5, the resin-sealed semiconductor is sealed with an epoxy resin 6 or the like. The structure of the device 10 is the same as that shown in FIG.

該ステージＩｌａ部分に凹凸を付加する方法を説明する
図（ｂ）は、第２図同様に図（ａ）のリードフレーム１
１を裏面側から見た状態で表わしており、（■）は成形
したままのリードフレーム１１をまた（ｎ）は凹凸を付
けた状態をそれぞれ示している。Figure (b), which explains the method of adding unevenness to the stage Ila portion, shows the lead frame 1 of Figure (a), similar to Figure 2.
1 is shown as viewed from the back side, (■) shows the lead frame 11 as molded, and (n) shows the state with unevenness.

図（１）で、成形したままのリードフレーム１１は、は
ぼ中央部に５〜１０ｍ＋ｗ角のステージｌｌａと該ステ
ージＩｌａを保持する例えば２個の保持部１１ｃおよび
該ステージｌｌａを取り囲むようにその周囲放射状に形
成した複数の配線電極ｌｉｄとで構成されていることは
第２図の場合と同様である。In Figure (1), the as-molded lead frame 11 has a stage lla of 5 to 10 m+w angle in the center, two holding parts 11c holding the stage lla, and a stage lla surrounding the stage lla. As in the case of FIG. 2, it is composed of a plurality of wiring electrodes lid formed radially around the periphery.

ここで、該リードフレーム１１の片面のステージ１１ａ
より僅かに小さい例えば図の一点鎖線で示す領域Ｓ＋の
部分のみを、第２図同様に複数（図では９個）の円形状
の突起が残るように通常の手段によってエツチング除去
する。Here, the stage 11a on one side of the lead frame 11 is
For example, only a slightly smaller area S+ shown by the dashed line in the figure is etched away by ordinary means so that a plurality of (nine in the figure) circular protrusions remain, as in FIG.

この場合には図（ｎ）に示す如（、該ステージ１１ａの
片面に複数の突起１１ｂと共にその周囲に該突起１１ｂ
と同じ高さの壁Ｌｉｅが残る。In this case, as shown in FIG.
A wall of the same height remains.

メツキ処理を施す工程を説明する図（Ｃ）は、図（ｂ）
をＣ−Ｃ’で切断した断面を上下反転させて表わしてい
る。Diagram (C) explaining the plating process is diagram (b)
The cross section taken along line CC' is shown upside down.

図で、（イ）は図ら）の（Ｉ）に対応しまた（口）は図
ら）の（ＩＩ）に対応するものである。In the figure, (a) corresponds to (I) in figure et al., and (mouth) corresponds to (II) in figure et al.

ここで（ハ）に示す如く該ステージｌｌａの突起１１ｂ
側の全面に第２図同様のマスク７を添着して咳面を被覆
した後、通常の方法で銀メツキ処理を施すが、複数の突
起１１ｂが散在して配置されていても図（ｂ）で説明し
た如くその周囲が該突起１１ｂと同じ高さの壁ｌｉｅで
囲まれているため銀メツキ液の流入がなく、結果的に図
（ニ）に示す如く銀メツキ層３は凹凸形成面内には形成
されない。Here, as shown in (c), the protrusion 11b of the stage lla
After covering the coughing surface by attaching a mask 7 similar to that shown in FIG. As explained above, since the periphery of the protrusion 11b is surrounded by a wall having the same height as that of the protrusion 11b, there is no inflow of the silver plating solution, and as a result, the silver plating layer 3 is formed within the uneven surface as shown in Figure (d). is not formed.

従ってかかる構成になる樹脂封止型半導体装置では、封
止樹脂材料がステージｌｌａの凹凸形成面側の壁１１ｃ
の内部で銀メツキ層を介することなく直接ステージｌｌ
ａの凹凸形成面と接することから、接触面積の拡大とあ
いまって該封止樹脂材料のステージｌｌａに対する密着
性が向上し、プリン）！板等の外部回路に装着する際の
熱による封止樹脂材料の剥離やクラックの発生を完全に
防止することができる。Therefore, in the resin-sealed semiconductor device having such a configuration, the sealing resin material is the wall 11c of the stage lla on the uneven surface side.
stage II directly without using a silver plating layer inside the
Since it is in contact with the uneven surface of a, the contact area is expanded and the adhesion of the sealing resin material to the stage lla is improved, and the pudding)! It is possible to completely prevent the sealing resin material from peeling off or cracking due to heat when attached to an external circuit such as a board.

〔発明の効果〕〔Effect of the invention〕

上述の如く本発明により、プリント基板等の外部回路に
装着しても剥離やクランク等が発生することのない特性
および生産性に優れた樹脂封止型半導体装置を提供する
ことができる。As described above, according to the present invention, it is possible to provide a resin-sealed semiconductor device which has excellent characteristics and productivity and does not cause peeling or cranking even when attached to an external circuit such as a printed circuit board.

なお本発明の説明に当たっては、リードフレームのステ
ージ片面に形成する突起を円柱状に形成した場合につい
て行っているが、その断面を三角。In the description of the present invention, the protrusion formed on one side of the stage of the lead frame is cylindrical, but its cross section is triangular.

四角等何れの形状にしても同様の効果を得ることができ
る。The same effect can be obtained by using any shape such as a square.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明になる樹脂封止型半導体装置の一例を示
す図、 第２図は従来の樹脂封止型半導体装置の一例を示す図、 である。図において、 ２は半導体チップ、　　　３はメツキ層、５はワイヤ、
　　　　　　６は封止樹脂材、７はマスク、 １０は樹脂封止型半導体装置、 １１はリードフレーム、　　ｌｌａはステージ、１１ｂ
は突起、　　　　　　ｌｌｃは保持部、ｌｉｄは配線電
極、　　　　ｌｉｅは壁、をそれぞれ表わす。 Ｉ　ｌ　図 ９東ｆ）＃旨打止型ギ導６％￥Ｌ／）−夕）胤示イロ１
２　口FIG. 1 is a diagram showing an example of a resin-sealed semiconductor device according to the present invention, and FIG. 2 is a diagram showing an example of a conventional resin-sealed semiconductor device. In the figure, 2 is a semiconductor chip, 3 is a plating layer, 5 is a wire,
6 is a sealing resin material, 7 is a mask, 10 is a resin-sealed semiconductor device, 11 is a lead frame, lla is a stage, 11b
is a protrusion, llc is a holding portion, lid is a wiring electrode, and lie is a wall. I l Fig. 9 East f) # Uchistop type Gi guide 6% ¥ L/) - Yu) Taneji Iro 1
2 mouths

Claims (1)

【特許請求の範囲】 リードフレームのステージ上に半導体チップを搭載し、
該半導体チップ上の複数の電極と該各電極に対応して上
記ステージの周囲に配置された該リードフレームの配線
電極との間をワイヤボンディングし、上記半導体チップ
とワイヤボンディング部分を上記ステージと共に樹脂封
止した樹脂封止型半導体装置であって、 上記リードフレームのステージが、半導体チップ搭載面
の裏面に散在配置した複数の突起および該ステージの周
囲に沿い該突起と等しい高さの閉ループをなす壁を備え
てなることを特徴とした樹脂封止型半導体装置。[Claims] A semiconductor chip is mounted on a stage of a lead frame,
Wire bonding is performed between the plurality of electrodes on the semiconductor chip and wiring electrodes of the lead frame arranged around the stage corresponding to each electrode, and the semiconductor chip and the wire bonding portion are bonded to resin together with the stage. A resin-sealed semiconductor device, wherein the stage of the lead frame has a plurality of protrusions scattered on the back side of the semiconductor chip mounting surface and a closed loop having the same height as the protrusions along the periphery of the stage. A resin-sealed semiconductor device characterized by having a wall.
JP1026218A 1989-02-03 1989-02-03 Resin-sealed semiconductor device Expired - Lifetime JP2506429B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1026218A JP2506429B2 (en) 1989-02-03 1989-02-03 Resin-sealed semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1026218A JP2506429B2 (en) 1989-02-03 1989-02-03 Resin-sealed semiconductor device

Publications (2)

Publication Number Publication Date
JPH02205351A true JPH02205351A (en) 1990-08-15
JP2506429B2 JP2506429B2 (en) 1996-06-12

Family

ID=12187263

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1026218A Expired - Lifetime JP2506429B2 (en) 1989-02-03 1989-02-03 Resin-sealed semiconductor device

Country Status (1)

Country Link
JP (1) JP2506429B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5440169A (en) * 1993-01-08 1995-08-08 Mitsubishi Denki Kabushiki Kaisha Resin-packaged semiconductor device with flow prevention dimples
EP0771029A3 (en) * 1995-10-24 1997-07-30 Oki Electric Ind Co Ltd Semiconductor device with improved structure to avoid cracks and manufacturing process

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5694760A (en) * 1979-12-28 1981-07-31 Nec Corp Semiconductor device
JPS6331147A (en) * 1986-07-24 1988-02-09 Nec Corp Lead frame of semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5694760A (en) * 1979-12-28 1981-07-31 Nec Corp Semiconductor device
JPS6331147A (en) * 1986-07-24 1988-02-09 Nec Corp Lead frame of semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5440169A (en) * 1993-01-08 1995-08-08 Mitsubishi Denki Kabushiki Kaisha Resin-packaged semiconductor device with flow prevention dimples
EP0771029A3 (en) * 1995-10-24 1997-07-30 Oki Electric Ind Co Ltd Semiconductor device with improved structure to avoid cracks and manufacturing process
US5864174A (en) * 1995-10-24 1999-01-26 Oki Electric Industry Co., Ltd. Semiconductor device having a die pad structure for preventing cracks in a molding resin
US6177725B1 (en) 1995-10-24 2001-01-23 Oki Electric Industry Co., Ltd. Semiconductor device having an improved structure for preventing cracks, improved small-sized semiconductor and method of manufacturing the same
US6459145B1 (en) * 1995-10-24 2002-10-01 Oki Electric Industry Co., Ltd. Semiconductor device having an improved structure for preventing cracks, and improved small-sized semiconductor
US6569755B2 (en) 1995-10-24 2003-05-27 Oki Electric Industry Co., Ltd. Semiconductor device having an improved structure for preventing cracks, improved small sized semiconductor and method of manufacturing the same

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