JPH02205908A - Data processor - Google Patents

Abstract

PURPOSE:To reduce the variance in inductance component by distributedly arranging clock drivers in an LSI to distribute the current flowing to the wiring. CONSTITUTION:Clock drivers which are arranged in plural positions in the LSI and have the same clock and the wiring for wired OR between their outputs are provided. That is, clock drivers 3 and 4 are distributed in plural positions in the LSI. Consequently, the internal clock is changed and a large current momently flows to an internal clock signal line 6 when the clock input is changed, but this large current distributedly flows to clock drivers 3 and 4. Thus, the variance due to inductance is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock driver, and particularly to a circuit system for speeding up the internal clock of an LSI having a clock input.

[Conventional technology]

With the recent development of process technology, LSIs such as microprocessors have become faster and more highly integrated.
Products that operate at high speeds have also been developed.

One of the problems in realizing such a highly integrated high-speed LSI is increasing the speed of the internal clock.

In other words, as LSIs become more highly integrated, when increasing the speed of the internal clock, it is no longer possible to obtain sufficient characteristics by considering only capacitance as a load, as in the past, and it is now necessary to consider inductance as well. .

[Problem to be solved by the invention]

Conventionally, this type of problem has progressed without any concrete countermeasures being taken. However, considering future increases in integration and speed, countermeasures to this problem are essential. Simply increasing the size of the clock driver for high capacitance loads as in the past has the disadvantage that a locked waveform cannot be obtained at the target operating frequency due to the inductance component.

[Means to solve the problem]

The clock driver of the present invention includes clock drivers with the same clock arranged at multiple locations inside an LSI, and wiring for wire-ORing the outputs of the clock drivers.

That is, in the present invention, the clock drivers are distributed at multiple locations inside the LSI, and the influence of the inductance component can be reduced.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

1 is a clock input terminal, 2 is an input buffer, 3.4 is a clock driver, 5 is an internal circuit, 6 is an internal clock signal line, and 7 is a signal line for transmitting the output of the input buffer 2 to the clock driver 4. When the clock input changes here, the internal clock changes and the internal clock changes instantaneously to the signal line 6.
A large current flows through. However, since this current is divided and flows between the clock drivers 3 and 4, fluctuations due to inductance can be reduced.

FIG. 2 is a block diagram of another embodiment of the invention. In this embodiment, a third clock driver 8 is provided,
The black and white drivers are distributed in three locations.

〔Effect of the invention〕

As explained above, the present invention allows the clock driver to
By arranging them in a distributed manner within the I, the current flowing through the wiring can also be dispersed, which is effective in reducing di/dt due to fluctuations in the inductance component and increasing the speed of the catechesis clock.

[Brief explanation of the drawing]

FIG. 1 and FIG. 2 are block diagrams each showing an embodiment of the present invention.

Claims (1)

[Claims] What is claimed is: 1. A data processing device comprising: clock drivers arranged at multiple locations inside a semiconductor chip; and wiring for wire-oring the outputs of the same clock drivers.