JPH02206202A - Combining and distribution circuit device for microwave multi-terminal - Google Patents

Abstract

PURPOSE:To provide electric isolation between input and output microwave lines by providing a distribution circuit in which gates of 2nd field effect transistors(TRs) are connected together and connected to a drain of 1st field effect TR. CONSTITUTION:Each signal inputted to input terminals T1-T3 via 1st-3rd input microwave lines 31-33 is amplified by FETs 41-43 and combined and the combined signal is amplified by FETs 51-53 and distributed. Then each distributed signal is outputted to 1st-3rd output microwave lines 61-63 via output terminals T4-T6. Since sources of the FETs 41-43 are isolated electrically by the irreversibility of the FETs 31-43, the electric isolation among the 1st-3rd input microwave lines 31-33 connecting to each source is attained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to a plurality of microwave lines (hereinafter, microwave lines are lines for transmitting signals with a frequency of approximately 1 GHz or more, Refers to coplanar lines such as railroad tracks or slot lines, microstrip lines, etc.

) The present invention relates to a microwave multi-terminal combining/distributing circuit device that performs power combining of signals inputted to a plurality of microwave lines, and then performs power combining of the signals input to a plurality of microwave lines.

[Prior Art] FIG. 6 is a circuit diagram of a conventional Wilkinson type power distribution/synthesis circuit.

In FIG. 6, impedance transformers lot to 104 of 1/4 wavelength are connected between the signal input terminal 100 and four signal output terminals 105 to 108, respectively, and the signal output terminals 105 to 10g port P,
Resistors R1 having the same resistance value are connected between them. Here, when the signal source impedance connected to the input terminal 100 is R1, and the load resistance connected to the output terminals 105 to 108 is RL, each characteristic impedance Z of the impedance transformers 101 to 104 is f.
By setting the input/output terminal to0.105
Impedance matching can be performed in 108 to 108. In addition, a resistance value R9 is set so that reflected waves generated when each load resistor connected to the output terminals 105 to 108 deviates from the predetermined value RL do not appear at other output terminals. Isolation is ensured.

In the Wilkinson-type distribution/combination circuit configured as described above, a signal input to the input terminal 100 is divided in power through the impedance transformers 101 to 104 each having a characteristic impedance of 2, and the power is divided to the respective output terminals 105 to 108. is output to. Therefore, the circuit operates as a distribution circuit.

In addition, the terminal 100 is placed above the output terminal, and each terminal 105 to 1
By using 08 as an input terminal, each signal is input to each input terminal 105 to 108, and the power of each signal is combined via impedance transformers 101 to 104, respectively, and outputted to an output terminal 100. Therefore, the circuit operates as a synthesis circuit.

FIG. 7 is a circuit diagram of a conventional branch line type power distribution/synthesis circuit.

In FIG. 7, four and eleven quarter-wavelength lines No. 14 to No. 17 are connected in a ring shape, and line No. 14 and line No. 15 are connected.
The connection point of line No. 14 and line No. 17 is connected to terminal Ill, the connection point of line No. 15 and line No. 16 is connected to terminal No. 12, and the connection point of line No. 14 and line No. 17 is connected to terminal No.
and the connection point of line No. 17 is connected to terminal No. 13. Here, the impedance of the load or signal source connected to the terminals 110 to 13 is set to 2. When the characteristic impedance of the 14th and 16th lines is 21, and the characteristic impedance of the 15th and 17th lines is 22, set each impedance so that each impedance satisfies z, -1 77G. By doing so, impedance matching can be performed at each of the tenth to thirteenth terminals.

In the branch-line type power distribution/synthesis circuit configured as described above, for example, when a signal is input to terminal tiO, the power is distributed to terminal 12 and terminal 13 with a phase difference of 90°, and the signal is output. and no signal is output to terminal ill. Also, for example, when a certain signal is input to terminal 12, and a signal delayed by 90 degrees than the signal input to terminal 12 is input to terminal 13, a signal obtained by power-combining the respective signals is output to terminal 13. 11, and no signal appears at terminal 10. Furthermore, for example, if a certain signal is
When a signal delayed by 90° than the signal input to terminal 13 is input to terminal 12, a signal in which the power of each signal is combined is output to terminal 10, and the signal input to terminal ill is input to terminal 12.
No signal appears. That is, in this circuit I,
Since a signal input to one terminal passes through two paths and is output to another terminal in the same phase or in opposite phase, electrical isolation can be obtained between the input lines and between the output lines.

FIG. 8 is a circuit diagram of a conventional distributed power distribution circuit.

This circuit consists of three common-source field effect transistors (hereinafter referred to as FETs), which have been reported in many studies in the field of microwave monolithic integrated circuits (hereinafter referred to as MMICs) in recent years. This circuit is a combination of distributed amplifiers A, , A, and, compared to the circuit described above, is characterized by the use of FETs as active elements.

In FIG. 8, one end of a series circuit formed by four inductors (or high impedance microwave lines) 129 to 132 connected in series is terminated via a resistor 141, and the other end of the series circuit is an input terminal 120. connected to. Also, the connection point P1 between the inductor 129 and the inductor 130
, a connection point P3 between the inductor 130 and the inductor 131,
and a connection point P between inductor 131 and inductor 132.

are the gates of FET123 and FET126, respectively.
124, 127 gates, and FETI 25.128
connected to each gate.

Further, one end of a series circuit formed by connecting four inductors (or high impedance microwave lines) 133 to 136 in series is terminated via a resistor 142, and the other end of the series circuit is connected to the output terminal 121. Ru. Further, a connection point P between the inductor 133 and the inductor 134, a connection point PI% between the inductor 134 and the inductor 135, and a connection point Pa between the inductor 135 and the inductor 136 are connected to the drains of the FETs 123 to 125, respectively.

Further, one end of a series circuit formed by connecting four inductors (or high impedance microwave lines) 137 to 140 in series is terminated via a resistor 143, and the other end of the series circuit is connected to the output terminal 122. be done. Also,
A connection point P8 between the inductor 137 and the inductor 138, a connection point Pus between the inductor 138 and the inductor 139, and a connection point P between the inductor 139 and the inductor 140. are connected to each source of FETs 126-128, respectively.

In the circuit configured as above, the input terminal 120
and the resistor 141, between the output terminal 121 and the resistor 142, and between the output terminal 122 and the resistor 143, respectively.
The parasitic capacitances 123 to 128 and the inductors 129 to 140 constitute an LC ladder circuit type low-pass filter similar to a distributed constant line. Here, each ladder circuit type low-pass filter is designed to match impedance at the input terminal 120 and output terminals 121 and 122.

Now, the parasitic capacitance between the gate and source and the parasitic capacitance between the drain and source of each of the above FETs 123 to 128 are expressed as C.
First, Cdl, the signal voltage input to the input terminal 1201 is delayed by the delay phase amount determined by the inductance value of each inductor and the above parasitic capacitance value C, and then the signal voltage input to the input terminal 1201 is - Applied between sources. These signal voltages are applied to each FET 123 to 12.
After being amplified by 8, it is output between the drain and source of each FET 123 to 128. These signal voltages have a phase relationship determined by the delay phase amount described above, and the inductor and parasitic capacitance Cdl on the output terminal 121 and 122 side
The LC ladder circuit type low-pass filter consisting of
After the output terminals 121 and 122 are corrected to have the same phase and the power is combined, the output terminals 121 and 12
The power is divided into two and output.

The number of FETs used in this power distribution circuit is generally 3 to 7 per distributed amplifier, and the operating frequency band of the circuit is several octaves or more. Note that isolation between the input and output lines is obtained by the irreversibility of the FET.

In addition, by switching the drains and gates of each FET 123 to 128 in FIG. 8 and connecting them, and making the terminals 121 and 122 the input terminals and the terminal 120 the output terminal, the circuit of FIG. 8 can be converted into a distributed power combining circuit. It can be used as

[Problems to be Solved by the Invention] In the conventional power combining/distributing circuits shown in FIGS. 6 and 7 described above, in order to realize impedance matching at input and output terminals and isolation between output terminals,
Since a wavelength line is essential, it is difficult to miniaturize the circuit, and due to the frequency dependence of 1/4 wavelength, the frequency band used is generally narrow. Furthermore, since each circuit is a reciprocal circuit, there is a problem in that isolation between the input terminal and the output terminal cannot be obtained.

The conventional power distribution circuit shown in FIG.
Even if the inductors and inductors were arranged closely, it was not easy to downsize the device to 2 mm square or less.

Furthermore, the branch-line type combining/distributing circuit shown in FIG. 7 and the distributed type dividing/combining circuit shown in FIG. In order to do this, it is necessary to combine a plurality of synthesis/distribution circuits, and as the number of terminals increases, there is a problem in that the area occupied by the circuits on the board increases significantly.

Also, in the Wilkinson-type distribution/combination circuit shown in Figure 6, if it is configured and integrated in a planar pattern using microstrip lines, etc., it is practical to reduce the number of input terminals or output terminals to two. This is a fishing boat, and when the circuit is made to have multiple terminals, there are problems similar to those described above.

The purpose of the present invention is to solve the above problems and provide microwave multi-terminal synthesis that can provide isolation between input and output terminals, easily increase the number of terminals, and significantly reduce the size compared to conventional methods. An object of the present invention is to provide a distribution circuit device.

[Means for Solving the Problems] A first invention of the present application is such that each source of a plurality of first field effect transistors whose gates are grounded is connected to a plurality of different input microwave lines, and 1st
a composite circuit in which the drains of field effect transistors are connected to each other, and each source of a plurality of second field effect transistors whose drains are connected to each other is connected to a plurality of different output microwave lines, and The present invention is characterized in that it includes a distribution circuit in which the gates of the two field effect transistors are connected to each other and connected to the drains of the six first field effect transistors.

Further, a second invention of the present application is characterized in that at least one of the output microwave lines is connected to at least one of the input microwave lines via a feedback circuit.

Furthermore, a third invention of the present application is characterized in that a gain adjustment resistor is connected between the drain of the six first field effect transistors and the gate of the six second field effect transistors and the ground. .

Furthermore, the fourth invention of the present application provides that the source of the six first field effect transistor and the source of the six second field effect transistor are connected to the source of the six first field effect transistor and the six second field effect transistor. It is characterized by connecting a voltage applying means for applying a bias voltage to turn each transistor on or off.

[Function] With the above configuration, in the first invention of the present application, each signal inputted via each of the input microwave lines is processed by the six first field effect transistors of the synthesis circuit. After being amplified, the power is combined, and the combined signal is input to the six second field effect transistors of the distribution circuit, where it is amplified, power distributed, and output to each of the output microwave lines.

Here, by setting each gate width of the six first field effect transistors so that the mutual conductance of the six first field effect transistors becomes the reciprocal of the characteristic impedance of each of the input microwave lines, Impedance matching with each input microwave line can be achieved. Furthermore, due to the irreversibility of the six first field effect transistors, signals are transmitted between the input microwave lines and from the drain of the six first field effect transistors to the input microwave lines. is not performed.

Similarly, by setting the gate width of the six second field effect transistors so that the mutual conductance of the six second field effect transistors is the reciprocal of the characteristic impedance of each of the output microwave lines, Impedance matching with the output microwave line can be achieved. Moreover, due to the irreversibility of each of the second field effect transistors, between the respective output microwave lines, and
No signal is transmitted from each of the output microwave lines to the gate of each of the second field effect transistors.

In this way, impedance matching with the input and output microwave lines and electrical isolation between the input and output microwave lines can be achieved.

Further, in the second invention of the present application, at least one of the output microwave lines is connected to at least one of the input microwave lines via a feedback circuit, thereby providing input/output in the circuit device. The frequency characteristics of the gain between microwave lines can be corrected. Therefore, the frequency characteristics can be adjusted to be flat up to a predetermined frequency, for example.

Furthermore, in the third invention of the present application, a gain adjustment resistor is connected between the drain of each of the first field effect transistors and the gate of each of the second field effect transistors and the ground, and the resistance of the resistor is By changing the resistance value, the gain between the input and output microwave lines in the circuit can be adjusted.

Furthermore, in the fourth invention of the present application, each of the above-mentioned first
By connecting the voltage applying means to the source of the field effect transistor and the source of each of the second field effect transistors, each of the first field effect transistor and the second field effect transistor are turned on or off. It can be turned off, and the transmission path of the signal input via the input microwave line and the signal output via the output microwave line can be arbitrarily set.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

First Embodiment FIG. 1 shows the first embodiment of the present invention, which uses a FET.
It is a circuit diagram of a microwave synthesis distribution circuit with 3 human outputs,
The circuit includes three gate-grounded FETs 41 to 43,
Three drain-grounded FETs 51 to 53 and resistance value R
It is composed of a gain adjustment resistor 70 having the following characteristics. It is assumed that each of the FETs 41 to 43 and 51 to 53 has mutual conductance g to gas.

As shown in FIG. 1, the first
The input microwave line 31 of is connected to the FE via the input terminal T.
A second input microwave line 32, which is connected to the source of FET T41 and has a characteristic impedance Z2, is connected to the source of FET 42 via the input terminal T2, and a third input microwave line 33, which has a characteristic impedance Z, is connected to the input It is connected to the source of the FET 43 via the terminal T. F
The drains of the ETs 41 to 43 are connected together and grounded via a resistor 70, and the drains of the FETs 51 to 53
connected to each gate. The source of the FET 51 is connected to the first output microwave line 61 having a characteristic impedance z4 via the output terminal T, and the source of the FET 52 is connected to the output terminal T.

is connected to a second output microwave line 62 having a characteristic impedance Z, through an output terminal T, and the source of the FET 53 has a characteristic impedance 2. It is connected to a third output microwave line 63 having a .

Now, assuming that each of the FETs 41 to 43 and 51 to 53 is a FET that can be described only by mutual conductance g to g+++s, the S parameter of the microwave synthesis/distribution circuit shown in FIG. 1 is as shown in the following equation. Note that the subscripts of the symbols of the input/output terminals T1 to T are given as subscripts of the S parameters.

1k-Or (j-1, 2, 3; -4, 5, 6) (2) (j-1.2.3; -4, 5, 6) (3) S,, -0, (
+≠m; II m-1, 2, 3° and 1. m-4
, 5, 6) (4) Here, Sll is the reflection coefficient at each terminal T, to T, Slk is the transfer coefficient from the output terminal T, to input terminal T1 to T, and SkI is the input terminal T1. 5 and 11 are transfer coefficients from input terminals TI to T1 and output terminals TI to T1.

In the circuit shown in Fig. 1, FET4 is
Setting each gate width from 1 to 43.51 to 53, g+alZal= 1 (i -1, 2,..., 6
) (5) The reflection coefficients S at each of the above input/output terminals TI to T are all zero.

In the circuit of FIG. 1, which is set so that the above equation (5) holds true, the input terminals T1 to T are connected to the input terminals T1 to T via the first to third input microwave lines 31 to 33.

Each signal input to each FET 41 to 43
The synthesized signal is amplified by and then synthesized, and the synthesized signal is
The signals are amplified and distributed by each of the FETs 51 to 53, and each of the distributed signals is transmitted to each output terminal T, T, T,
The first to third output microwave lines 61 to 6
3 is output.

The microwave synthesis/distribution circuit shown in FIG. 1, which is set as shown in equation (5) above, has the following effects.

(1) Input end reflection coefficient SII+S! t, S33, and the output end reflection coefficient "44+SS5+S@@" are all zero, so impedance matching can be achieved between the input/output lines 31 to 33, and 61 to 63 and the circuit.

(2) Reverse transfer coefficient S+h (j-1, 2, 3; k
-4, 5, 6) are zero, so the input terminal T.

It is possible to electrically isolate between the output terminals T4 to T10 and the output terminals T4 to T10.

<3) From input terminals TI to T, to output terminals T4 to T,
Since the transfer coefficient Sk, to the resistor 7 is expressed by equation (3),
By changing the zero resistance value R, the gain between the input and output of the circuit can be changed.

In addition, each source of FET41 to FET43 is
Since they are electrically isolated by the irreversibility of the input microwave lines 31 to 43, it is possible to electrically isolate the first to third input microwave lines 31 to 33 connected to each source.

Similarly, each source of FET51 to FET53 is
Since the first to third output microwave lines 61 to 63 are electrically isolated by irreversibility, the first to third output microwave lines 61 to 63 connected to each source can be electrically isolated.

Furthermore, the spacing between the input microwave lines 31 to 33 and the output microwave lines 61 to 63 does not require a length of 1/4 wavelength as in the conventional circuits of FIGS. 6 and 7 described above. Therefore, the microwave combining/distributing circuit constituted by the FETs 41 to 43, 51 to 53 and the resistor 70 can be significantly miniaturized compared to the conventional circuit described above.

Furthermore, the circuit shown in FIG. 1 does not require an inductor to connect each FET as in the conventional circuit shown in FIG. Since the configuration corresponds to the number of l to l, it is possible to significantly reduce the size compared to the circuit shown in FIG. 8, and the number of input terminals and output terminals can be easily increased.

Second Embodiment FIG. 2 is a circuit diagram of a microwave combining/distributing circuit according to a second embodiment of the present invention. It is characterized by having the following. In FIG. 2, the same parts as in FIG. 1 are given the same reference numerals.

The circuit of FIG. 2 is different from the circuit of the first embodiment shown in FIG. Connecting the series circuit of Cc, (2) Inductor L
and the connection point P1 of the capacitor Cc are connected to the bias terminal Tbl via the resistor 70 and grounded via the high frequency shorting capacitor C51; (3) the drains of the FETs 51 to 53 are connected to the bias terminal Tb2; In addition to connecting the high frequency short circuit capacitor Cb! and (4) FET51.
The connection point of each gate of 53 to 53 is connected to a bias setting resistor Rg.
and ground through FET41 to 43.51.
Each of the sources Rbl to R0 is connected to each resistor Rbl to R0.
This means that it was grounded through the ground.

In the microwave combining/distributing circuit configured as described above, by applying a predetermined DC bias voltage to the bias terminals "r, , T, .
Bias settings from 3.51 to 53 can be made.

Further, as in the first embodiment, by changing the resistance value R of the resistor 70, the input microwave lines 31 to 33 can be
It is possible to adjust the gain of the signals output from the output microwave lines 61 to 63. Furthermore, inductor L
By adjusting the inductance value of each FE74
1 to 43. suppresses the influence of parasitic capacitance of 51 to 53,
There is an advantage that the gain of the signal can be maintained at a predetermined level up to the high frequency range.

In the above second embodiment, each of the FETs 41 to 43.
Although each of the sources 51 to 53 is grounded via bias adjustment resistors Rb1 to R1, the present invention is not limited to this, and the DC voltage of each source may be controlled in place of the resistors Rbl to R1. By connecting the circuit and applying a DC voltage that turns on or off the FET corresponding to each source, each terminal T1 to T can be selectively enabled. That is, the transmission paths of signals input and output via the input terminals T to T and the output terminals T4 to T can be arbitrarily set.

Third Embodiment FIG. 3 is a circuit diagram of a microwave combining/distributing circuit according to a third embodiment of the present invention. FE of grounding
A feedback circuit F consisting of T44, a microwave line 34.64, and a feedback capacitor Cf, and a feedback circuit F with a grounded drain.
ET55, gate grounded FET45, microwave line 3
5, 65, and a feedback capacitor Cf, and a feedback circuit F consisting of a FET 56 with a common drain and a common gate FET.
It is characterized by providing a feedback circuit F consisting of an ET 46, a microwave line 36, 66, and a feedback capacitor Cf. In FIG. 3, the same parts as in FIG. 2 are given the same reference numerals. The above differences will be explained below.

In FIG. 3, each gate of FETs 51 to 53 is
Gate and source of ET54, microwave line 64, feedback capacitor Cf, 1 microwave line 34, and FE
FET41 to FET4 through the source and drain of T44
Connected to each drain of 3. In addition, FET51 to 5
Each gate of No. 3 is connected to the gate and source of the FET 55, the microwave line 65, the feedback capacitor Cf, the microwave line 35, and the source and drain of the FET 45.
It is connected to each drain of FETs 41 to 43.

Furthermore, each gate of FET51 to FET53 is connected to FET56.
It is connected to each drain of the FETs 41 to 43 via the gate and source of the FET 46, the microwave line 66, the feedback capacitor Cfi, the microwave line 36, and the source and drain of the FET 46.

In the microwave synthesis/distribution circuit of FIG. 3 configured as described above, since the feedback circuits Fl to F are provided,
A part of the signal on the output side can be fed back to the input side to easily correct the frequency characteristics of the gain deviation from a predetermined gain, thereby adjusting the gain in the operating frequency band of the microwave synthesis/distribution circuit. flattening can be easily achieved.

FIG. 4 is a frequency characteristic diagram showing the calculation results of the relative gain of the circuit of the third embodiment when the feedback capacitance Cf1 (i-1, 2, 3) of the feedback capacitor is changed. .

In FIG. 4, when the feedback capacitance Cf + is OpF, the frequency characteristic is that of the circuit of the first embodiment. When the feedback capacitance Cf is gradually increased to 0.15 pF,
As shown in FIG. 4, a substantially flat frequency characteristic can be obtained. Furthermore, when the feedback capacitance Cf is increased,
The gain of the circuit decreases in the high frequency region. Therefore,
By setting appropriate feedback circuits Fl to F3, the gain of the circuit can be flattened.

In the above third embodiment, the feedback capacitor Cf
, but the present invention is not limited to this, and a feedback circuit made of other types of passive elements or active elements may be used.

In the third embodiment described above, the number of input terminals, the number of output terminals, and the number of feedback circuits are the same, but they are not limited to this, and may be configured differently.

Fourth Embodiment FIG. 5(A) is a plan view of the MMIG of the fourth embodiment showing an example of a circuit pattern for the microwave synthesis/distribution circuit shown in FIG. (A) is a vertical cross-sectional view taken along the line AA', FIG. 5 (C) is a vertical cross-sectional view taken along the line B-B' in FIG. 5 (A), and FIG. (A) c
A vertical cross-sectional view along line -c', Fig. 5(E) is shown in Fig. 5(E).
It is a longitudinal cross-sectional view about the DD' line of A). Figure 5 (
In A) to (E), the same parts as in FIG. 2 are given the same reference numerals.

In FIG. 5(A), a Schottky gate type FET (hereinafter referred to as MESFET) 41 is located approximately in the center on the left side of the rectangular semi-insulating GaAs semiconductor substrate l.
An active layer 17 is formed by implanting impurity ions from the upper surface of the semiconductor substrate l into the upper surface where the active layer 17 is to be formed.

A gate 41g of the MESFET 41 is formed integrally with the conductors 2a and 2b at approximately the center of the operating layer 17. Here, the planar shape of the gate 41g is a longitudinal gate width w parallel to the vertical direction in FIG. 5(A), and a gate length g.

It has a rectangular shape. Furthermore, the drain 41d and the source 41s are spaced apart from the gate 41g by a predetermined distance, with the gate 41g in between, and the active layer 1
7 and conductors 20a respectively.

20b1 is formed integrally with the center conductor 3 of the human-powered coglenar line 31. Here, each of the source 41s and drain 41d has a rectangular planar shape, and the longitudinal side of the source 41s and drain 41d is parallel to the side of the gate 41g in the gate width W direction. A gate 41g is formed on the active layer 17 in the semiconductor substrate l by a known method as described above.

By the source 41s and drain 41d, the MESFE
It forms T41.

Furthermore, gates 4 each having a gate width W and a gate length g are provided on the active layers 17a and 17b on the lower side of the rotation in FIG. 5(A) of the MESFET 41, respectively.
2g, MES with source 42s and drain 42d
A MESFET 43 is formed which includes the FET 42, a gate 43g1, a source 43s, and a drain 43d having a gate width W and a gate length g3. Furthermore, MESFET
41.42.43 Figure 5 (A) upper right side of the operating layer 1
8. On 18a and 18b, similar to the MESFET 41, there are gates having gate width W and gate length g) 5
1g, MES with source 51s and drain 51d
MESFET 52 includes a FET 51, a gate 52g having a gate width W and a gate length g, a source 52s and a drain 52d, and a MESFET 53 including a gate 53g having a gate width W and a gate length g, a source 53s and a drain 53d. It is formed.

Ground conductors 2a and 2b are respectively placed on the semiconductor substrate l on both upper and lower sides of the MESFET 41 and conductor 3 in FIG. 5(A).
is separated from the conductor 3 by a predetermined distance Q1, and the source 4
Near 1s, a bridge conductor lOa is formed integrally with the gate 41g so as to surround the source 41s, and is further formed on the conductor 3 to connect the ground conductors 2a and 2b via the insulating layer 10ia. These ground conductors 2a, 2b
and the center conductor 3 constitute an input coplanar line 31.

In addition, ground conductors 2b are placed on the semiconductor substrate l on both the upper and lower sides of the MESFET 42 and the conductor 4 in FIG. 5(A).
, 2c are separated from the conductor 4 by a predetermined distance Q2 and surround the source 42s in the vicinity of the source 42s,
A bridge conductor lOb is formed integrally with the gate 42g and further connects the ground conductors 2b and 2c on the conductor 4 via the insulating layer 10ib. These ground conductors 2b
, 2C and the center conductor 4, the input coplanar line 3
2.

Furthermore, ground conductors 2 are placed on the semiconductor substrate l on both upper and lower sides of the MESFET 43 and the conductor 5 in FIG. 5(A).
c, 2d are at a predetermined distance l! from the conductor 5. , and is formed integrally with the gate 43g so as to surround the source 43s in the vicinity of the source 43s, and furthermore, the conductor 5
A bridge conductor 10c is formed thereon to connect the ground conductors 2c and 2d via an insulating layer 1O1C. These ground conductors 2 c +2 d and the center conductor 5 constitute an input coplanar line 33 .

Furthermore, grounding conductors 2g are provided on the semiconductor substrate l on both upper and lower sides of the conductor 8 in FIG. 5(A).

2f are formed apart from the conductor 8 by a predetermined distance a4, and furthermore, a bridge conductor 10d is formed on the conductor 8 to connect the ground conductors 2g and 2f via an insulating layer 10id. These ground conductors are 2g.

2f and the center conductor 8, the output coplanar line 61
It consists of

Further, ground conductors 2f and 2e are formed on the semiconductor substrate l on both upper and lower sides of the conductor 7 in FIG. A bridge conductor lOe is formed thereon to connect the ground conductors 2f and 2e via an insulating layer 10ie. These ground conductors 2f, 2e and the center conductor 7 constitute an output coplanar line 62.

Further, ground conductors 2e and 2db are formed on the semiconductor substrate l on both upper and lower sides of the conductor 6 in FIG. Ground conductors 2e, 2 are placed on top via an insulating layer 10if.
A bridge conductor 10f connecting db is formed. These ground conductors 2e.

2db and the center conductor 6, the output coplanar line 6
3.

The above-mentioned ground conductors 2d and 2db are further connected to the drain 41
It is formed integrally with the substantially rectangular ground conductor 2da located on the right side of the drains 51d, 52d, and 53d in the figure in FIG.

The substantially rectangular conductor 22 located on the left side of FIG. 5(A) of MESFE751.52.53 has drains 51d, 52d, 53d.

The conductor 22, the insulating layer 19a, and the ground conductor 2da form a known metal-insulator-metal capacitor (hereinafter referred to as MI
It is called an M capacitor. ) 15a, and this M
IM capacitor 15a is MESFET51.52.5
This is a high frequency grounding capacitor connected to each of the drains 51d, 52d, and 53d of No.3.

The conductor 20a is connected to the ground conductor 2 on the semiconductor substrate l on the upper side of the drain 41d of the MESFET 41 in FIG.
a* 2 d Drain 41 separated from a by a predetermined distance
A bridge conductor l is integrally formed with the conductor 2Oa and connects the ground conductors 2a and 2da via an insulating layer (not shown) on the conductor 2Oa.

g is formed. the conductor 20a and the ground conductor 2a.

2da constitutes a coplanar line. moreover,
The conductor 20a is connected to one end of a spiral-shaped conductor 21 formed on the semiconductor substrate 1 on the upper side of the ground conductor 2a in FIG.
is connected to one end of a bridge conductor 10m formed on a portion of the conductor 28 via an insulating layer (not shown), and the other end of the bridge conductor 10m is connected to one end of the conductor 28. here,
The spiral conductor 21 constitutes a first inductor (L).

Drain 41d of MESFET41 and MESFET42
A conductor 20 is placed on the semiconductor substrate 1 between the drain 42d of the
b is formed integrally with the drains 41d and 42d at a predetermined distance from the ground conductors 2b and 2da, and furthermore, the ground conductors 2b and 2da are formed on the conductor 20b via an insulating layer (not shown). A connecting bridge conductor lOi is formed. The conductor 20b and the ground conductors 2b and 2da constitute a coplanar line.

Drain 42d of MESFET42 and MESFET43
The conductor 20 is placed on the semiconductor substrate l between the drain 43d of the
c is formed integrally with the drains 42d and 43d at a predetermined distance from the ground conductor 2c+2da, and is further provided with an insulating layer (not shown) on the conductor 20c.
A bridge conductor 10h connecting the ground conductors 2c and 2da is formed. The conductor 20c and the ground conductors 2c and 2da constitute a coplanar line.

A conductor 25 is formed integrally with a conductor 26 formed on the semiconductor substrate l on the ground conductor 2g on the upper right side of the MESFET 51 in FIG. 5(A) via an insulating layer 19b.

Here, the conductor 25, the insulating layer 19b, and the ground conductor 2
g constitutes a high frequency short circuit MIM capacitor 15b, which together with the above-mentioned MIM capacitor 15a becomes the high frequency short circuit capacitor Cbl in FIG.

The conductor 23a is connected to the ground conductor 2da on the upper semiconductor substrate l in FIG. 5A of the gate 51g of the MESFE751.
, 2g and integrally formed with the gate 51g at a predetermined interval, and further connects the conductor 22.25 on the conductor 23a via the insulating layer 10ij.
is formed.

The conductor 23a and the ground conductors 2da and 2g constitute a coplanar line. Further, the conductor 23a is formed integrally with the conductor 23d1 and the conductor 24 formed on the semiconductor substrate l.

A conductor 23b is placed on the semiconductor substrate l between the gate 51g of the MESFET 51 and the drain 52g of the MESFET 52.
are formed integrally with the gates 51g, 52g apart from the ground conductors 2da, 2f by a predetermined distance, and
A ground conductor 2d is placed on the ground conductor 3b via an insulating layer (not shown).
A bridge conductor 10M connecting a and 2f is formed.

The conductor 23b and the ground conductors 2da and 2f constitute a coplanar line.

MESFET52 gate 52g and MESFET52
A conductor 23c is formed integrally with the gates 52g, 53g at a predetermined distance from the ground conductors 2da, 2e on the semiconductor substrate 1 between the drain 53g of the conductor 23c, and an insulating layer ( (not shown), a bridge conductor 10k is formed to connect the ground conductors 2da and 2e. The conductor 23c and the ground conductors 2da and 2e constitute a coplanar line.

A rectangular conductor 27 is formed integrally with the conductor 28 on the semiconductor substrate l on the upper side of the conductor 23a in FIG. .

), and the conductor 27, the insulating layer, and the conductor 24 constitute the coupling MIM capacitor 12 (Cc).

A conductor 29 is formed on the semiconductor substrate l with an insulating layer (not shown) interposed on the conductor 2g, respectively.
16. Here, the conductor 29, the insulating layer, and the conductor 2g constitute the entire high frequency short circuit MIM capacitor 14 (cb+).

Impurity ions are implanted in advance into the semiconductor substrate l between the conductor 23d and the upper end 2dac of the ground conductor 2da in FIG. 13c(Rg) is formed.

Further, impurity ions are implanted in advance into the semiconductor substrate l between the conductor 28 and the conductor 9, so that the conductor 28.9
A resistor 13 (R) is formed to connect the two. Further, impurity ions are implanted in advance into the semiconductor substrate l between the conductors 26 and 16, thereby forming a resistor 13b connecting the conductors 16 and 26. Here, the conductor 16 constitutes the bias terminal Tkl, and the conductor 26 constitutes the bias terminal T1.
However, in this embodiment, the conductor 16.2
6 is connected through a resistor 13b, the bias terminals T, . . . , TI are combined into one. By setting the resistance value of the resistor 13b to the same value as the resistance value R of the resistor 13, the same bias voltage can be applied between the drains and sources of all the MESFETs 41 to 43 and 51 to 53.

With the above configuration, each of the drains 41d to 43d of the MESFETs 41 to 43 is connected to the conductor 20, the inductor 1. Bridge conductor 10m.

It is connected to the grounding conductor 2g via the conductor 28, the resistor 13 and the MIM capacitor 14, and is grounded at high frequency.
Each gate 51g to 53g of MESFET 51 to 53
is connected to the ground conductor 2da and grounded via the conductors 23a, 23d and the resistor 13c. Furthermore, MESFE
Each drain 51d to 53d of T51 to 53 is MIM
They are connected to ground conductors 2da and 2g via capacitors 15a and 15b, respectively, and are grounded at a high frequency.

The microwave combining/distributing circuit configured as described above has the same effects and operations as the circuit of the second embodiment shown in FIG. Further, according to experiments conducted by the present inventor, it has been confirmed that the circuit can be realized with a size of about 1 mm square, and that the microwave synthesis/distribution circuit can be significantly miniaturized compared to the conventional one.

In the fourth embodiment described above, the MESFETs 41 to 43, and 51 to 53 are arranged close to each other and connected via lumped constant circuits, but the present invention is not limited to this, and the MESFETs 41 to 43, and 51 to 53 are connected via lumped constant circuits. The connection may be made via a microwave line.

In the fourth embodiment described above, a coplanar line is used as the input/output line, but the present invention is not limited to this, and other types of microwave lines such as a microstrip line or a slot line may be used.

Other Embodiments In each of the above embodiments, a three-man power, three-output microwave synthesis/distribution circuit is described, but the invention is not limited to this.
A circuit with two or more human power outputs, four or more human power outputs, or four or more outputs may be configured. Furthermore, in the above embodiments, the number of input terminals and the number of output terminals are the same, but
The present invention is not limited to this, and a single-manpower multi-output or multi-input/l-output circuit may be configured.

In the first to third embodiments described above, the resistor 70 is provided, but the present invention is not limited to this, and the resistor 70 may not be provided.

[Effects of the Invention] As detailed above, according to the first invention of the present application, each source of a plurality of first field effect transistors whose gates are grounded is connected to input microwave lines on different sides. and a composite circuit in which the drains of the first field effect transistors are connected to each other, and the sources of the plurality of second field effect transistors whose drains are connected to each other are respectively connected to different output microwave lines. In addition, since the distribution circuit is provided in which the gates of the second field effect transistors are connected to each other and the drains of the first field effect transistors, impedance matching with the input and output microwave lines, It is also possible to realize a microwave multi-terminal synthesis/distribution circuit having electrical isolation between input and output microwave lines. Further, unlike the conventional circuits shown in FIGS. 6 and 7, a 1/4 wavelength line is not required, so that the circuit can be significantly miniaturized compared to the conventional circuits, and wideband operation can be realized.

Furthermore, like the conventional distributed distribution/synthesis circuit shown in Fig. 8,
Many inductors, one input or one output, and several FEs
Since no T is required, the plate can be made even smaller. Furthermore, in order to increase the number of inputs or outputs,
Since it is only necessary to add the first field effect transistor or the second field effect transistor by the number of inputs and outputs, it is possible to easily increase the number of terminals without changing the circuit dimensions.

Further, according to the second invention of the present application, at least one of the output microwave lines is connected to at least one of the input microwave lines via a feedback circuit, so that the input microwave line in the circuit device is connected to the input microwave line. It is possible to correct the frequency characteristics of the gain between the output microwave lines. Therefore, the frequency characteristics can be adjusted to be flat up to a predetermined frequency, for example.

Furthermore, according to the third invention of the present application, a gain adjustment resistor is connected between the drain of each of the first field effect transistors and the gate of each of the second field effect transistors and the ground, and the resistor is connected to the ground. By changing the resistance value of
The gain between the input and output microwave lines in the circuit can be adjusted.

Furthermore, according to the fourth invention of the present application, by connecting the voltage applying means to the source of each of the first field effect transistors and the source of each of the second field effect transistors, and each of the second field effect transistors can be turned on or off, respectively, and a signal input via the input microwave line and a signal output via the output microwave line. The transmission route can be set arbitrarily.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a microwave combining/distributing circuit according to a first embodiment of the present invention, FIG. 2 is a circuit diagram of a microwave combining/distributing circuit according to a second embodiment of the present invention, and FIG. 3 is a circuit diagram of a microwave combining/distributing circuit according to a second embodiment of the present invention. A circuit diagram of a microwave synthesis/distribution circuit according to a third embodiment of the present invention. FIG. 4 is a diagram showing the relative gain frequency characteristics of the circuit of FIG. 3. FIG. 5(A) is a circuit diagram of the circuit of FIG. 2. A plan view of an MMIC showing an example of a circuit pattern of Nodame, FIG. 5(B) is a vertical cross-sectional view taken along line A-A' in FIG. 5(A), and FIG. 5(C) is a vertical cross-sectional view of FIG. 5(A). Figure 5 (D) is a vertical cross-sectional view taken along line C-C'' of Figure 5 (A), Figure 5 (E) is Figure 5 (A). Figure 6 is a circuit diagram of a conventional Wilkinson type distribution/combination circuit, Figure 7 is a circuit diagram of a conventional branch line type distribution/combination circuit, and Figure M8 is a conventional distribution type circuit. It is a circuit diagram of a distribution circuit. 31.32.33... Input microwave line, 41.4
2.43...FET with gate grounded. 51.52.53...FET with drain grounded. 61.62.63... Output microwave line, 70...
・Gain adjustment resistor, Rml to Rh, ... bias setting resistor, Fl, F
,,F,...Feedback circuit, Cfl, Cft, Cfs...Feedback capacitor. Patent Applicant: A.T.R. Optical Radio Communication Research Institute Co., Ltd. Agent: Patent Attorney: 1 person, Aohaku, and 1 person (Fig. 1, Fig. 3, Fig. 2, Fig. 4, Fig. 5, CB) District 5 (C)

Claims (4)

[Claims] (1) The sources of the plurality of first field effect transistors with gates common are each connected to a plurality of different input microwave lines, and the drains of the first field effect transistors are connected to each other. The synthesis circuit and the sources of the plurality of second field effect transistors having common drains are connected to different output microwave lines, and the gates of the second field effect transistors are connected to each other. A microwave multi-terminal synthesis distribution circuit device comprising a distribution circuit connected to the drains of each of the first field effect transistors. (2) The microwave multi-terminal synthesis and distribution circuit device according to claim 1, wherein at least one of the output microwave lines is connected to at least one of the input microwave lines via a feedback circuit. . (3) A gain adjusting resistor is connected between the drain of each of the first field effect transistors and the gate of each of the second field effect transistors and the ground. Terminal synthesis distribution circuit device. (4) turning on or off each of the first field effect transistors and the second field effect transistors at the source of each of the first field effect transistors and the source of each of the second field effect transistors; 2. The microwave multi-terminal synthesis/distribution circuit device according to claim 1, further comprising voltage application means for applying a bias voltage for the multi-terminal multi-terminal synthesis/distribution circuit.