JPH02206831A - Full adder circuit - Google Patents

Abstract

PURPOSE:To realize a full adder circuit which can operate at a higher speed by detecting the current difference or the voltage difference of a complementary output signal and outputting the signal of an addition result in sense amplifier circuits. CONSTITUTION:The XOR signal and the XNOR signal of input signals are outputted in a first and second logical circuits 21 and 22. A first level assurance circuit 31 assures the levels of the signals outputted from the circuit 21 to a power potential or an earth potential and gives them to the circuit 22. A second level assurance circuit 32 assures the levels of the signals outputted from the circuit 22 to the power potential or the earth potential and gives them to the input of the first sense amplifier circuit 41. Transmission gate circuits 51 and 52 cause the input signals to pass or interrupt them in accordance with the levels of the output signals of the circuit 21. A carry signal deletion circuit 61 controls the level of a carry input signal which the circuit 51 has caused to pass. A carry signal generation circuit 62 controls the level of the complementary signal of the carry input signal which the circuit 52 has caused to pass in accordance with the level of the signal A or B. The second sense amplifier circuit 42 outputs a carry output signal CO and the complementary signal, the inverse of CO from output terminals Y and the inverse of Y.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a full adder circuit that operates at high speed.

[Conventional technology]

Figure 8 shows an example of the configuration of a conventional full adder circuit.
This invention was announced at the ``Study of differential operation type full adder with level guarantee circuit'' held at the 2011 National Conference of the Institute of Electronics and Communication Engineers, and was also disclosed in Japanese Patent Application Laid-open No. 124133/1983.

In FIG. 8, power supply potential ■. is set to logic "1", and ground potential GMD is set to logic "0".

In the figure, numerals 1 to 6 are signal input terminals; the terminal 1 receives the summand signal A, and the terminal 2 receives the complementary signal W of the summand signal A.

An addend signal B is input to the terminal 3, and a signal complementary to the addend signal B is input to the terminal 4.

A carry input signal Cin is input to the terminal 5, and a - signal complementary to the carry input signal Cin is input to the terminal 6.

21 and 22 are first and second logic circuits that generate and output exclusive OR (XOR) signals and negative exclusive OR (XNOR) signals of input signals. First logic circuit 2
The input signal to 1 is the above terminal! , 2. Addend signal pair A, X and addend signal pair B input from 3 and 4 respectively,
π, and the output signal is the XNO output to the signal line 201.
This is the R signal and the XOR signal output to the signal line 202. In addition, the input signals to the second logic circuit 22 are the XNOR signal and the X0II signal, which are output signals from the first logic circuit 21 to the signal lines 201 and 202, and the carry input input from terminals 5 and 6, respectively. Signal vs. Cin.

τn, and the output signal is XO output to the signal line 203.
These are the R signal and the XNOR signal output to the signal line 204.

31, 32 and 33 are level guarantee circuits. The first level guarantee circuit 31 connects the first logic circuit 21 to the signal line 20.
1, 202, the XNOR, The levels of the XNOR and XOR signals output to the lines 201 and 202 are guaranteed to be the power supply potential VCC or the ground potential GNI, and are applied to a first inverting amplifier circuit 81 and a second inverting amplifier circuit 82, which will be described later.

51 and 52 are transmission gate circuits. The first transmission gate circuit 51 receives a carry input signal C input from the terminal 5.
in is the re-output signal of the first logic circuit 21, that is, XNOR
It is passed or blocked depending on the level of the signal and the X0II signal. The second transmission gate circuit 52 passes or blocks the signal sn input from the terminal 6 depending on the level of the re-output signal of the first logic circuit 21, that is, the XNOR signal and the XOI+ signal.

Reference numeral 61 denotes a carry signal cancellation circuit, which g controls the level of the carry input signal Cin passed by the first transmission gate circuit 51.
Control is performed according to the level of the signal τ or ■.

A carry signal generation circuit 62 controls the level of the carry input signal Cin according to the level of the signal A or B with a signal complementary to the carry input signal Cin passed by the second transmission gate circuit 52.

The carry signal deletion circuit 61 and the carry signal generation circuit 6
The output signal No. 2 is set to the power supply potential VCC or the ground potential G by the third level guarantee circuit 33 described above. The signal is supplied to the third inverting amplifier circuit 83 and the fourth inverting amplifier circuit 84 with a guarantee of .

Here, the level guarantee circuits 31, 32 and 33 will be explained. As shown in FIG. 8, the level guarantee circuit 31 (32, 33) is composed of two PMO5 type transistors, whose sources are both connected to the power supply potential VCC, and whose drains are both connected to external terminals. , the gate is interconnected to the drain of the other.

The operation of such a level guarantee circuit 3N32, 33) is as follows (where the potential of one terminal is the ground potential G, 1.
, the transistor whose gate is connected to that terminal turns on, and the power supply potential VCe appears at the other terminal. At this time, the transistor whose gate is connected to the terminal where the power supply potential VCC appears turns off. That is, if one of the two terminals becomes the ground potential GN6, the other always becomes the power supply potential VCC.

If such level guarantee circuits 31, 32 and 33 are not added to the logic circuits 21, 22, etc., for example, since the first logic circuit 21 is composed of NMO5 type transistors, ■? If Δ is the dark value potential and 2 is the source input potential, the drain potential only reaches v−v7Il<VcC.

If a signal lower than the power supply potential VCC is applied to the transistor, a current may flow directly from the power supply potential VCC to the ground potential G0, resulting in an increase in power consumption or a decrease in margin against noise. In order to avoid such a situation, level guarantee circuits 3032, 33) are added.

The entire operation of the conventional full adder circuit shown in FIG. 8 is as follows.

Addend signal A and its complementary signal τ are input to terminals 1 and 2, respectively, and addend signal B is input to terminals 3 and 4, respectively.
and its complementary signal π are input.

By inputting the addend signal pair ^, λ and the addend signal pair B, U to the first logic circuit 21, the XNOR signal and the Signal from the logic circuit 21! 201 and 202, and the respective levels are guaranteed by the first level guarantee circuit 31.

The XNOR signal and the XOR signal output from the first logic circuit 21 to the signal lines 201 and 202, the carry input signal Cin input to the terminals 5 and 6, and its complementary signal τi are transmitted to the second logic circuit. 22, XNO
The R signal and the X0II signal are respectively sent to the second logic circuit 22.
The signals g203 and g204 are outputted from the signal g203 and g204, and the respective levels are guaranteed by the second level guarantee circuit 32.

XNOR signal and X output to signal lines 203 and 204
The OR signal is given to a first inverting amplifier circuit 81 and a second inverting amplifier circuit 82, respectively, and the first inverting amplifier circuit 81
The output signal of the second inverting amplifier circuit 82 is outputted as a sum signal S from the terminal 7, and the output signal of the second inverting amplifier circuit 82 is outputted as a signal complementary to the sum signal S from the terminal 8.

Carry input signal Cin input to terminals 5 and 6, respectively
and its complementary signal - are the XNOR signal and XO output from the first logic circuit 21 to the signal vA201.202.
First transmission gate circuit 51 whose opening/closing is controlled by the R signal
and is also input to the second transmission gate circuit 52. Note that the transmission gate circuits 51 and 52 are both controlled to open and close by the same signal, so they open and close at the same time.

According to the opening/closing of the transmission gate circuit 5152, the carry input signal Cin and its complementary signal n remains as the signal &I.
2O3 and 206, or is blocked.

When the carry input signal Cin and its complementary signal Tn are cut off by the transmission gate circuits 51 and 52, the carry signal cancellation circuit 61 or the carry signal generation circuit 62 outputs the summand signal pair A, A signal is generated by X and the addend signal pair BJ. Signal &11205 and signal &*206
Since the third level guarantee circuit 33, the third inverting amplifier circuit 83, and the fourth inverting amplifier circuit 84 are connected to guarantee the logical value "1" or "0", the third inverting amplifier circuit The output signal 83 is output as a carry output signal CO from the terminal 9, and the output No. 18 of the fourth inverting amplifier circuit 84 is output from the terminal 10 as a complementary signal 2 of the carry output signal CO.

In FIG. 9 (al, (b), Tel and fdl are the signal lines 203 in the conventional full adder circuit configured as described above.
and 204, and a schematic diagram showing waveforms of sum signals S and T.

In FIG. 9(a), fbl, (C1 and fd), VCC is the power supply potential, O is the ground potential, VTI, VTI(
A) and VTI (B) indicate the dark potentials of the inverting amplifier circuits 81 to 84.

First, as shown in FIG. 9 (al), it is assumed that the signal line 203 is at the power supply potential VCC and the signal line 204 is at the ground potential GNo. The signal lines 203 and 204 start changing at time LO. The case where the dark potential of the inverting amplifier shown in FIG. 9 (bl) is V□(A) will be explained.

At time t5, the level of the sum signal S begins to change when the level of the signal vA203 exceeds the dark potential Vt+(A) of the inverting amplifier, and at time t6 the level of the signal line 204 reaches the dark potential VTl of the inverting amplifier. From the point in time when (A) is exceeded, the level of the complementary signal line of the sum signal S begins to change.

When the threshold potential vy+ of the inverting amplifier as shown in FIG. 9 (C1) is vcc/2, the following is true.

At time t4, when the levels of the signal lines 203 and 204 exceed the threshold potential of the inverting amplifier, both the level of the sum signal S and the level of its complementary signal 10 begin to change simultaneously.

The threshold potential of the inverting amplifier shown in FIG. 9 +dl is Va, (B
), the result is as follows.

At time t1, the level of the signal line 204 exceeds the dark potential Vr+(B) of the inverting amplifier, and the level of the complementary signal τ of the sum signal S begins to change, and at time t3, the level of the signal line 203 is inverted. The sum signal S begins to change when it exceeds the dark value potential V□(B) of the amplifier.

[Problem to be solved by the invention]

In the conventional full adder circuit as described above, the case where, for example, the potentials of the complementary sum signal pair S and T at terminals 7 and 8 change will be considered below.

Since the threshold potential of the inverting amplifiers 81 to 84 is vy+,
Is the potential of the signal [203, 204 V? The potential at the terminal 7.8 does not change until the inverting amplifiers 81 and 82 operate beyond l. Assuming that it is now V□" V cc/2,
As shown in FIG. 9 (el), changes in the potentials of the terminals 7.8 occur simultaneously.In reality, it is difficult to control the threshold potentials of the inverting amplifiers 81 to 84 to Vcc/2, and process fluctuations Accordingly, it becomes Vcc/2±α.

As shown in Figure 9 (al), the dark potential of the inverting amplifier is Vr
When changing between r(A) and Va,(B), the operation of the inverting amplifiers 81 to 84 is changed to the ninth
) + (cl, (dl) respectively. The signal I begins to change after a delay of L6-t4.Therefore, there is a problem that the operating speed is slower than in an ideal state.

The present invention was made in view of these circumstances, and
The present invention aims to provide a full adder circuit that can operate at higher speed by eliminating the influence of threshold fluctuations of circuit elements.

(Means for Solving Problem i1) The full adder circuit of the present invention uses a sense amplifier instead of the conventional configuration in which the final complementary sum signal pair and complementary carry output signal pair are obtained using an inverting amplifier. In addition, in order to obtain clock synchronization, a structure that can be controlled by an equalization signal synchronized with the clock is also adopted.

[Effect]

In the full adder circuit of the present invention, a sense amplifier circuit detects a current difference or a voltage difference between complementary output signals and outputs a signal representing the addition result. Further, by synchronizing the equalize signal with the clock, synchronization with other circuits can be obtained.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof.

FIG. 1 is a circuit diagram showing a configuration example of a first embodiment of a full adder circuit according to the present invention. Note that the same reference numerals are given to the same or corresponding parts as in the conventional example shown in FIG. 8 described above.

In FIG. 1, the power supply potential VCC is set to logic "1°", and the ground potential G0 is set to logic "O".

In the figure, 1 to 6 are signal input terminals, terminal 1 receives the summand signal A, and terminal 2 receives the complementary signal X of the summand signal A, respectively.

Terminal 3 receives an addend signal B, and terminal 4 receives a signal complementary to the addend signal B.

A carry input signal Cin is input to the terminal 5, and a signal complementary to the carry input signal C3n is input to the terminal 6.

21 and 22 are first and second logic circuits that generate and output an exclusive OR (XOR) signal and negative exclusive OR (χNOI+) 18 of input signals. The input signals to the first logic circuit 21 are the addend signal pairs A and T and the addend signal pair B input from the above-mentioned terminals 1.2.3 and 4, respectively.
, U, and the output signal is XN output to the signal line 201.
These are the OR signal and the XOR signal output to signal &*202. The input signals to the second logic circuit 22 are the XNOR signal and the XOR signal which are the output signals from the first logic circuit 21 to signals *201 and 202, and the carry input input from terminals 5 and 6, respectively. Signal vs. Cin.

and the output signal is XO output to the signal line 203.
This is the R signal and the XN0II signal output to the signal line 204.

31, 32 and 33 are level guarantee circuits. The first level guarantee circuit 31 connects the first logic circuit 21 to the signal line 20.
1, 202 is guaranteed to be the power supply potential VCC or ground potential G11m, and the second
to the logic circuit 22, and also to the second level guarantee circuit 32.
The level of the XNOR and XOR signals output from the second logic circuit 22 to the signal lines 201 and 202 is the power supply potential ■. Alternatively, it is guaranteed to be at the ground potential GND and is applied to input terminals T'& and (2) of a first sense amplifier circuit 41, which will be described later. In addition,
Output terminals Y and Y of the first sense amplifier circuit 41 are connected to terminals 7 and 8, respectively.

51 and 52 are transmission gate circuits. The first transmission gate circuit 51 receives a carry input signal C input from the terminal 5.
in is the re-output signal of the first logic circuit 21, that is, XNOR
It is passed or blocked depending on the level of the signal and the XOR signal. The second transmission gate circuit 52 passes or blocks the signal τi input from the terminal 6 depending on the level of the re-output signal of the first logic circuit 21, that is, the XNOR signal and the XOR signal.

Reference numeral 61 denotes a carry signal erasure circuit, which controls the level of the carry input signal Cin passed by the first transmission gate circuit 51 according to the level of the signal X or ■.

A carry signal generation circuit 62 controls the level of a complementary signal lever of the carry input signal Cin passed by the second transmission gate circuit 52 in accordance with the level of the signal A or B.

The carry signal deletion circuit 61 and the carry signal generation circuit 6
The output signal of 2 is guaranteed to be the power supply potential V (or ground potential G) by the third level guarantee circuit 33 described above and is applied to the input terminals T and 1 of the first sense amplifier circuit 41. Output terminals Y and Y of the sense amplifier circuit 42
are connected to terminals 9 and 1o, respectively.

Here, the level guarantee circuits 31, 32 and 33 will be explained. As shown in FIG. 1, the level guarantee circuit 3H32, 33) is composed of two PMO5 type transistors, whose sources are both connected to the voltage a potential VCC, and whose drains are both connected to external terminals. , the gate is interconnected to the drain of the other.

The operation of such level guarantee circuit 3N32, 33) is as follows. When the potential of one terminal changes to the ground potential GND, the transistor whose gate is connected to that terminal turns on, and the power supply potential VCC appears at the other terminal. At this time, the transistor whose gate is connected to the terminal where the power supply potential VCC appears turns off. That is, if one of the two terminals becomes the ground potential GNIl, the other always becomes the power supply potential VCC.

When such level guarantee circuits 31, 32 and 33 are not added to the logic circuits 21, 22, etc., for example, since the first logic circuit 21 is composed of NMO5 type transistors, vvg is its threshold potential, and ■ is Given the source input potential, the drain potential only reaches v - vt, < vCC.

If a signal lower than the power supply potential VCC is applied to the transistor, a current may flow directly from the voltage level VCC to the ground potential GN11, resulting in an increase in power consumption or a decrease in margin against noise. To avoid such a situation, level guarantee circuit 3N32.33)
is added.

Here, the sense amplifier circuits 41 and 42 will be explained.

FIG. 2 is a circuit diagram showing the configuration of the sense amplifier circuit 41 (42).

In FIG. 2, Q31. Both Q32 are PrIO3 type transistors, and Q33. Q34 is NMO5 type O
5 indista. The sources of PMO5 type transistors Q31 and Q32 are both connected to the power supply potential VCC, and the PM
The gates of O5 type transistors Q31 and Q32 are both P
It is connected to the drain of the MO5 type transistor Q31, the output terminal Y, and the drain of the NMO5 type transistor Q33. Further, the drain of the PMOS type transistor Q32 is connected to the output terminal Y and the drain of the NFlO5 type transistor Q34, and the sources of the NMO3 type transistors Q33 and Q34 are both connected to the ground potential GND. and NFIO5 type transistors Q33 and Q34
The gates of are connected to input terminals I and T, respectively.

The operation of such a sense amplifier circuit 4H42) will be explained with reference to the waveform diagram of FIG. In addition, FIG. 3(a) shows the levels of the signals 1203 and 204, bl (bl is the output signal of the first sense amplifier circuit 41, that is, the level of the sum signal pair S,3, and tc+ is the level of the above-mentioned conventional signal The levels of the sum signal pair S and S of the full adder circuit are shown, respectively.

It is also assumed that the dark value potential of the inverting amplifier used in the conventional full adder circuit is VT+, and that the level of the signal v1203 is initially at the power supply potential VCC and the level of the signal line 204 is at the ground potential G0.

Signal lines 203 and 204 start changing at time to. At time [2], when the potential difference between the input signal pair, that is, the potential difference between the signals 1203 and 204 becomes ΔV, the sense amplifier circuit operates, and the sum signal pair S and T change simultaneously, as shown in FIG. 3 (bl). do.

In the conventional full adder circuit, the third vIJ (as shown in Cl,
At time t1, when the level of the signal line 204 exceeds the threshold potential vy+ of the inverting amplifier, the level of the complementary signal of the sum signal S starts to change, and at time t3, the level of the signal line 204 exceeds the threshold potential vy+ of the inverting amplifier.
The level of the sum signal S begins to change at the point in time when the change in the level of the sum signal S exceeds the dark value potential Va of the inverting amplifier.

In this case, the level of the complementary signal S of the sum signal S of the conventional full adder circuit starts to change at an earlier time, t2, compared to the complementary signal S of the sum signal S of the full adder circuit of the present invention. . However, the level change of the sum signal S of the conventional full adder circuit starts to change at time t3, which is later than the time t2 when the sum signal pair S of the full adder circuit of the present invention starts to change in level. That is, in the conventional full adder circuit, the level of the sum signal pair S does not change until the level change of the signals 203 and 204 exceeds the threshold potential of the inverting amplifier, and as a result, the full adder circuit of the present invention is slower than the level change of the sum signal pair.

The overall operation of the full adder circuit of the present invention shown in FIG. 1 is as follows.

The summand signal A and its complementary signal X are input to terminals 1 and 2, respectively, and the addend signal B is input to terminals 3 and 4, respectively.
and its complementary signal ■ are input.

By inputting the addend signal pair A, λ and the addend signal pair B, ■ to the first logic circuit 21, the XN0II signal and the XOR signal of the addend signal A and the addend signal B are respectively
is output from the logic circuit 21 to the signal lines 201 and 202,
Each level is guaranteed by the first level guarantee circuit 31.

The XNOR signal and the XOR signal output from the first logic circuit 21 to the signal lines 201 and 202, the carry input signal Cin input to the terminal 5.6, and its complementary signal τn are connected to the second logic circuit. 22, XNO
The R signal and the XOR signal are each output from the second logic circuit 22 to the signal vA203.204, and the second level guarantee circuit 32 guarantees their respective levels.

XNOR signal and X output to signal 1203.204
The OR signals are applied to input terminals T and l of the first sense amplifier circuit 41, respectively. First sense amplifier circuit 4
The sum signal S is sent from the output terminal Y of 1 to the terminal 7, and the sum signal S is sent to the output terminal Y.
, complementary signals of the sum signal S are output to terminals 8, respectively.

Carry human power signal Cin input to terminals 5 and 6 respectively
and its complementary signal "σπ" are connected to the first transmission gate circuit 51 and the second transmission gate circuit whose opening and closing are controlled by the XNoRli signal and the XOR signal output from the first logic circuit 21 to the signal lines 201 and 202. The transmission gate circuits 51 and 52 are both controlled to open and close by the same signal, so they open and close at the same time.

According to the opening/closing of the transmission gate circuits 51, 52, the carry input signal Cin and its complementary signal are directly output to the signal lines 205 and 206, or are cut off.

When the carry input signal Cin and its complementary fs signal are blocked by the transmission gate circuits 51 and 52, the carry signal cancellation circuit 61 or the carry signal generation circuit 62 outputs the summand signal pair A, A signal is generated by W and the addend signal pair BJ. The signal line 205 and the signal line 206 are connected to a third level guarantee circuit 33 that guarantees a logical value of “1” and a second
A sense amplifier circuit 42 is connected thereto. signal g2
The output signal to the signal line 206 is input to the input terminal (2) of the second sense amplifier circuit 42, and the output signal to the signal line 206 is input to the input terminal T of the second sense amplifier circuit 42.

From the output terminal Y of the second sense amplifier circuit 42, a signal (2) complementary to the carry output signal CO is outputted to the terminal 9, and from the output terminal Y, the carry output signal CO is outputted to the terminal 10.

Next, regarding the second embodiment of the full adder circuit according to the present invention,
This will be explained with reference to the circuit diagram of FIG. 4 showing an example of its configuration. Note that the same reference numerals are given to the same or corresponding parts as the configuration of the first embodiment shown in FIG. 1 described above.

The second embodiment whose circuit configuration is shown in FIG. 4 differs from the first embodiment whose circuit structure is shown in FIG. The equalize signal ■ is transmitted to the carry signal erasure circuit 611, the carry signal generation circuit 62, and the first sense amplifier circuit 41. Second
The gate carry signal generation circuit 62 of the equalize transistor Q53 is provided to the sense amplifier circuit 42 and is further provided between the second logic circuit 22 and the second level guarantee circuit 32 and in the carry signal deletion circuit 61. Equalize transistors Q51 and C52 are interposed between the gate of equalize transistor Q54 provided in the third level guarantee circuit 33 and the third level guarantee circuit 33, respectively, and are connected to the gates thereof.

FIG. 5 is a circuit diagram showing the circuit configuration of the sense amplifier circuits 41 and 42 with enable used in this second embodiment.

Sense amplifier circuit 41 with enable shown in FIG.
．． 42 is configured as a current mirror type.

The configuration of the sense amplifier circuits 41 and 42 differs from the sense amplifier circuits 41 and 42 shown in FIG.
Type 5 transistor Q33. The point is that the source of C34 is not directly connected to the ground potential G1, but is connected to the ground potential G via the NMO5 type transistor Q41. Specifically, both NMO5 type transistors Q33
．． The source of C34 is NMO5 type transistor Q41
connected to the drain of this N? The source of the 105 type transistor Q41 is connected to the ground potential G and ID, and the equalize signal 2 is applied to its gate via the enable terminal E as an enable signal.

Such sense amplifier circuits 41 and 42 operate as follows.

When the equalize signal 1 applied to the enable terminal E is @0'', that is, when it is in the disabled state, the IIIMO3 type transistor Q41 is turned off, so this sense amplifier circuit 4H42) does not operate.

When the equalize signal ■ applied to the enable terminal is “1”, that is, when it is in the enable state,
Since the NMO3 type transistor Q41 is turned on,
This sense amplifier circuit 41 (42) operates.

Figure 6 (al ~ (phantom is the second part of the full adder circuit shown in Figure 4)
3 is a timing chart showing the operation timing of the embodiment.

Figure 6 (a) - (Ite to gl, vc, is "tfit"
■ is the equalize signal, V is. indicates the equalized potential. In addition, FIG. 6 (al is the equalized signal 1, FIG. 6 fbl is the input signal, FIG. 6 (C1 to (
n indicates the signal lines 203, 204, 205, and 206, respectively, and FIG. However, the potentials of the signal lines 201 and 202, the potentials of the signal lines 203 and 204(7), and the potentials of the signal lines 205 and 206 are complementary to each other.

During the equalization period, that is, during the period when the equalize signal 1 is "0" as shown in FIG. 6 (M1), no data is input to this full adder circuit, as shown in FIG. At this time, signal lines 201 and 202, signal lines 203 and 204,
205 and 206 are shown in Fig. 6 fc1. (d+, (
81 and (fl), they are equalized to an equal potential v2° by equalizing transistors Q51 and Q52, respectively.

The first sense amplifier circuit 41 is in a disabled state, and therefore both output terminals of the first sense amplifier circuit 41 become high impedance. More specifically, l1
Since the MO5 type transistor Q41 is in the off state, current from the power supply potential VCC to the ground potential G1 is cut off, resulting in a high impedance state.

Further, the carry signal erasure circuit 61 and the carry signal generation circuit 62 are connected to the equalization transistor Q during the equalization period.
Since 53 and Q54 are off, it does not operate.

When the equalization period ends and the equalization signal becomes "1", data is input to this full adder circuit as shown in FIG.
The potentials of 204, 205, and 206 are as shown in Fig. 6 (C1 to ff
As shown in 1, the power supply potential VCC or the ground potential G begins to change in the direction of force. At this time, since the first sense amplifier circuit 41 is enabled, the signal lines 203 and 2
04 and the signal lines 205 and 206 become ΔV, the potential of the output signal of the first sense amplifier circuit 41 becomes the power supply potential ■. Alternatively, it becomes the ground potential GN6.

Fig. 7 fa+, (b) shows signal lines 203 and 2, respectively.
04 and the sum signal pair S, which is the output signal of the first sense amplifier circuit 41. FIG.

In FIG. 7, as shown in (a), at first the signal line 20
The potentials of 3 and 204 are equalized potentials V! Suppose it is at a. When the potentials of the signal lines 203 and 204 begin to change at time tO, and the potential difference between the signal lines 203 and 204 reaches Δ■ at time t7, the first sense amplifier circuit 41 as shown in FIG. works and the sum signal pair S
One device starts changing from a high impedance state at the same time. That is, the potential change of the sum signal pair S, T starts with only a slight delay of the time difference between times t7 and t10.

Therefore, by synchronizing the equalization signal 1 with the clock of the device in which the full adder circuit of the present invention is incorporated, it becomes possible to operate the full adder circuit of the present invention in synchronization with the entire device.

Note that in both the first and second embodiments, XOR
The first logic circuit 21 and the second logic circuit 22 for generating the signal and the XNOR signal are configured as shown in FIGS. 1 and 4, but other configurations are of course possible. be.

In addition, in the carry signal erasure circuit 61 and the carry signal generation circuit 62, the "0" level is set as active, but it is of course possible to set the "l# level as active, and similarly, the level guarantee circuit 3L32.33 is configured to guarantee the “1” level in both of the above embodiments, but
``Of course, it may be configured to guarantee 0 level or to guarantee both levels.

Further, although the sense amplifier circuits 41 and 42 are configured as a current mirror type in both of the above embodiments, it is of course possible to adopt other configurations.

〔Effect of the invention〕

As described in detail above, according to the full adder circuit of the present invention, it is possible to eliminate the variable axes of the threshold potentials of the circuit constituent elements, thereby realizing a full adder circuit that can operate at higher speed. Further, by controlling with an equalize signal, clock synchronization with other circuits can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a configuration example of the first embodiment of the full adder circuit of the present invention, FIG. 2 is a circuit diagram showing the configuration of its sense amplifier circuit, and FIG. 3 is a timing diagram showing its operating state. 4 is a circuit diagram showing a configuration example of the second embodiment of the full adder circuit of the present invention, FIG. 5 is a circuit diagram showing the configuration of the sense amplifier circuit, and FIGS. 6 and 7 are FIG. 8 is a circuit diagram showing an example of the configuration of a conventional full adder circuit, and FIG. 9 is a timing chart showing its operating state. 21.22...Logic circuit 31, 32.33...
・Level guarantee circuit 41.42...Sense amplifier circuit 51.52...Transmission gate circuit 61...Carry signal deletion circuit 62...Carry signal generation circuit Q
51. Q52. Q53. Q54...Equalizing transistor Note that the same reference numerals in each figure indicate the same or corresponding parts. Funeral map of agent Masuo Oiwa

Claims (3)

[Claims] (1) A complementary addend signal pair, a complementary addend signal pair, and a complementary carry input signal pair are input, and a first complementary signal pair indicating the addition result and the occurrence of a carry are input. A full adder circuit that outputs a second complementary pair of signals indicating presence or absence, the first sense amplifier circuit outputting a pair of complementary sum signals based on a potential difference or current difference between the first complementary signal pair; , a second pair of complementary carry output signals outputting a pair of complementary carry output signals according to a potential difference or a current difference between the second pair of complementary signals;
A full adder circuit characterized by comprising a sense amplifier circuit. (2) A first logic circuit that inputs a complementary addend signal pair and a complementary summand signal pair and outputs a first exclusive OR signal and a first negative exclusive OR signal. and a first guaranteeing a first or second potential for a signal pair of the first exclusive OR signal and the first negative exclusive OR signal output from the first logic circuit. a level guarantee circuit; inputting the first exclusive OR signal, the first negative exclusive OR signal, and a pair of complementary carry input signals to generate a second exclusive OR signal and the second exclusive OR signal; a second logic circuit that outputs a negative exclusive OR signal; and a signal of the second exclusive OR signal and the second negative exclusive OR signal output from the second logic circuit. a second exclusive OR signal that guarantees the first or second potential for the pair, and outputs the second exclusive OR signal and the second negative exclusive OR signal as a complementary sum signal pair; using a level guarantee circuit and at least one of the first exclusive OR signal and the first negative exclusive OR signal,
first and second gate circuits that respectively pass or block the input pair of complementary carry input signals; and when the first gate circuit is in a blocking state, the pair of addend signals and the summand signal a carry signal generation circuit that generates a carry generation signal based on the pair; and a carry signal generation circuit that generates a carry deletion signal based on the addend signal pair and the summand signal pair when the second gate circuit is in a cutoff state. an erasing circuit; and each signal output from the carry signal generating circuit and the carry signal erasing circuit has the first or second
and a third level guarantee circuit that guarantees the potential of the second gate circuit and outputs the outputs of the first and second gate circuits as a pair of complementary carry output signals, a first sense amplifier circuit that outputs a complementary sum signal pair based on a potential difference or current difference between the second exclusive OR signal and the second negative exclusive OR signal output from the level guarantee circuit; and a second sense amplifier circuit that outputs a pair of complementary carry output signals based on a potential difference or current difference between the outputs of the first and second gate circuits output from the third level guarantee circuit. A full adder circuit characterized by: (3) A first logic circuit that inputs a complementary addend signal pair and a complementary summand signal pair and outputs a first exclusive OR signal and a first negative exclusive OR signal. and a first guaranteeing a first or second potential for a signal pair of the first exclusive OR signal and the first negative exclusive OR signal output from the first logic circuit. a level guarantee circuit; inputting the first exclusive OR signal, the first negative exclusive OR signal, and a pair of complementary carry input signals to generate a second exclusive OR signal and the second exclusive OR signal; a second logic circuit that outputs a negative exclusive OR signal; and a signal of the second exclusive OR signal and the second negative exclusive OR signal output from the second logic circuit. a second exclusive OR signal that guarantees the first or second potential for the pair, and outputs the second exclusive OR signal and the second negative exclusive OR signal as a complementary sum signal pair; using a level guarantee circuit and at least one of the first exclusive OR signal and the first negative exclusive OR signal,
first and second gate circuits that respectively pass or block the input pair of complementary carry input signals; and when the first gate circuit is in a blocking state, the pair of addend signals and the summand signal a carry signal generation circuit that generates a carry generation signal based on the pair; and a carry signal generation circuit that generates a carry deletion signal based on the addend signal pair and the summand signal pair when the second gate circuit is in a cutoff state. an erasing circuit; and each signal output from the carry signal generating circuit and the carry signal erasing circuit has the first or second
and a third level guarantee circuit that guarantees the potential of the first and second gate circuits and outputs the outputs of the first and second gate circuits as a pair of complementary carry output signals, , equalizing means for matching the potentials of the second exclusive OR signal and the second negative exclusive OR signal; means for inhibiting operation; and a potential difference or current difference between the second exclusive OR signal and the second negative exclusive OR signal output from the second level guarantee circuit outside the predetermined period. a first sense amplifier circuit that outputs a pair of complementary sum signals and does not operate during the predetermined period; and a second sense amplifier circuit that outputs a pair of complementary carry output signals based on the potential difference or current difference between the outputs of the second gate circuit and does not operate during the predetermined period. circuit.