JPH02206916A - Clock switching type phase locked loop oscillating circuit for phase locking - Google Patents

Abstract

PURPOSE:To prevent an output clock signal from generating disturbance even at system switching by resetting a frequency divider circuit frequency-dividing an input clock signal with a selected phase locking clock signal so as to make the phases of phase locking clock signals of two systems coincident with each other. CONSTITUTION:Singles being the result of differentiating output signals B, E from 2 systems of frequency divider circuits 3, 4 at differentiating circuits 5, 6 respectively are inputted to a selection circuit 7 as phase locking clock signals C, F, a selected phase locking clock signal H is used as a reference signal to a phase comparator 9 and the signal H is used to reset 2 systems of the frequency divider circuits 3, 4. The output phase of the frequency divider circuits 3, 4 is set properly at the reset of the frequency divider circuits to make the phase of the phase locking clock signals C, F for the two systems inputted to the selection circuit 7 coincident with each other. Thus, there is no phase change exists in the reference signal to the phase comparator 9 even at the switching of the phase locking clock signal and of disturbance takes place in the output clock signal.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides two clock signal generation units in a communication device.
The present invention relates to a phase synchronized oscillation circuit that selects one of the reference input signals of a system and generates various clock signals synchronized with it.

[Conventional technology]

FIG. 5 is a block diagram of a conventional phase synchronization clock switching type phase synchronization oscillator circuit disclosed in, for example, Japanese Patent Application Laid-Open No. 136741/1983, and in the figure (1) is a first clock signal input terminal; (2) is a second clock signal input terminal;
(3) is a first frequency dividing circuit that frequency divides the first input clock signal, and (4) is a second frequency divider circuit that frequency divides the second input clock signal.
(7) is a selection circuit, (8) is a selection circuit (7).
), (9) is a phase comparator,
αQ is a phase synchronized oscillation circuit, (6) is a third frequency dividing circuit that divides the frequency of the output clock signal, and @ is a clock signal output terminal.

Next, the operation will be explained. The clock signals input from the clock input terminals (1) and (2) are divided by the frequency dividing circuits (3) and (4), respectively, to generate phase synchronization clock signals, which are input to the selection circuit (7). Ru.

The selection circuit (7) selects one of the two systems of phase synchronization clock signals according to the selection signal from the selection signal input terminal (8), and inputs it to the phase comparator (9) as a reference signal. . On the other hand, the phase comparator (9) receives a feedback clock signal obtained by dividing the output clock signal by the frequency dividing circuit (6), and compares the phase with the phase synchronization clock signal from the selection circuit (7). Then, a phase difference signal corresponding to the phase difference between the two is output. The phase synchronized oscillator circuit αQ controls the frequency of the output clock signal according to this phase difference signal,
By adjusting the oscillation frequency so that the phase difference between both clock signals input to the phase comparator (9) becomes small,
An output clock signal synchronized with the selected input clock signal is obtained. Next, the selection circuit (when the phase synchronization clock signal selected by the switching signal is switched,
In accordance with the phase of the new phase synchronization clock signal input to the phase comparator (9), synchronization is pulled in by the phase synchronization oscillation circuit αQ, and the clock signal synchronized with the selected clock signal after switching becomes the clock signal. Output from output terminal @.

[Problem to be solved by the invention]

The conventional phase synchronization clock switching type phase synchronization oscillator circuit is
Since it is configured as above, the first frequency dividing circuit (3)
Phase synchronization clock signal from and second frequency divider circuit (4)
There is no guarantee that the phases of the phase synchronization clock signals from the Therefore, when switching the clock signal for phase synchronization,
The phase of the reference signal input to the phase comparator (9) changes, and accordingly, a phase difference signal is generated from the phase comparator (9), causing disturbance to the output clock signal from the phase synchronized oscillator circuit α0. There was a problem that occurred.

This invention was made to solve the above-mentioned problems, and provides a phase synchronization clock switching type phase synchronization oscillator circuit that does not cause disturbance in the output clock signal even when switching the phase synchronization clock signal. The purpose is to obtain.

[Means to solve the problem]

In the phase synchronization clock switching type phase synchronization oscillator circuit according to the present invention, the signals obtained by differentiating the output signals from the two frequency dividing circuits by differentiating circuits are inputted to the selection circuit as the phase synchronization clock signal, and the selected The clock signal for phase synchronization is used as the reference signal to the phase comparator, and that signal is used to
This resets the frequency divider circuit of the system.

[Effect]

By appropriately setting the output phase of the frequency dividing circuit when resetting the frequency dividing circuit, the phases of the two systems of phase synchronization clock signals input to the selection circuit match.

Therefore, even when the clock signal for phase synchronization is switched, there is no phase change in the reference signal to the phase comparator, and no disturbance occurs in the output clock signal. Explain the diagram. 1st
In the figure, (1) is the first clock signal input terminal, (2
) is a second clock signal input terminal, (3) is a frequency divider circuit that divides the first input clock signal, (4) is a divider/frequency circuit that divides the second input clock signal, (5) is a first differentiating circuit that differentiates a clock signal of a predetermined frequency from the first frequency divider circuit (3), and (6) differentiates a clock signal of a predetermined frequency from the second frequency divider circuit (4). (7) is a selection circuit that selects one of the output signals from the two systems of differentiation circuits; (8) is a selection signal input terminal that controls the selection circuit; (9) is a phase comparison circuit; αQ is a phase-locked oscillation circuit, and ση is a third circuit that divides the output clock signal.
4 is a frequency dividing circuit, and 4 is a clock signal output terminal.

Further, FIG. 2 shows a waveform diagram corresponding to the signal names on each line shown in FIG. 1. In the waveform diagram, as an example, the frequency division ratio of the first frequency division circuit (3) is -, the frequency division ratio of the second frequency division circuit (4) is 1, and the differentiation circuit (5) 9 (6) Now let us differentiate the falling edges of the signals B and H, respectively.

The first input clock signal A is frequency-divided by a frequency dividing circuit (3) to generate a clock signal B of a predetermined frequency.
The falling edge of the signal C is differentiated by the differentiating circuit (5) and becomes the signal C. When the level of the selection signal G from the outside is "L", the selection circuit (7) selects the signal C. Then, the signal C passes through the selection circuit (7) and is sent to the first and second frequency dividing circuits. As shown in FIG. 2, the falling phases of signal B and signal E coincide with each other. As a result,
The phases of the differentiated signal C1 and signal F also match. Subsequently, when the level of the selection signal G changes to °H°, the selection circuit (7)
In this case, signal F is selected, but since the phases of signal C and signal F match, no change in phase occurs in signal H after selection. On the other hand, the signal H, that is, the signal F selected by the selection circuit (7), is applied to the reset terminals of the first and second frequency divider circuits with the same phase as before switching, and as shown in FIG.
, E and the signals C, F remain in phase. Therefore, even if the selection signal G changes to °L'' again, the signal H
There is no change in the phase of

Due to the above operation, even if switching occurs in the selection circuit (7), the phase of the reference signal H to the phase comparator (9) is always kept constant, and as a result, the output clock signal from the phase synchronized oscillator circuit (LO) There will be no disturbance.

Note that in the above embodiment, the differentiating circuits (5) # (6) are placed after the frequency dividing circuits (3) # (4), but when the frequencies of the first and second input clock signals are the same, is one differential circuit (
) may be placed after the selection circuit (7).

〔Effect of the invention〕

As described above, according to the present invention, by resetting the frequency divider circuit that divides the frequency of the input clock signal by the selected phase synchronization clock signal, the phases of the two systems of phase synchronization clock signals can be matched. Therefore, even during system switching, the phase of the reference signal to the phase comparator is kept constant, and there is an effect that no disturbance occurs in the output clock signal from the phase synchronized oscillation circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a phase synchronization clock switching type phase synchronization oscillation circuit according to an embodiment of the present invention, and FIG. 2 illustrates the operation of a phase synchronization clock switching type phase synchronization oscillation circuit according to an embodiment of the present invention. The waveform diagrams of each part of the circuit, FIGS. 3 and 4, are the circuit configuration diagrams in other embodiments, and FIG.
The figure is a configuration diagram of a conventional phase synchronization clock switching type phase synchronization oscillation circuit. In each figure, (1) is a first clock signal input terminal, (2) is a second clock signal input terminal, (3) is a first frequency dividing circuit, (4) is a second frequency dividing circuit,
(5) is the first differentiating circuit, (6) is the second differentiating circuit, (
7) is a selection circuit, (8) is a selection signal input terminal, (9) is a phase comparator, CIG is a phase synchronized oscillation circuit, αυ is a third frequency dividing circuit, and @ is a clock signal output terminal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In a phase synchronized oscillator circuit that selects one of two input clock signals to generate a synchronized clock signal, a first input clock signal is frequency-divided to generate a clock signal of a predetermined frequency. a frequency divider circuit, a second frequency divider circuit that divides the second input clock signal to generate a clock signal of a predetermined frequency, and differentiates the outputs of the first and second frequency divider circuits, respectively. First and second differentiating circuits that generate clock signals for phase synchronization, and one of the clock signals for phase synchronization from the first and second differentiating circuits according to the logic of a selection signal input from the outside. a selection circuit that selects the signal and resets the first and second frequency dividing circuits with the selected signal; a phase comparator that uses the output signal from the selection circuit as a reference input signal; A phase synchronized oscillation circuit generates an output clock signal of a predetermined frequency synchronized with a reference input signal according to a phase difference signal, and a clock signal of a frequency for phase comparison is generated from the output clock signal. and a third frequency dividing circuit that supplies the phase comparator to the phase comparator, so that there is no disturbance in the phase of the output clock signal from the phase synchronization oscillation circuit even at the moment when the phase synchronization clock signal from the selection circuit is switched. A clock switching type phase synchronization oscillator circuit for phase synchronization, characterized in that the phase synchronization clock switching type phase synchronization oscillator circuit is characterized in that the phase synchronization clock does not occur.