JPH08149000A - PLL circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] A wideband PL that switches multiple VCOs.
In the L circuit, another VC is released before the VCO is unlocked.
Switch to O so that the lock does not come off. [Structure] In phase comparator 2, an external signal from terminal 1 and N /
The phases of the comparison signals from the M counter 8 are compared, the phase difference signal is input to the LPF 3, and unnecessary frequency components are filtered.
A signal from the LPF is applied to the VCO 5b via the switch 4, a clock having a frequency corresponding to the signal voltage is oscillated, output from the terminal 7 via the switch 6, and simultaneously input to the N / M counter for multiplication / minute division. And the frequency is returned to the phase comparator. The signal from the LPF is applied to the voltage comparators 9 and 10, and the voltage comparator 9 compares the lower limit voltage E1 with which the lock is not lost and the voltage comparator 10 with the upper limit voltage E2.
Is output and input to the CPU. Based on these signals, the CPU switches to the VCO 5a or 5c when the control voltage reaches the lower limit voltage or the upper limit voltage.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a PLL (phase locked l
oop = VCO (voltage control)
lled oscillator = voltage-controlled oscillator circuit) and a wide lock range is obtained by switching these.

[0002]

2. Description of the Related Art In order to digitally process a video signal, a clock synchronized with the video signal is required. A PLL circuit is often used to generate a clock, but in order to lock the input signal in a wide frequency range, a VC having a wide frequency variable range is used.
O is required. However, widening the frequency variable range of the VCO has a problem of lowering frequency stability. Therefore, a method is used in which a plurality of VCOs having different oscillation frequencies are provided and these are switched to widen the lock range. FIG.
Is an example of a conventional PLL circuit for such a purpose. In this circuit, the horizontal synchronizing signal from the terminal 1 is applied as a reference signal to the phase comparator 2, the phase is compared with the comparison signal from the N / M (multiplication / division) counter 8, and the phase difference is determined. The difference signal voltage is output, and this difference signal voltage is set to LPF (low pa
ss filter = low-pass filter) 3 to integrate, and apply to VCO 5a, 5b or 5c via switch 4 to control the oscillation frequency, and the output of this VCO is multiplied / divided by N / M counter 8 for comparison. The signal is fed back to the phase comparator 2 to output a clock synchronized with the reference signal from the terminal 1.

The VCO 5a, 5b or 5c is switched by the CPU
(Central processing circuit) It is performed by interlocking the switch 4 and the switch 5 with a signal from 21,
For example, the oscillation frequency of the VCO is centered around VCO5b,
When the VCO 5a is for a high frequency region and the VCO 5c is for a low frequency region, the switches 4 and 6 are first switched to the b side to activate the VCO 5b, and the lock detection signal f2 from the phase comparator 2 as shown in FIG. Is at L level (locked state)
From H level (out of lock due to phase lead), switches switches 4 and 6 to a side to activate VCO 5a, and lock detection signal f1 goes from L level (lock state) to H level (due to phase delay). If the lock is released), switch switches 4 and 6 to the c side to turn VCO5c
Is working. As a result, if the input signal is within the lock range of the three VCOs, a clock synchronized with this signal can be stably obtained.
Since the CPU 21 switches the VCO after the lock is released,
There is a problem that the screen is distorted due to a temporary loss of synchronization when switching.

[0004]

SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention is directed to switching a plurality of VCOs without unlocking and eliminating the disturbance of the screen due to the switching of VCOs.

[0005]

In order to solve the above-mentioned problems, the present invention provides a phase comparator for comparing the phases of a reference signal from the outside and an internal comparison signal and outputting a phase difference signal,
A low-pass filter (LPF) that filters unnecessary frequency components of the signal from the phase comparator; a plurality of voltage-controlled oscillation circuits that respectively oscillate clocks having a frequency corresponding to the signal voltage from the low-pass filter; A switch for switching the voltage controlled oscillation circuit, a frequency divider for dividing the signal from the voltage controlled oscillation circuit and inputting it to the phase comparator, and a voltage set as a lower limit at which the signal from the low pass filter is not out of lock. A first voltage comparator that outputs an H-level signal when the comparison result is low, and a first voltage comparator that outputs an H-level signal when the comparison result is higher than the voltage set as the upper limit of lock release of the signal from the low-pass filter. From a two-voltage comparator and a CPU that operates on the basis of the signal from the first voltage comparator and the signal from the second voltage comparator, and switches the switch with the signal resulting from the operation. There is provided a PLL circuit form.

[0006]

With the above construction, the PL according to the present invention
In the L circuit, a plurality of VCOs are set so that clocks of different frequencies are oscillated with the same control voltage and the lock ranges overlap each other. Two voltage comparators are provided, the signal voltage from the LPF is compared with the lower limit voltage without lock and the upper limit voltage without lock, a signal based on the comparison is applied to the CPU, and the oscillation frequency of the operating VCO. The VCO is switched by switching the switch depending on whether the lock is below the lower limit of unlocking or above the upper limit of unlocking.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a PLL circuit according to the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a PL according to the present invention.
It is a principal part block diagram of one Example of L circuit. In the figure, 1 is an input terminal, which is a reference horizontal synchronizing signal (H-syn
c) Enter etc. Reference numeral 2 is a phase comparator which compares the phases of the reference signal from the input terminal 1 and the comparison signal from the N / M counter (multiplier / divider) 8 to obtain a difference signal voltage corresponding to the phase difference and a lock detection signal f1. , F2 are output respectively. The lock detection signals f1 and f2 are both "L" while locked.
It is a level, and when the phase of the comparison signal advances with respect to the reference signal and the lock is released, f2 becomes “H” level, and when the phase of the comparison signal is delayed from the reference signal and the lock is released, f1 becomes “H”. It becomes a level.

An LPF 3 filters an unnecessary frequency component of the difference signal voltage from the phase comparator 2. 4 is a switch, L
Signal voltage from PF3 is VCO5a, VCO5b or VC
Switch to O5c and input. VCO5a, VCO5b and V
CO5c is a voltage controlled oscillation circuit that oscillates a clock having a frequency corresponding to the signal voltage from the LPF 3, respectively, and oscillates clocks having different frequencies with the same signal voltage,
Set the center frequency so that the lock ranges overlap each other. Reference numeral 6 denotes a switch, which interlocks with the switch 4 to switch the output of the VCO 5a, VCO 5b or VCO 5c and output from the terminal 7.

The N / M counter 8 multiplies / divides the clock from the switch 6 so that it has the frequency of the horizontal synchronizing signal from the input terminal 1 to generate a comparison signal, which is fed back to the phase comparator 2. Reference numeral 9 is a voltage comparator which compares the signal voltage from the LPF 3 with a lower limit voltage E1 of the lock that cannot be unlocked by any of VCO5a, VCO5b and VCO5c, and when the lower limit voltage E1 or less, outputs an "H" level signal S1. Output. Ten
Is a voltage comparator for converting the signal voltage from the LPF3 to VCO5
Compared with the lock upper limit voltage E2 at which any of a, VCO5b and VCO5c is unlocked, when it is equal to or higher than the upper limit voltage E2, the "H" level signal S2 is output. Reference numeral 11 denotes a CPU, which is a signal S1 from the voltage comparator 9 and a signal S2 from the voltage comparator 10.
Is input, and when the signals S1 and S2 are both at the “L” level, a signal that fixes the switches 4 and 6 to the b side is output, the signal S1 is at the “L” level, and the signal S2 is at the “H” level. In the case of, a signal for switching the switches 4 and 6 to the a side is output, the signal S1 is at the "H" level, and the signal S2 is at the "L" level.
In the case of the level, a signal for switching the switches 4 and 6 to the c side is output. When the lock detection signal f1 from the phase comparator 2 becomes the "H" level, the CPU 11 releases the lock due to the phase delay of the comparison signal, and the lock detection signal.
When f2 becomes "H" level, it is judged that the lock is released due to the phase advance of the comparison signal.

Next, the operation of the PLL circuit according to the present invention will be described. The phase comparator 2 compares the phases of the horizontal synchronizing signal (reference signal) from the input terminal 1 and the comparison signal from the N / M counter 8 and outputs a difference signal voltage and a lock detection signal according to the phase difference. To do. Unwanted frequency components of the difference signal voltage are filtered by the LPF 3, and the difference signal voltage is switched to VC via the switch 4.
Applied to O5b. The VCO 5b oscillates a clock having a frequency corresponding to the signal voltage from the LPF 3 and outputs it from the terminal 7 via the switch 6. Clock from VCO5b is N /
It is input to the M counter 8, multiplied by N times so as to have the frequency of the reference signal from the terminal 1, divided by M, and fed back to the phase comparator 2. VCO5a, VCO5b and VCO
5c is, for example, the lower limit control voltage E1 at which the lock is not released and the upper limit control voltage at which the lock is not released due to different oscillation frequencies at the center voltage shown in FIG.
The E2s are set to be substantially the same, and the lock ranges (control voltages E1 to E2 in the figure) are set so that the three VCOs are vertically overlapped with each other. In addition, in the example of FIG.
Although three VCOs are provided, two VCOs are provided depending on the stability of the horizontal sync signal that must be processed, or four VCOs are provided.
You may make it provide more than one piece.

The voltage comparator 9 and the voltage comparator 10 have LP
The signal voltage from F3 is applied. The voltage comparator 9 sets this signal voltage as the lower limit at which the lock is not released.
Compared with E1, when the signal voltage is lower than the voltage E1, it outputs the signal S1 of “H” level, and the voltage comparator 10 compares the signal voltage with the voltage E2 set as the upper limit of the lock, and then the voltage E2. When it is higher, the "H" level signal S2 is outputted and inputted to the CPU 11, respectively.

The CPU 11 calculates based on these signals. That is, when both the signal S1 and the signal S2 are at the "L" level, a signal for fixing the switches 4 and 6 to the b side is output, and when the signal S1 is at the "L" level and the signal S2 is at the "H" level. A signal for switching the switches 4 and 6 to the side a is output. This is because the frequency of the horizontal synchronizing signal from the terminal 1 moves to the higher side and the voltage from the LPF3 applied to the VCO 5b rises to the voltage E2 or higher, which causes the oscillation frequency of the VCO 5b to be as shown in (b) of the figure. Since it is in the upper "switching region", the switches 4 and 6 are switched to the side a, so that the switch is switched to the VCO 5a which is set to oscillate a frequency higher than the VCO 5b (arrow A). Avoid unlocking. When the signal S1 is at "H" level and the signal S2 is at "L" level, a signal for switching the switches 4 and 6 to the c side is output. This is terminal 1
The frequency of the horizontal sync signal from the above shifts to the lower side, so that the voltage from the LPF3 applied to the VCO 5b becomes a voltage.
This is because the voltage drops below E1 and the oscillation frequency of the VCO 5b is in the "switching region" at the bottom of (b) in the figure.
When 6 and 6 are switched to the c side (arrow B), the VCO 5c is set to oscillate at a frequency lower than the VCO 5b, and the lock is held.

[0013]

As described above, P according to the present invention
According to the LL circuit, the frequency of the horizontal synchronizing signal from the outside moves up and down from the center value and the control voltage of the VCO fluctuates.
When LL is about to come out of the lock range, the lock is not released because the VCO is switched to another VCO before the lock is released. Therefore, in the device using the clock generated by this PLL circuit, the screen is not disturbed due to the unlocking even when processing a video signal having a large frequency fluctuation of the horizontal synchronizing signal.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of an embodiment of a PLL circuit according to the present invention.

FIG. 2 is a diagram for explaining VCO switching.

FIG. 3 is a block diagram of a main part of an example of a conventional PLL circuit.

FIG. 4 is a diagram for explaining VCO switching in a conventional PLL circuit.

[Explanation of symbols]

 1 Reference signal input terminal 2 Phase comparator 3 LPF 4 switch 5 VCO 6 switch 8 N / M (multiply / divide) counter 9 Voltage comparator 10 Voltage comparator 11 CPU E1 Unlockable lower limit voltage E2 Unlockable Upper limit voltage

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H04N 5/12 A

Claims (8)

[Claims] 1. A phase comparator that compares the phases of an external reference signal and an internal comparison signal and outputs a phase difference signal, and a low-pass filter that inputs the signal from the phase comparator and filters unnecessary frequency components. A voltage-controlled oscillation circuit that oscillates a plurality of clocks each having a frequency corresponding to the voltage of the signal from the low-pass filter, a switch that switches the plurality of voltage-controlled oscillation circuits, and a clock from the voltage-controlled oscillation circuit. A frequency divider which divides the frequency and inputs it to the phase comparator; and a first voltage comparator which compares the signal from the low-pass filter with a first reference voltage and outputs an H-level signal when the signal is lower than the first reference voltage. A second voltage comparator that compares the signal from the low-pass filter with a second reference voltage and outputs an H-level signal when the signal is higher than the second reference voltage; and a signal and a second voltage from the first voltage comparator. Comparison Calculation based on the signal from the instrument,
A PLL circuit composed of a CPU that switches the switch by a signal obtained by calculation. 2. The PLL circuit according to claim 1, wherein the first reference voltage is a voltage set as a lower limit of lock release, and the second reference voltage is a voltage set as an upper limit of lock release. 3. A frequency multiplier for multiplying a frequency and a frequency divider for frequency dividing are provided, and a signal from the voltage controlled oscillator circuit is multiplied and divided, and is input to the phase comparator. The PLL circuit according to claim 1 or claim 2. 4. The voltage controlled oscillator circuit is configured to oscillate clocks of different frequencies with the same control voltage.
The described PLL circuit. 5. The plurality of voltage controlled oscillator circuits oscillate clocks of different frequencies with the same control voltage,
The PLL circuit according to claim 1, claim 2, claim 3 or claim 4, wherein the lock ranges overlap each other. 6. The plurality of voltage controlled oscillation circuits are configured such that a lock lower limit voltage and a lock upper limit voltage are substantially the same voltage, respectively. The PLL circuit according to claim 4 or claim 5. 7. The PLL circuit according to claim 1, claim 2, claim 3, claim 4, claim 5, or claim 6, wherein the voltage controlled oscillator circuit is provided in three circuits. 8. The switch is composed of a first switch and a second switch which are interlocked with each other. The first switch switches the input side of the plurality of voltage controlled oscillation circuits to input a signal from the low pass filter. The PLL circuit according to claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, or claim 7, wherein the output side of the plurality of voltage-controlled oscillation circuits is switched by two switches.