JPH02207366A - Inter-processor communication system - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an inter-processor communication method that enables communication between multiple processors in a multiprocessor system and also between other processors. .

[Conventional technology]

FIG. 7 is a block connection diagram of a microprocessor system showing a conventional inter-processor communication method disclosed in, for example, Japanese Patent Application Laid-Open No. 60-237566.
．． 2 is a processor, 4 is a shared memory, and 5.6 is an interrupt cause signal.

Next, the operation will be explained.

As shown in FIG. 7, data is exchanged by providing a shared memory 4 that can be accessed by either processor 1 or processor 2. This shared memory 4
can be used by processor 1 or processor 2 in the same way as its own memory, and an area of this shared memory 4 can be used, for example, for transmitter processor 1 and receiver processor 2.
Decide and allocate addresses separately for use. Therefore,
The sending processor 1 writes data such as instructions or status that it wants to send to the receiving processor 2 as the destination processor in the area assigned to it. This is done just like normal memory access. After writing the data, the transmitting processor 1 sends a KI10 command to the receiving processor 2. The receiving processor 2 is set so that the instruction from the transmitting processor 1 causes an interrupt to the receiving processor 2. The receiving processor 2 also allows the transmitting processor 1 to immediately move on to the next process.
F) Immediately sends back a response signal to terminate the I10 command, etc. The receiving processor 2 may then read and process data such as instructions sent from the transmitting side at any time of its own choosing. At this time, it does not matter whether the transmitting processor is the processor 1t or 2, and it is possible to communicate using the same method. Although the above description has been made regarding the two processors 1 and 2, it is clear that the same method can be used between a plurality of processors. Also, when data is transferred using the method described above, if the processing speeds of both processors 1 and 2 do not match (for example, one processor 1 has a lot of data to send to the other processor 2, but the receiving processor If processor 2 is busy with other processing and does not have time to receive the data, it must confirm receipt of the data.In this case, when the receiving processor 2 completes reception, it clears the area. By clearing (or accepting a certain response pattern), the sending processor 1 is notified that the data has not yet been processed. , even if there is data to be sent, a waiting process is performed.By doing this, data loss due to differences in processing speed between the processors 1 and 2 can be avoided.

FIG. 8 is a two-chart showing the above operation. In the figure, the transmission area and reception area are the same address area on the shared memory 4 as shown in Figure 7, and are named transmission area and reception area depending on the direction of data flow. There is.

Further, if the transmission area (reception area of the other party) is divided for each processor 1 and 2 so that the transmission side processor 1 and the reception side processor 2 can be interchanged, there will be no data interference.

Next, the operation of each step of the chart 70 in FIG. 8 will be explained. First, sender access? In step 1, it is determined whether there is transmission data or not and whether the transmission area of the shared memory 4 is empty, respectively, and in step 5T201,
5T202) If there is no transmission data or if the transmission area is not empty, the transmission process ends. On the other hand, if step 5T202 is empty, data is written in the transmission area (step 5T203), and an interrupt notification is sent to the destination processor, which is the receiving processor 2 (step 5T204).

On the other hand, the receiving processor 2 processes the interrupt made in step 5T204, responds to the transmitting processor 1 (step 5T206), and reads the receiving area (step 5T207). Clear the reception area (Step 5T2)
08), the reception process ends. Note that step 5 above
When the sending processor 1 confirms that the response has been returned to the sending side at T206 (step 5T205),
End the sending process.

[Problem to be solved by the invention]

Since the conventional inter-processor communication system is configured as described above, for example, when data from the transmitting processor 1 is being communicated to the receiving processor 2, other processors other than the transmitting processor 1 or the receiving processor 2 If communication is to be performed to processor 2 on the receiving side, processors 1 and 2
．． . . . If a receiving area is provided for each processor, it is necessary to make the communication to the processor 2 of the other processor wait until the receiving processor 2 completes receiving the communication from the transmitting processor 1, and the gross set t1.2 ．． -... In addition to the overhead of communication between processors 1, 2... If a transmission area and a reception area are provided for a combination of It had problems such as not being able to be used with processor systems.

This invention was made to solve the above-mentioned problems, and even when communication is in progress from a sending processor to a receiving processor, communication from another processor to the receiving processor can be interrupted. It is an object of the present invention to provide an inter-processor communication method that can suppress an increase in the transmission/reception area of a shared memory compared to the number of processors even if the number of processors in a multiprocessor system increases.

[Means to solve the problem]

The inter-processor communication method according to the present invention divides a shared memory, allocates areas, and stores information on the presence of data in each of these areas.

By storing information and communication data of the other processor and notifying the other processor of an interrupt, communication between processors is performed at high speed.

[Effect]

The shared memory in this invention is divided into a plurality of areas, and each area stores information on whether data is being written, data presence or no data, information on the other processor, and communication data, and each area stores , the transmitting side processor searches for an area with no data in the shared memory, stores the data presence information and the other party's processor information 1 communication data in this area, and operates to notify the other party's processor, the receiving side processor. .

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 1 is a processor, 2 is a processor, 3 is a processor, and 4 is a shared memory.

Further, 12.21 is an interrupt signal between processor 1 and processor 2, 13.31 is an interrupt signal between processor 1 and processor 3, and 23.32 is an interrupt signal between processor 2 and processor 3. - On the other hand, the shared memory 4 is divided into a plurality of areas 4AK as shown in FIG. Area 4b is a processor information writing area in which processor information of the communication partner is written, and 4c is a communication data writing area.

Next, the operation will be explained. It is assumed that all contents of the shared memory 4 are 101 in the initial state.

First, the transmitting side processing from the processor 1 as the transmitting side processor to the processor 2 as the receiving side processor will be explained according to the flowchart of FIG. First, the processor 1 determines the presence or absence of transmission data in step ST.
I), if there is one, start the transmission operation. Next, the processor 1 searches for the data state write area 4a in which the no-data pattern 100'' is stored in the area 4A of the shared memory 4, and searches for the data state write area 4a in which the no-data pattern 100'' is stored, and searches for the data state write area 4a in which the no-data pattern 100'' is stored.
10'' (step ST2).The processor 1 also writes the other party's processor information writing area 4bK.
, writes a pattern indicating the processor 2 of the communication partner (step ST3'), and writes data to be transmitted in the communication data writing area 4c (step ST4). moreover,
Processor 1 writes pattern "20" with data in data state writing area 4a (step 5T5), and uses interrupt signal 12 to generate an interrupt to processor 2 to notify a communication request (step ST6). Next, 1 processor 1 refers to the data status writing area 4a, checks whether the pattern 1001 with no data has been written, and if so, indicates the completion of communication. Chishi, step 5TIK return (step 5T7
).

Next, in the interrupt processing on the processor 2 side, the processor 2 sequentially examines the area 4A in the shared memory 4 from the beginning, examines the contents of the destination processor information writing area 4b, and writes a pattern that matches its own. It is checked whether the pattern 1201 with data is written (Step 5 TII), and if it matches the self, the contents of the data status writing area 4a are further checked to determine whether the data presence pattern 1201 is written (Step 5 T12). ). Step 5TI1. If it is determined in step 5T12 that the area 4A does not match with itself or that there is no data, the area 4A is advanced to the next step, all areas 4A of the shared memory 4 are checked, and these steps are repeated (step 5T13). On the other hand, if all areas are completed in step 5T13, the interrupt processing ends.

Next, if it is determined in step 5T12 that there is data, the processor 2 receives the contents of the communication data writing area 4c and transfers the data to the receiving area in step 5T.
14) Writes a pattern "LOOM" with no data in the data state writing area 4a (step 5T15), and ends the interrupt processing.

Furthermore, in the processing of the processor 2, the processor 2 checks whether or not there is area 4AK data (step 5T).
21) If there is, process the data in area 4A, and after completing this processing, erase the data in area 4A (step 5T22).

FIG. 4 is a flow diagram showing another inter-processor communication method in the multiprocessor system shown in FIG. According to this, each step 5T31 to step 5T37 in the transmission side processing from processor 1 to processor 2 is as follows.
Each step STI to step ST7 in the case shown in FIG.
This is the same as before. In this case, step 5T3
In step 7, the processor 1 refers to the data status writing area 4a and determines the pattern g3ol that is currently receiving data based on its contents.
When it detects that has been written, it knows that the communication is complete and returns to step 5T31.

Next, in the interrupt processing on the processor 2 side, the processor 2 sequentially examines the area 4A of the shared memory 4 from the top,
Check the contents of the destination processor information writing area 4b,
Check whether there is a pattern that matches the self (step 5T61), and if there is a matching pattern, then check the data status writing area 4a and check whether the pattern "20" with data is written. (Step 5)
T62).

Here, step 5T61. If any of the determination results in step 5T62 is negative (NO), advance to area 4A and repeat the process in step 5T61 until all areas 4A of shared memory 4 are examined. 5T63), the interrupt processing ends when all areas 4A are completed. On the other hand, if it is determined in step 5T62 that there is data, a pattern 130'' indicating that data is being received is written in the data status writing area 4a (step 5T62).
T64), the interrupt processing ends.

On the other hand, in the processing of the processor 2, the processor 2 examines the area 4A of the shared memory 4 starting from the beginning)
Furthermore, the contents of the destination processor information writing area 4b are examined to determine whether there is a pattern that matches the self (step 5T71). Next, the processor 2 examines the contents of the data state writing area 4a to check whether there is a pattern with data, and if there is no pattern with data or if there is no pattern that matches itself in step 5T71, , area 4A is advanced, and the process of step 5T71 is repeated until the entire area 4A is examined (step 5T73). If data is being received in step 5T72, processor 2 receives the contents of communication data writing area 4c and executes processing based on the contents (step 5T74). Subsequently, the processor 2 writes a pattern 10 of no data in the data state write area 4a.
01 is written (step 5T75).

FIG. 5 shows a multiprocessor system illustrating another embodiment of the present invention. This differs from the one shown in FIG. , each interrupt signal 12.21, [3,31,
Interrupt signal selection circuit 14 that selects signals 23 and 32, respectively.
, 15.16, 17.18.19.

FIG. 6 is a diagram 70 showing an inter-processor communication system according to this embodiment. According to this, steps 5T81 to 5T86 in the transmission side processing from processor 1 to processor 2 are similar to steps STI to ST6 shown in FIG. In this case, in step 5T86, processor 1 generates an interrupt to processor 2 using interrupt signal 12, notifies processor 2 of the communication request, and returns to step 5T81.

Next, in the interrupt processing of processor 2, first, the processor?
2 is interrupt notification 72g INT interrupt reception pattern l FF
1 is written (step 5T91), the interrupt signal selection circuit 14.16 for other processors is turned off to disable interrupts (step 5T92), and the interrupt processing is terminated.

On the other hand, in the reception process of the processor 2, the interrupt notification flag I
Check the contents of NT to determine whether interrupt reception pattern 1 FF 1 exists (Step 5TIOI), and if it exists, clear the count value (Step 5T102).
. Next, the processor 2 examines the area 4A in the shared memory 4 in order from the beginning, and then the processor 2 of the other party
, and determines whether a pattern 1B1 that matches the self is written (step 5T103).

As a result of this determination, if it has been written, the contents of the data status writing area 4a are examined to determine whether there is a pattern with data (step 5T104); if there is no pattern with data, or step 5T103
If pattern IB- is not written in step 5T108. Next, if it is determined in step ST104 that there is data, the count value I is incremented (step 5T105), and predetermined data processing is performed based on the contents of the communication data writing area 4c (step 5T106). In addition, the processor 2 also writes data state write area 4aK dataless pattern Woo.
1 is written (step 5T107), the area 4A is advanced, the entire area 4A of the shared memory 4 is examined, and the processing from step 5T103 onward is repeatedly executed (step 5T108). In this way, the value of the count value ■ is checked, and if it is not 0, the processing from step 5T102 onward is repeated (step 5T109). Subsequently, if the count value is 0, the contents of the interrupt communication flag INT are checked, and if the interrupt reception pattern II FF l is not stored, the processes from step 5TIOI are repeated (step 5T110), The interrupt completion pattern room is stored in the interrupt notification flag INT (Stella 7'5T111). And an interrupt signal selection circuit 14.1 for other processors.
6 to enable interrupts (step 5T112
).

Although the above embodiment shows an example of transmission from processor 1 to processor 2, transmission from processor 3 to processor 2, for example, can be executed in the same manner.

Further, in the above embodiment, a case has been described in which three processors 1, 2, and 3 are provided, but four or more processors may be provided, and the same effects as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, the shared memory is divided into a plurality of areas for communication between processors of a plurality of processors, and each time a transmission occurs, the transmitting processor searches for the area with no data, and Since the configuration is configured to store data presence information, information on the other processor, and communication data, and notify the other processor, even when the number of processors increases, the overhead of inter-processor communication can be reduced. Memory size of shared memory x 7
' Even if the number of processors increases, there is an effect that the shared memory does not need to be increased compared to the number of processors.

[Brief explanation of the drawing]

FIG. 1 is a block connection diagram of a multiprocessor system showing an inter-processor communication system using a shared memory according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the configuration of a shared memory according to an embodiment of the present invention, and FIG. FIG. 4 is a flowchart showing a processing procedure for an inter-processor communication method using a shared memory according to an embodiment of the present invention, and FIG. 4 is a flowchart showing a processing procedure for an inter-processor communication method using a shared memory according to another embodiment of the invention. , FIG. 5 is a block connection diagram showing a multiprocessor system showing an inter-processor communication method using a shared memory according to another embodiment of the present invention, and FIG. 6 is a flowchart showing the processing procedure of the inter-processor communication method shown in FIG. 7 is a block connection diagram showing a multiprocessor system showing a conventional inter-processor communication method using a shared memory, and FIG. 8 is a flow diagram showing a processing procedure of the conventional inter-processor communication method using a shared memory. 1.2.3 is a processor, 4 is a shared memory, Sr2 is a pattern writing step during data writing, Sr1 is a destination processor writing step, Sr1 is a data writing step, Sr5 is a writing step with data, Sr6 is an interrupt generation step, Sr1 is return step, 5TII
5T12 is a content matching determination step, 5T12 is a data presence/absence determination step, 5T13 is an entire area determination step, and 5T15 is a data-free pattern writing step. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In an inter-processor communication method in which a shared memory is commonly used by multiple processors to mutually communicate data, when a transmitting processor starts transmission, it searches for an area with no data in the shared memory and stores data in this area. A data writing pattern write step in which the pattern that is currently being written is written in the data status area of the destination device, and following this writing step, a pattern indicating this destination processor is written in the destination processor information write area in the above area. a processor write step, a data write step of writing the above data to be sent to the communication data write area of the above area, a data presence write step of writing a pattern with data in the data status area of the above area, and the above processor on the sending side. an interrupt generation step in which an interrupt is generated to request communication from the target processor, and the target processor examines the area of the shared memory in order from the beginning, and determines that the contents of the information write area of each target processor are the same as its own. a content match determination step for determining whether or not there is a match; a data presence/absence determination step for the destination processor to examine the contents of the data status area and determine whether or not there is data; If the content does not match the self or the above data does not exist, the next area is sequentially checked and the interrupt is terminated after this is carried out for all areas. A no-data pattern write step that writes a no-data pattern to the status area and ends interrupt processing, and when the no-data pattern is detected to be written to the data status area, the sending processor indicates the completion of communication. and a return step of making a determination and returning to the pattern writing step.