JPH02207619A - A/D conversion device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an A/D conversion device, and particularly to a high-resolution A/D conversion device.
This invention relates to a conversion device.

2. Description of the Related Art In recent years, with the spread of digital equipment, the performance of an A/D converter, which is an interface between analog and digital signals, has become important and greatly influenced. An example of a conventionally used A/D conversion device is shown in FIG. 5, and will be explained. The A/D conversion device shown in FIG. 5 is called a successive approximation type and operates as follows.

■Set the MSB (most significant bit) of the successive approximation register 102 at 1 +s and others to “O”, and set this to D/
It outputs to an A converter (hereinafter referred to as DAC) 103.

■The comparator 100 compares the input and the output of the DAC 103,
If (input) ≧ (DAC output), set “1pa” to the next lower bit, and if (input) < (DAC output), set the bit in question to “0” and set the next lower bit to “0”. is set to “1”.

■Repeat steps 1 and 2 from MSB to LSB (least significant bit).

(2) Take out data from the successive approximation register 102 and make it a digital output.

Problems to be Solved by the Invention However, in the above configuration, when the number of bits is increased to improve the resolution, the conversion time increases, so the comparator 100 and the DAC 1 are required to maintain the operating frequency.
03 is required to operate at very high speed. Moreover, the closer you get to the lower bit LSB, the less resolution you can get.
There have been problems in that the SN ratio deteriorates and it becomes more susceptible to the influence of surrounding noise. The present invention has been made in view of the above problems.
It is an object of the present invention to provide an A/D conversion device that is less affected by peripheral noise and does not require speeding up of elements used due to an increase in bits.

Means for Solving the Problems In order to solve the above-mentioned problems, an A/D converter according to the present invention includes a plurality of A/D converters that convert analog signals into digital signals, and a plurality of A/D converters that convert analog input signals into digital signals with different levels. a plurality of level converting means for converting the signal into a signal and inputting the signal to the plurality of A/D converters, respectively;
/D converter output as an input, ratio detection means for determining a ratio between the reference input and another input using one of the inputs as a reference input, and adjusting the level of the other input according to the ratio. a level adjustment device for selecting and outputting one of the output of the level adjustment device and the reference input; and selection means for selecting and outputting one of the outputs of the plurality of A/D converters, selection control means for switching immediately when the level exceeds a predetermined value, detecting the vicinity of zero cross of the plurality of inputs when the level of the plurality of inputs becomes below a predetermined level, and switching at the vicinity of the zero cross; The output is made into an A/D conversion output.

Function As mentioned above, dedicated A/D converters are provided for high input level and low input level, and low input level is level-amplified and then A/D converted to increase the resolution, and the resolution of each digital output is increased. Since it is switched digitally depending on the barking state, it is less susceptible to the influence of surrounding noise.Also, since it is switched digitally, it is not affected by the noise associated with switching, making it possible to use a high-resolution A/D converter. can be realized using a low-resolution A/D converter, and the operating speed of the elements used can be the same as conventional ones. Furthermore, because the signal is switched immediately when the waveform level increases, and when the waveform level decreases, it is switched near the zero cross, so switching within one waveform cycle does not occur, and waveform discontinuity occurs due to waveform switching. There is almost no impact.

Example The present invention will be explained below based on the drawings.

FIG. 1 is a block diagram schematically showing an A/D conversion device according to the present invention. To explain this figure, 1 is an amplifier that amplifies analog input. Here, one with a gain of about 24 dB is used. 2 and 3 are A/Ds with almost the same characteristics.
A converter (hereinafter referred to as ADC) converts an analog signal into a digital signal. Here, one with 18-bit resolution is used. Although an offset normally occurs in an A/D converter, it is assumed here that the offset level is zero or has been removed.

A multiplier 5 multiplies each 16-bit data applied to inputs X and Y, rounds off the least significant bit of the upper 21 bits of the multiplication result, and outputs the upper 20 bits. 6 is a level detector which outputs "1" when the absolute value of the ADC2 output exceeds a certain value. Here, when the input exceeds ±31744, "1" is output.

7 is a ratio detector, which monitors the level detector 6 and detects when the output of ADC2 is within ±31744;
The data output from 3 is compared, the ratio is calculated, and the result is output as 16-bit data. 8 is a selector, and if the control signal given to terminal C is "1", terminal A
If the control signal applied to terminal C is "0", the signal applied to terminal B is output.

Terminal A is a 20-bit input, but terminal B is a 16-bit input, and when outputting data given to terminal B, the sign bit of that data is added to the upper 4 bits, making it a 20-bit output. There is. A selector control circuit 9 controls the selector 8 based on the output of the level detector 6.

11 is a low pass filter (hereinafter referred to as LPF) that connects the ADC
Bandwidth limitation of the signals input to 2 and 3 is performed.

Next, the operation shown in FIG. 1 will be explained. The analog input band-limited by LPFII is directly connected to ADC3;
is amplified by 24 dB by amplifier 1.

Since the characteristics of ADCs 2 and 3 are almost the same, ADC 2 outputs a value approximately 16 times that of ADC 3. However, when a high amplitude analog input is given, ADC2 overflows L, and only ADC3 operates normally. When the level detector 6 detects that the ADC 2 is not overflowing, the ratio detector 7 accurately determines the ratio of the outputs of the ADCs 2 and 3 at this time.

Here, the method of calculating the ratio by the ratio detector 7 is as follows.
You can also find the quotient by dividing the output value of ADC2 by the output value of ADC3, but for example, if the output of ADC3 is "00000"
10000000000" may be stored. Since the value obtained by the ratio detector 7 is multiplied by the output value of the ADC 3 using the multiplier 5, the multiplier 5 The output of is the same value as the output of ADC 2. The output of multiplier 5 and the output of ADC 2 are switched using selector 8 based on the output of selector control circuit 9. Here, the operation of selector control circuit 9 will be explained. explain in detail.

FIG. 2 is a block diagram showing a specific example of the selector control circuit 9 in FIG. 1. To explain this diagram, 20 is D
The flip-flop 21 is a D flip-flop with reset. A clock signal CLK is applied to the D flip-flop 20, and here a 100 kHz clock signal is used. 22 is exclusive OR (hereinafter FO
(referred to as R gate).

Next, the operation shown in FIG. 2 will be explained in conjunction with FIGS. 1 and 3. A terminal C of the selector control circuit 9 is given the most significant bit (hereinafter referred to as MSB) of the output of the ADC 2. D
This signal is delayed by flip-flop 20 and applied to the other input of OR gate 22. For this reason E
The output of the OR gate 22 outputs a pulse signal every time the MSB of the ADC 2 output is inverted. Here, the MSB of the ADC2 output matches the sign of the ADC2 output, and the inversion of the sign naturally occurs near zero. In other words, the EOR gate 22 generates a pulse signal every time the ADC 2 output passes near zero. On the other hand, when the output of the ADC2 becomes smaller than the threshold value V'v, the level detector 6
The output of is converted from "'1" to "0" (Figure 3 (B)
time tlI). The output of the level detector 6 is given to the reset terminal R of the D flip-flop 21 via the terminal A, and since the reset is released, the EOR gate 22
The output terminal of the D flip-flop 21 is inverted from "1°" to "O" near the zero cross of the ADC2 output (time 1+ in FIG. 3(C)).

Next, when a signal with a level greater than the threshold VT is input to the level detector 6, the output of the level detector 6 immediately becomes "
1" (time t2 in FIG. 3(B)), the D flip-flop 21 is reset, and the Q output immediately becomes "1°".
(time t2 in FIG. 3(C)). This signal is given to the selector 8, and when the signal amplitude of the input analog signal is large, the selector 8 directly performs A/D conversion and outputs it, and when the signal amplitude of the analog signal becomes small, the selector 8 converts it into an analog signal. A zero cross is detected in the output of the ADC 2 which amplifies the signal amplitude and performs A/D conversion, and the output is output from this point onwards.

Thereafter, similar operations are performed from time t4 to time t7.

FIG. 4 shows another embodiment of the selector control circuit 9. In this embodiment, the selector control circuit 9 has the ADC 2 as an input.
The upper 12 bits of the output are taken in. 80 is an all-0 detector, and when all input signals are "0", "
For example, a 12-input NOR gate corresponds to this. 31 is an all-1 detector that outputs "1" when all input signals are "1"; for example, a 12-input NOR gate. This corresponds to the AND gate.

32 is an OR gate. To explain this diagram, ADC
The upper 12 bits of 2 outputs are all “1’° or “0”
When , the OR gate 32 outputs "1". This allows A
When the DC2 output is between -16 and +15, that is, when the ADC2 output is close to zero, the OR gate 32 outputs "1". The output of the OR gate 32 is applied to the D flip-flop 21, and a control signal is generated in the same manner as in the case of FIG.

In FIG. 4, the control signal is inverted even if the ADC2 output does not necessarily cross zero, but conversely, even if it crosses zero, it will not be inverted unless the value at that time is in the range of -16 to +15.
The inversion operation is performed after waiting until such a signal appears. In other words, switching by the selector 8 is performed reliably when the input level of the analog signal is a small value.

By performing the switching operation using the selector 8 as described above, when the signal amplitude is large, the switching is not performed in one cycle in a complicated manner, and there are fewer problems such as waveform discontinuity due to switching at zero crossing. Since the switching is performed in the vicinity, it is possible to suppress the occurrence of distortion during switching, and it is possible to perform A/D conversion with high resolution regardless of the magnitude of the signal amplitude of the analog input.

In addition, since it is usually easy to obtain a high-performance analog amplifier 1, by configuring it in this way, the gain of the amplifier 1 does not become a problem.
Further, even if the sensitivities of the ADCs 2 and 3 are not the same, a stable A/D converter with high bits and high resolution can be obtained. Further, it is not necessarily necessary to use a high-resolution A/D converter, and the operating speed may be the same as conventional ones.

Also, the number of bits of the output of the A/D converter is determined by the gain of amplifier 1, so the number of output bits can be changed by changing the gain of amplifier 1 as necessary. I can do it. Additionally, since all output switching is done digitally, there is no noise or click noise associated with this.

In the above embodiment, the analog input is amplified and input to ADC2, but the signal is directly input to ADC2, and the signal attenuated using an attenuator is input to ADC3. It's fine to do it this way.

Further, although two A/D converters are used in the above embodiment, three or more A/D converters may be used, and analog inputs of different levels may be applied to each A/D converter.

Effects of the Invention As described above, the present invention includes a plurality of A/D converters that convert an analog signal into a digital signal, and a plurality of A/D converters that convert an analog input signal into a plurality of signals with different levels. A plurality of level conversion means each input to a converter and outputs of the plurality of A/D converters are input, and one of the inputs is used as a reference input to calculate a ratio between the reference input and other inputs. a ratio detection means, a level adjustment device that adjusts the level of the other input according to the ratio, a selection device that selects and outputs one of the output of the level adjustment device and the reference input; When the level of the plurality of inputs exceeds a predetermined value based on the level of the output of the plurality of A/D converters, switching is immediately performed, and when the level of the plurality of inputs falls below a predetermined level, the signal is switched around the zero cross of the plurality of inputs. selection control means for detecting and switching near the zero cross, and by making the output of the selection means an A/D conversion output, when the analog signal level is small, the A/D conversion is performed after amplifying it to a large amplitude analog signal.
Since D conversion can be performed, the resolution can be kept high and it can be made less susceptible to the influence of surrounding noise. In addition, since the switching is performed digitally, a high-resolution A/D converter can be realized using a low-resolution A/D converter without being affected by noise associated with switching. The operating speed can be kept the same as before. Moreover, since the signal is switched immediately when the waveform level increases and near zero cross when the waveform level decreases, there is almost no effect of waveform discontinuity associated with the switching location.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an A/D conversion device according to the present invention, and FIG. 2 is a selector control circuit 9 in FIG. 1.
3 is a waveform diagram for explaining the operation of the A/D converter according to the present invention, and FIG. 4 is a detailed diagram of the selector control circuit 9.
FIG. 5 is a block diagram showing a conventional A/D converter. 1... Amplifier, 2, 3... A/D converter, 5...
Multiplier, 6...Level detector, 7...Ratio detector, 8...Selector, 9...Selector control circuit, 11...Name of low-pass filter agent Patent attorney Weight Awano et al. 1 person's figure tEE? "Q\"-nl

Claims (1)

[Claims] (1) A plurality of A/D converters that convert an analog signal into a digital signal, and a plurality of A/D converters that convert the analog input signal into a plurality of signals with different levels and input them to the plurality of A/D converters, respectively. level converting means, a ratio detecting means which takes the outputs of the plurality of A/D converters as an input, uses one input among the inputs as a reference input, and calculates a ratio between the reference input and another input; a level adjustment device that adjusts the level of the other input according to the level adjustment device; a selection device that selects and outputs one of the output of the level adjustment device and the reference input; and the selection device is connected to the plurality of A/D converters. Based on the level of the output, when the level of the plurality of inputs exceeds a predetermined value, switching is immediately performed, and when the level of the plurality of inputs becomes below a predetermined level, the vicinity of zero crossing of the plurality of inputs is detected, and switching is performed near the zero crossing. An A/D conversion device comprising a selection control means, and an output of the selection means is an A/D conversion output.