JPH02208765A - Input/output controller - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a host computer and a plurality of input/output devices (hereinafter referred to as
(abbreviated as Ilo)).

[Prior Art] A conventional device of this type is shown in FIG. FIG. 2 is a block diagram showing the configuration of a conventional input/output control device of this type. In the figure, (2) is a connection mechanism, which constitutes an interface with a host computer (not shown). (3a) are I/O control mechanisms, (4a) are ROMs for storing microprograms built into the I/O control mechanisms (3a), and (5) are engineering/Os (not shown). ), (6) shows a control signal, and (7) shows a data signal.

Figure 2 shows an example in which five I/O control mechanisms (3a) are installed, and each I/O control mechanism (3a) is connected to a connection mechanism (2
), it sends and receives control signals and data signals to and from the host computer, and each controls Ilo connected via an interface cable (5).

Next, the operation will be explained. Each I/O control mechanism (3a)
Each has a built-in ROM (4a) that stores a control microprogram, and when the input/output control device is powered on, each I/O control mechanism (3a)
reads each microprogram and becomes operational according to this microprogram. When each I/O control mechanism (3a) becomes operational, it becomes possible to send and receive control signals (6) and data signals (7) to and from the host computer via the connection mechanism (2). It becomes possible to input and output various data to /O, and to display data from Ilo on the host computer.

[Problems to be Solved by the Invention] Since the conventional input/output control device as described above is configured as described above, when changing the microprogram of the I/O control mechanism, each microprogram must be changed. This may require changes, and may cause confusion in terms of maintenance such as sub-number management. Furthermore, there is a problem that the processing speed is limited due to the slow reading speed of the ROM.

The operation of loading a microprogram from an external storage device storing it to a RAM on the main storage device by initial program loading is described, for example, in Japanese Patent Laid-Open No. 62-25.
As disclosed in Publication No. 353, "Microprogram loading method," this has been widely used in the past, but the I/O control mechanism for controlling Ilo includes each IO control mechanism as described above. Since each mechanism has a built-in ROM, there are problems as described above.

This invention was made to solve such problems, and it is possible to maintain and change microprograms all at once, regardless of the number of I/O control mechanisms installed, and to provide input/output with high processing speed. The purpose is to obtain a control device.

[Problems to be Solved by the Invention] The input/output control device according to the present invention includes, in addition to the I/O control mechanism, a storage mechanism having a ROM that stores a microprogram for operating the I/O control mechanism. It was decided to incorporate RAM into the I/O control mechanism.

[Function] In this invention, a storage mechanism is provided, and each I/O control mechanism has a built-in RAM, and when the power is turned on, this R
Since we decided to load the microprograms into the AM, the programs that run each I/O control mechanism are stored in one R.
It becomes possible to store it in OM.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1st
The figure is a block diagram showing one embodiment of the present invention, where the same reference numerals as in Fig. 2 indicate the same or corresponding parts, (1) is a storage mechanism, and (3) is an I/O control mechanism in this embodiment. , (4) are RAMs built into the I/O control mechanism (3), (11) is a counter, (12) is an address generator, and <13) is an EPROM (erasable
programmable ROM), and the storage mechanism (1) includes a counter (11) and an address generator (
12) and E F ROM (13).

Next, the operation will be explained. When the power is turned on to the input/output control device, the counter (11) in the storage mechanism (1) operates, and after a sufficient setup time, the address predetermined by the address generator (12) is set to E P
Sent to ROM (13), EPROM (13)
The microprograms stored in the shared bus are sequentially sent out onto the shared bus.

Each I/O control mechanism sequentially stores the contents of the sent microprogram in its own RAM (4), and when all I/O control mechanisms (3) have finished storing the microprogram, Finish loading. Next, each I/
The O control mechanism (3) sequentially reads and executes the loaded microprograms and becomes operational.

When each I/O control mechanism (3) becomes operational, it becomes possible to send and receive control signals (6) and data signals (7) to and from the host computer via the connection mechanism (2).
You can input and output various data to and from Ilo.
In the above embodiment, an EPROM is used as a storage mechanism to store the microprogram. This is to facilitate rewriting when there is a change in the other F.
A ROM may be used, and other ROMs may be used if rewriting is not required.

Further, the RAM built into the I/O control mechanism may be either static RAM or dynamic RAM.

[Effects of the Invention] As explained above, this invention provides a storage mechanism, stores a microprogram in this storage mechanism, and loads it into the RAM provided in each I/O control mechanism when the power is turned on. , microprograms can be maintained and changed all at once regardless of the number of I/O control mechanisms installed, which has the effect of improving device reliability and increasing processing speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional device. (1) is a storage mechanism, (2) is a connection mechanism, (3) is an I/O control mechanism, (4) is a RAM, (5) is an interface cable, (6) is a control signal,
(7) is a data signal, (11) is a counter, (12) is an address generator, and (13) is an EPROM. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] An input/output device that is connected between a host computer and each input/output device (hereinafter referred to as I/O), and has a plurality of I/O control mechanisms that read programs themselves and operate according to these programs. In the control device, the RO that stores the above program
M and this program to the above multiple I/Os when starting the device.
An input/output control device comprising: a storage mechanism having means for transferring to an O control mechanism; and a RAM built in each of the plurality of I/O control mechanisms for storing the transferred program. .