JPH02209014A - Synchronous circuit - Google Patents

Abstract

PURPOSE:To reduce jitter of a frequency division synchronous output and to improve the accuracy by frequency-dividing an intermediate frequency division output of a digital PLL circuit having a frequency being a multiple of the reciprocal of an integer of a 2nd desired frequency into a frequency being one over an integral number of the 2nd desired frequency, obtaining a reset pulse and giving it to a main frequency divider means. CONSTITUTION:An intermediate frequency division output of a digital PLL circuit 10a is used, it is supplied to a reset output frequency divider circuit 20, in which the frequency is frequency-divided into a reciprocal of an integer times a 2nd desired frequency to form a reset pulse 4. Then a main frequency divider circuit 30 is reset by a reset pulse having a frequency being a multiple of one over an integral number of the 2nd desired frequency generated from the reset output frequency divider circuit 20. Thus, an output of the main frequency divider circuit is synchronized with an output of the digital PLL circuit 10a. Since a reset signal of the main frequency dividing circuit is obtained from the reset output frequency divider circuit receiving an intermediate frequency division output of the digital PLL circuit and frequency-dividing the output by a desired value, jitter is considerably reduced different from a conventional system reset at a period over a several number of multiple.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention has a digital PLL circuit that is synchronized to an input frequency K, and is capable of generating a synchronization signal whose frequency is -(K-≠). This invention relates to a synchronous circuit with low jitter.

(Prior Art) It is often necessary to divide a reference signal of a certain oscillation frequency (hereinafter referred to as the original oscillation) by a desired frequency division ratio to obtain a frequency-divided signal synchronized with the original oscillation. Particularly in the fields of communication and control, such synchronization signals are required to prevent synchronization and maintain accuracy.

By the way, right now, from Genshin [t, 144 M) Iz 8
K! The corresponding 8 of the digital PLL (needs-locked loop) circuit with a frequency division ratio of 1/(24X3) to obtain Iz
Consider a synchronous circuit that generates a 311.4 H)z synchronous output signal synchronized with the K11z output.

To convert the original oscillation from 6.144 Mllz to 38.4 K11z, it is sufficient to divide the frequency by 1/(25
8.4 In the case of a circuit that generates a K11z synchronous output signal, as shown in Figure 3, conventionally the original oscillation B, 144 MHz
8K of the digital PLL circuit 10 whose input signal 1 is
Pass the Hz output through the first frequency divider circuit 20 that divides the frequency by 115 to create a set pulse 4 of 1.8 2' K5) The second frequency dividing circuit 30 that divides the frequency is reset, so that the output clock from the second frequency dividing circuit 30 is 38.4 KHz, which is intended to be synchronized with the 8 kllz output of the PLL circuit IO. I was trying to get it as a 5.

However, if the digital PLL circuit 10 described above performs control to increase or decrease the original oscillation by 8.144 MHz-period every 8 kHz, which is its own output clock 3, depending on the error at that time, the first component The circuit 20 is a digital P
Since the 8 kHz output from the LL circuit 10 is divided by 115, the output will have an increase/decrease of up to 5 cycles of 8.144 M)Iz, and the second frequency will be set as the reset input. There is a problem in that the output of the circulation circuit 30 has an increase/decrease (jedder) of a maximum of 5 cycles of 6.144M1lz.

(Problems to be Solved by the Invention) When using a digital PLL circuit as described above and obtaining a desired frequency-divided output synchronized with its output, in the conventional configuration, the pulse that synchronizes the output frequency is a digital PLL circuit.
Since the output of the LL circuit is further divided into frequencies, synchronization with the target output frequency is only once every few cycles compared to the synchronization of the output of the digital PLL circuit, so distortion at reset is large and jitter becomes large. There was a problem.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a synchronization circuit that can reduce jitter and obtain highly accurate frequency-divided synchronization output.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve the above object, the present invention is configured as follows. That is, a digital PLL circuit that divides a desired original frequency to obtain a signal of a desired frequency is used to divide the original frequency and output a second desired frequency that is synchronized with the output of the digital PLL circuit. In the synchronous circuit, the intermediate frequency division output of the digital PLL circuit, which has a frequency that is a multiple of an integer of the second desired frequency, is divided into an integer of the second desired frequency. A reset output frequency dividing means is provided to obtain a reset pulse and supply it to the main frequency dividing means.

(Function) In this device having such a configuration, the main frequency dividing means divides the original frequency to obtain an output of a second desired frequency synchronized with the output of the digital PLL circuit. To synchronize with the output of the circuit, a reset signal is generated based on the output of the digital PLL circuit to reset the main frequency divider circuit. This reset signal uses an intermediate frequency-divided output of the digital PLL circuit having a frequency that is a multiple of an integer fraction of the second desired frequency, in order to generate a reset pulse that is an integer fraction of the second desired frequency. , this is applied to the reset output frequency dividing means, and the frequency is divided by an integer fraction of the second desired frequency, thereby producing a reset pulse. Since the main frequency dividing means is reset by a reset pulse of an integer fraction of the second desired frequency generated by the reset output frequency dividing means, the output of the main frequency dividing means is the output of the digital PLL circuit. Moreover, the reset of the main frequency dividing means is obtained by the reset output frequency dividing means which obtains the intermediate frequency divided output of the digital PLL circuit and divides it into a desired frequency.
Since the reset is performed within the correction period of the LL circuit, it is possible to significantly reduce jitter, unlike the conventional method, which resets at a period several times or more than the correction period.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings. In addition, here, in order to compare with the conventional example, the original vibration 6.1
Frequency division ratio 1/ (to obtain 8 K11z from 44 MHz
Consider a synchronous circuit that generates a synchronous output signal of 38.4 Hz in synchronization with the 8 kHz output of a digital PLL (phase-locked loop) circuit of 24K3). This device does not frequency-divide the final output of the digital PLL circuit to generate the reset signal, but uses the intermediate output of the digital PLL circuit and divides it in a frequency dividing circuit to generate the reset pulse. The above problem is solved by generating this. For example, in the case of the prior art example, 1/(2
5X3) Divide the frequency by 175 and get 12.8
Create a kHz pulse and reset the 1/(25X5) frequency divider circuit.

I will explain in detail. Fig. 1 is a block diagram showing a configuration example of the present invention. Input signal 2
It outputs an 8 kllz clock 3 synchronized with the 8 kllz clock 3. This 8ktlz clock 3 output is 8kllzl
This becomes the l-type force signal 2.

In addition, 20 is a first frequency divider that divides the intermediate clock 6 of the 1/(24×3) frequency division, which is an intermediate output of the digital PLL circuit 10a, by 115 and outputs the reset pulse 4 of 12.8 kHz. The circuit, 30, converts the original oscillation by 1/
This is a second frequency divider circuit that divides the frequency by (25×5) and generates the target output clock 5, and this second frequency divider circuit 30 is reset by the reset pulse 4 output from the first frequency divider circuit 20. This is the configuration.

FIG. 2 is a block diagram showing a schematic configuration of the digital PLL circuit 10a, in which 11 is a PLL control circuit;
2 and 13 are frequency dividing circuits. The frequency dividing circuits 12 and 13 are used to perform frequency division to obtain 8 kllz from the original oscillation B, 144 Mllz. Here, for convenience, the frequency dividing circuit 12 is the upper frequency dividing stage, and the frequency dividing circuit 13 is the lower frequency dividing stage. The output of the frequency dividing circuit 12 is the original oscillation B, which is the input signal 1, 144M1
This is a dividing stage in the middle of dividing lz by 1/ (28x3).
This frequency divider circuit 13 of the lower frequency division stage is designed to obtain an output of 64 kHz (intermediate clock 6), which is twice as high as that of the frequency divider circuit 12.
The output clock 3 of 8 kHz is generated by dividing the frequency of the output by 8. The PLL control circuit 11 controls these frequency dividing circuits 12 and 13 to increase or decrease by one cycle every 8 kHz according to the error.

Next, the operation of this device having the above configuration will be explained. In such a configuration, the digital PLL circuit 10a operates in synchronization with the synchronous input signal 2 of 8 kllz, which is the feedback of the output clock 3, and the input original oscillation 8.144
The clock 3 of 8 kllz is generated from Mllz, but since the PLL circuit 10a is composed of a digital circuit, as shown in FIG.
1/(25x3) frequency division stage (frequency division circuit 1)
2), an 84 kHz intermediate clock 6 can be extracted.

The first frequency dividing circuit 20 which divides the frequency by 115 has its 84 kll
Divide the intermediate clock 6 of z by 115 to get 12.8 kll
z reset pulse 4 is output. And 1/(25
X5) The second frequency dividing circuit 30 that divides the frequency has an original frequency of 8.144
A clock signal 5 of 38.4 kHz is generated from an input signal 1 of MHz, which is reset by the reset pulse 4 of 12.8 kHz and synchronized with the synchronous input signal 2 of 8 kHz.

Here, the digital PLL circuit 10a generates an original oscillation of 8.144 Mll every 8 kllz, which is the frequency of the synchronization input signal 2.
z If it increases or decreases by one period, (i4
The same applies to the clock 6 of kllz. Therefore, that f
34kl! 12 obtained by dividing the clock 6 of z by 115
．． The reset pulse 4 of 8 kllz is also the original frequency 6.144 old at a rate of about 8 kllz! There is an increase/decrease of 21 cycles.

The second frequency divider circuit 30, which generates 38.4 kllz from the original oscillation 6.144 Mllz, receives the reset pulse 4 of 12.8 kllz, which is the output of the first frequency divider circuit 20, and is reset. , this second frequency dividing circuit 30
The output of 38.4 kllz is also the original oscillation [i, 144 M!] at a rate of about 8 kllz. There is an increase/decrease of lz-period. Therefore, in the above example, the output width is reduced to 1 compared to the conventional one.
This can be reduced to 15.

In this way, the present invention uses a digital PLL circuit that divides a desired original frequency to obtain a signal of a desired frequency, and divides the original frequency to generate a second signal synchronized with the output of the digital PLL circuit. In a synchronous circuit having a main frequency dividing means for obtaining an output of a desired frequency, 1. In order to obtain a reset pulse of an integer fraction of the second desired frequency, a reset output frequency dividing means is used to obtain an intermediate frequency divided output of the digital PLL circuit and divide it into a desired frequency. Since the reset output frequency dividing means generates a reset pulse of an integer fraction of the second desired frequency to reset the main frequency dividing means, the output of the main frequency dividing means is It can be synchronized with the output of the digital PLL circuit, and the reset of the main frequency division means is obtained by obtaining the intermediate frequency division output of the digital PLL circuit and dividing it into a desired frequency by the reset output frequency division means. Therefore, since the reset is performed within the correction period of the digital PLL circuit, jitter can be significantly reduced, unlike the conventional method in which the reset is performed at a period several times or more than the correction period.

It should be noted that the present invention is not limited to the embodiments described above and shown in the drawings, and can be implemented with appropriate modifications within the scope without changing the gist thereof.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a synchronous circuit that can significantly reduce the output shifter width.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a pb road section, and FIG. 3 is a block diagram explaining a conventional example. 1... Input signal (original oscillation), 2... Synchronous input, 3...
- Output clock, 4... Reset pulse, 5... Output clock, 6... Intermediate clock, lOa... Digital PLL circuit, 12.13, 20.30... Frequency dividing circuit. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] A digital PLL circuit that divides a desired original frequency to obtain a signal of a desired frequency is used, and a second PLL circuit that divides the original frequency and synchronizes with the output of the digital PLL circuit. and a main frequency dividing means for obtaining an output at a desired frequency, wherein the intermediate frequency divided output of the digital PLL circuit, which has a frequency that is a multiple of an integer of the second desired frequency, is outputted from the second desired frequency.
1. A synchronous circuit comprising a reset output frequency dividing means which divides a desired frequency by an integer fraction, obtains a reset pulse, and supplies the reset pulse to the main frequency dividing means.