JPH02210396A - Automatic musical performance device of electronic musical instrument - Google Patents

Abstract

PURPOSE:To constitute this device so that a performer can write freely a musical tone in a storage device or can change it by designating an address of the storage device in accordance with an operation of an address stepping operating means, writing musical tone information and reading it out successively and generating automatically the musical tone. CONSTITUTION:An input device 11 executes an input operation of musical tone informa tion for an automatic musical performance, a storage device 9 has many addresses, and an address stepping operating means 4 executes an address stepping operation in the direction of one of the address value increase direction or the address value decrease direction with regard to the storage device 9. An address designating means 7 designates an address of the storage device 9 in accordance with an operation of the address stepping operating means 4, and a writing means 5 writes musical tone information consisting of sound pitch information and time information corresponding to an operation of the input device 11 in an address designated by the address designat ing means 7. A musical tone generating means 10 generates automatically a musical tone by reading out successively the musical tone information written in the storage device 9. In such a way, a performer can write freely a musical tone in the storage device or can change it.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic performance device for an electronic musical instrument.

(Description of Prior Art) A conventional automatic performance device for an electronic musical instrument is disclosed in, for example, U.S. Pat.
, No. 890.871, the musical tones played by a player on a keyboard are encoded and stored as they are, and are reproduced for automatic performance. Therefore, conventional automatic performance devices for electronic musical instruments merely have a function similar to that of a tape recorder, and lack the ability for the performer to freely compose and arrange music. Even if you want to arrange part of the song,
With conventional automatic performance devices for electronic musical instruments, the performer had to replay the song from the beginning on the electronic instrument and arrange part of it. Since musical tones cannot be stored in the device, the user cannot enjoy automatic performance of an electronic musical instrument at all.

(Objective and General Description of the Invention) The present invention has been made in view of the drawbacks of the conventional automatic performance devices for electronic musical instruments. An object of the present invention is to provide an automatic performance device for an electronic musical instrument having a function of freely changing musical tones in the middle of a musical tone.

An automatic performance device for an electronic musical instrument according to the present invention includes (a) an input operation means for inputting musical tone information for automatic performance; and (b) a memory having a large number of addresses and readable and writeable for each address. (c) address increment operation means for performing an address increment operation in either the address value increasing direction or address value decreasing direction with respect to this storage device; (d) the address increment operation means; (8) musical tone information consisting of pitch information and time information corresponding to the operation of the input operation means at the address specified by the address specification means; and (f) musical tone generating means that automatically generates musical tones by sequentially reading musical tone information written in the storage device.

According to the configuration of the present invention, address specification can be performed in two directions, so input information for a part of a song can be easily rewritten by returning the address. Furthermore, since an event method is used in which musical tone information consisting of pitch information and time information is written into the storage device, the storage device can be used efficiently.

(Description of Structure and Operation of the Present Invention) The present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 shows an embodiment of the present invention, in which the fixed contact of the start switch 1 is grounded, the movable contact is connected to the positive voltage source +■ via a resistor on one side, and the input side of the delay circuit 2 on the other side. and is connected to the reset terminal R of the address generator.

The address generator 7 is composed of a counting circuit such as a combination of a counter and a decoder or a shift register, and in addition to the above-mentioned reset terminal R, the address generator 7 performs an addition or subtraction operation on the count input terminal C and the address generator Tough. It has an up/down designation input terminal U/D for designating either one of them.

For example, the logical value "
When a logic value "1" is input, an addition operation is performed, and when a logic value "O" is input, a subtraction operation is performed.

The output side of the delay circuit 2 is connected to the first input terminal of the OR circuit 3. Manual operation, the address generator control device 4 manually controls the up/down designation switch S1 and the address generator 7 to output a logical value "1" or 0" to the up/down designation input terminal U/D of the address generator 7. It has a manually operated step switch S2 for stepping.Here, the output of the up/down designation switch S1 is configured to be output from an output terminal A1, and the output terminal A1 is an address generator. It is connected to the up/down designation input terminal U/D of the front panel.

The output and force of the manual operation step switch S2 is configured to be output from the output terminal A2.
It is connected to the fixed contact M of the automatic changeover switch 6. Here, the manually operated advance switch S2 is configured so that one pulse is output when it is turned on once.

The movable contact of the manual/automatic changeover switch 6 is connected to the second input terminal of the OR circuit 3, and the output side of the OR circuit 3 is connected to the counting input terminal C of the address generator turf.

The address signal output side of the address generator turf is connected to the address input side of the random access memory 9, and the write/read designation input terminal W/R of the random access memory 9 is connected to the movable contact of the write/read designation switch 8. ing. The fixed contact W (writing side) of the check writing/reading designation switch 8 has a logical value “1”.
is input, and the fixed contact R (readout side) has the logical value “0”.
” has been input. Here, when the random access memory 9 receives a logical value “1” to its write/read designation input terminal W/R, it enters a writable state, and a logical value “O” is input. It is configured so that it becomes readable when it is read.

The output side of the input device 11 is connected to the write input side of the random access memory 9, and this input device 11 inputs musical tone information to be stored at each address of the random access memory 9 according to the player's intention (player's switching It has a function to output according to the operation). The output musical tone information includes all the information required to determine one generated musical tone, and in this embodiment, the musical tone information is formed by the following information group and the generated musical tone is determined.

Therefore, the input device 11 is provided with a large number of switches that output these various types of information, and the performer operates these switches according to his/her will to write the musical tone information of the generated musical tone into the random access memory 9. I do.

The readout output of the random access memory 9 is connected on the one hand to the tone generator 10 and on the other hand to the input of the time-detecting automatic address generator control device 5 - here, the readout output of the random access memory 9 is connected to the tone forming device 10 and on the other hand to the input of the time-detecting automatic address generator control device 5; Of the musical tone information, only the time information is input to the detection automatic address generator control device 5, and what is input to the musical tone forming device 1O is the remaining scale information (octave information + note name information), rest information, and envelope control information.

The time detection automatic address generator control device 5 receives time information from the random access memory 9, accurately counts the specified time (musical sound generation time, musical sound generator stop time), and outputs only within that time. It is configured to output a time signal TS (logical value "1") from the terminal B2, and to generate one pulse from the output terminal B1 at the same time as the above-mentioned indicated time is counted. Here, output terminal B1 is manually operated.
It is connected to the fixed contact A of the automatic changeover switch 6, and its output terminal B2 is connected to the time signal input terminal T of the musical tone forming device 10.

The musical tone forming device 10 receives the scale information, rest information, envelope position information read out from the random access memory 9, and the time signal TS outputted from the output terminal B2 of the time detection automatic address generator control device 5. It has a function of generating musical tones determined by each piece of information and a time signal.

The operation of the embodiment of the present invention having the above configuration will be described next. For convenience of explanation, the explanation will be divided into a ``musical tone information writing operation'' for writing musical tone information into the random access memory 9 and a ``musical tone information reading operation J'' for reading musical tone information from the random access memory 9 and generating musical tones.

Sound information writing operation When the performer writes musical sound information into the random access memory 9, the write/read designation switch 8 is turned on to the fixed contact W side. This causes switch 8
Since the logical value "1'" is input to the write/read designation input terminal W/R of the random access memory 9 through the write/read designation input terminal W/R, the random access memory 9 becomes in a writable state. Next, set the manual/automatic changeover switch 6 to the fixed contact M.
and then set start switch 1 to close. As a result, the address generator 7 can be operated by the manually operated address generator control device 4.

Further, since the positive voltage +V applied to the reset terminal R of the address generator Tough is grounded via the start switch 1, the reset state of the address generator Tough is released. At the time when the reset state of the address generator 7 is released, the positive voltage +V is still applied to the counting input terminal C of the address generator 7 via the delay circuit 2 and the OR circuit 3. The voltage +■ is counted as a logical value "1" and outputted to the address input side of the random access memory 9 as the first address signal ADI. Eventually, due to the action of the delay circuit 2, the ground potential (logical value "0'
'') is input to the OR circuit 3, so the start switch 1 will not be involved in the subsequent operation.As is clear from the explanation above, the address generator 7 is set to the first position by turning on the start switch 1. Address signal A
DI is generated, and the first address (address 1) of the random access memory 9 becomes writable by this first address signal ADZ. In this state, the performer inputs the musical tone information (time information, scale information, etc.) of the first beat of the song to be played automatically to the first address of the random access memory 9 by operating various switches provided on the input device 11. Can be written.

Next, the performer uses the manually operated address generator control device 4.
The up-down designation switch S1 is in the up position (the output terminal A1 outputs a logical value of "1").

). As a result, the logic value "1" is applied to the up/down designation input terminal U/D of the address generator.
" is input, and it is confirmed that the address generator is in a state where it performs an addition operation. Next, the manually operated advance switch S2 of the manually operated address generator control device 4 is turned to 1.
Set immersive times. As a result, one pulse is generated from the output terminal A2 of the manually operated address generator control device 4, and this pulse is inputted to the counting input terminal C of the address generator via the manual/automatic changeover switch 6 and the OR circuit 3. . The address generator 7 counts these pulses and outputs the second address signal AD2 to the random access memory 9. Therefore, the second address (address 2) of the random access memory 9 becomes writable. Therefore, by operating various switches on the input device 11 in the same way as in the case described above, the performer selects the second address of the piece of music to be played at the second address in the random access memory 9.
Musical tone information for beats can be written. The subsequent writing operation is performed by repeating the ON setting of the manually operated advance switch S2 of the manually operated address generator 4 and the operation of various switches of the input device 11, just like the writing of the musical tone information of the second beat.

Furthermore, if the performer makes a mistake in operating the input device 11 and writes incorrect musical tone information into the random access memory 9, the mistakenly written musical tone information can be corrected by the following operation. First, the up/down designation switch S1 of the manually operated address generator control device 4
Set it to the down side. As a result, output terminal A
Since the logical value "0" is output from 1, the address generator 7 is in a state where subtraction is possible. Subsequently, the manually operated advance switch S2 is turned on until the address signal AD1 corresponding to the address to which the erroneous musical tone information has been written is generated from the address generator. By this operation, after specifying the address of the random access memory 9 where the incorrect musical tone information has been written, the input device 1
All you have to do is operate the various switches in step 1 to write the correct musical tone information.

Reading A Next, a case will be described in which musical tone information written in the random access memory 9 is read out by the musical tone information writing operation described above and automatic performance is performed.

The performer first sets the write/read designation switch 8 to the fixed contact R side. As a result, the write/read designation input terminal W of the random access memory 9
Since the logical value "0" is input to /R, the random access memory 9 becomes readable. Next, the manual/automatic changeover switch 6 is set to the fixed contact A. This allows the time-detected automatic address generator control device 5 to control the address generator tofu. Next, when the start switch 1 is turned on, the reset state of the address generator turf is released, just as in the case of the musical tone information writing operation described above, and the first address signal ADI is outputted from the address generator turf.

Therefore, the musical tone information of the first beat of the performance piece stored in the first address of the random access memory 9 is read out, and of this read musical tone information, only the time information is stored in the time detection automatic address generator control device 5. The remaining scale information, rest information, and envelope control information are input to the musical tone forming device 10.

The time detection automatic address generator control device 5 is this one.
Upon receiving the time information of the beat, it immediately starts counting the time specified by the time information, and at the same time outputs the time signal Tmi (logical value "1") from the output terminal B2.

The musical tone forming device 10 receives the scale information, rest information, and envelope control information output from the random access memory 9, as well as the time signal TS (logical value “1”) output from the time detection automatic address generator control device 5, and starts playing. Generation of the musical tone of the first beat of the song is started according to this information.

Eventually, the time detection automatic address generator control device 5
However, when counting the time defined by the time information read from the first address of the random access memory 9, one pulse is generated from the output terminal B1 and at the same time the output terminal B2 outputs the time signal TS (logical value). "1"') output is stopped.

As a result, the musical tone forming device 10 finishes generating the musical tone of the first beat of the performance piece. The pulses generated from the output terminal Bl are inputted to the counting input terminal C of the address generator via the manual/automatic changeover switch 6 and the OR circuit 3. The address generator 7 receives this pulse and outputs the second address (GS number AD2). Therefore, the musical tone information stored in the second address of the random access memory 9 is read out. The subsequent sound generation operation is performed in one beat. This is done in exactly the same way as the musical tone generation of the second beat, and the musical tone of the second beat is generated from the musical tone forming device 10. In this way, the address generator turf is driven one after another by the time detection and the function of the automatic address generator control device 5. Accordingly, the musical tone information is read out one after another from the random access memory 9, and musical tones are sequentially generated from the musical tone forming device 1O.

Although this embodiment has been described on the assumption that the logical value "1" is output as the time signal TS from the output terminal B2 of the time detection self-excited address generator control device 5, the present invention is not limited to this. For example, when the time detection automatic address generator control device 5 counts the time output by the random access memory 9, its output terminal B
2, one pulse may be generated as the time signal TS.

5. In this embodiment, the output of the input device 11 is input only to the random access memory 9. However, the output of the input device 11 is also input to the musical tone forming device 10, so that when musical tone information is written to the random access memory 9, a musical tone corresponding to the musical tone information is generated from the musical tone forming device io. You can also do it.

Next, a case where the present invention is applied to a synthesizer type electronic musical instrument will be explained using FIGS. 2 to 7. still,
In the drawings attached to this specification, AND circuits and OR circuits are shown with the symbols shown in FIGS. Indicates that it has been entered.

FIG. 3 is a detailed diagram of the input device 11 in FIG. 1,
Time information designation switches T1 to T5 corresponding to each note (sixteenth note, eighth note, etc.) and octave information designation switches 01 to 0 corresponding to each musical range, respectively.
5, pitch name information designation switches N1 to N12 corresponding to each pitch name CNB, and each rest (llil stock,
Rest information specification switch R corresponding to eighth rests, etc.)
1 to R5 (this rest information is also used as time information) and a rest indication information designation switch NR indicating that the next note is a rest. This rest instruction information designation switch NR is used to, when a musical note is sounded and the next note is a rest, cause the generated musical note before the rest to be emitted by extending it to a certain extent to prevent unnatural musical tones from disappearing at the rest. It is provided in These switch groups T1 to T5. Of~05, Nl~N12. R1~R5,
A logic value "1" is input to one end of each NR.

The other ends of the time information designation switches T1 to T5 are respectively connected to the input side of the OR circuit group 21 as shown in the figure, and similarly, the other ends of the rest information designation switches R1 to R5 are connected to the input side of the OR circuit group 21 on the one hand. It is connected to the.

Here, the time information designation switches T1 to T5, the rest information designation switches R1 to R5, and the OR circuit group 21 are connected to each of these switches T1 to T5. By turning on each of R1 to R5, each output line TCI of the OR circuit group 21
~TC5 are wired so that coded time information as shown in the following table (1) is output.

Table (1) As is clear from this table (1), each note and each corresponding rest are indicated by the same code.

The other ends of the octave information designation switches 01 to 05 are respectively connected to the input side of the OR circuit group 22 as shown in the figure.
The other ends of the note name information designation switches N1 to N12 are also connected to the input side of the OR circuit group 230, respectively, as shown. Further, the other ends of the rest information designation switches R1 to R5 are connected to the input side of the OR circuit 25 on the other side. The output sides of the OR circuit groups 22 and 23 are respectively connected to the first input terminal group of the AND circuit group 24 as shown, and the output side of the OR circuit 25 is connected to the OR circuit group 24 via an inverter 27 as shown. is connected to the second input terminal group of.

Here, the other ends of the octave information designation switches 01 to 05 provided corresponding to each range and the OR circuit group 22
And the AND circuit group 24 connects each of these contacts 01 to 05.
By turning on each of them, the output lines OC1 to OC3 of the AND circuit group 24 are connected so that coded octave information as shown in Table (2) below is output.

Table (2) In addition, the other ends of the note name information specifying switches N1 to N12 provided corresponding to each note name, the OR circuit group 23, and the AND circuit group 24 are set to turn on each switch N1 to N12. As a result, the output lines NCI to NC4 of the AND circuit group 24 are connected so that coded pitch name information as shown in Table (3) below is output.

Table (3) In addition, the other ends of the rest information designating switches R1 to R5 provided for each rest, the OR circuit 25, the inverter 27, and the AND circuit group 24 are connected to each of the switches R1 to R5.
5, the output lines OCI to OC3 and NCI to
When the rest instruction information designation switch NR, which indicates that NC4 is all logical values and the next note is a rest, is turned on, the logical value ゛°1° is output from the output line NRC of the OR circuit 26.
The wires are connected so that “ is output.

As is clear from the above explanation, the pronunciation time implied by the note on the score is displayed by the time information in Table (1), and the pitch of the generated musical sound meant by the note on the score is displayed by the octave information in Table (2). The pitch name information shown in Table (3) is also displayed. As mentioned above, the octave information, information, and note name information are collectively referred to as scale information. The rest times of musical tones that are meant by rests on the score are shown in the table (time information 11).
To ensure that musical tone generation is stopped during this pause time, see Table 4.
), all octave information and note name information are set to the logical value °゛O''.

In addition to the various information coded as described above, a variable resistor group 28 connected to an appropriate voltage source (not shown) is provided to output envelope control information for controlling the envelope generator. This variable resistance group 28 is connected to the input side of an analog-to-digital converter (hereinafter referred to as A/D converter) group 29, respectively. Each output of the variable resistance group 28 digitally converted by the A/D converter group 29 is output as envelope control information.

As is clear from the above description, according to this input device 11, various information designation switches T1 to T5.01 to 05, N
1 to N12, R1 to R5, and NR as appropriate and adjust the variable resistor group 28 appropriately, all information (time information, scale information, rest information) regarding one musical tone (note on musical score) can be obtained. , envelope control information) can be encoded and generated.

In this embodiment, the minimum unit of time information is a sixteenth note, and the time information is further limited to five from a sixteenth note to a whole note, but the present invention is not limited to this.
For example, the input device 11 may be configured so that the minimum unit of time information is a 64th note, and various dotted notes are also output as time information.
may be configured.

FIG. 4 is a detailed diagram showing the random access memory 9 and musical tone forming device 10 in FIG. 1, and in this embodiment, a synthesizer is used as the musical tone forming device 1G.

First, the operation of writing musical tone information into the random access memory 9 will be explained. In FIG. 4, when a logical value "1" is input to the write/read designation input terminal W/R of the random access memory 9, the random access memory 9 is in a writable state as described above. In this state, each address (in this embodiment, one address is stored in the random access memory 9 in FIG. 4) specified by the address signal ADi (i=1...n) output from the address generator Coded musical tone information (time information, scale information, etc.) output from the input device 11 is written into the bits corresponding to one line of bits shown in FIG. In particular, the last bit* of each address in the random access memory 9 contains rest instruction information (inputted by the rest instruction information designation switch NR in FIG. (information output from the output line NRC of the device 11) is written. That is, if the next musical tone to be generated is a rest, a logical value "1" is written to this final bit, and if the next musical tone is not a rest, a logical value "0" is written to this final bit.

As described above, when writing to the random access memory 9, the manually operated address generator control device 4 is activated (the manual/automatic changeover switch 6 in FIG. 1 is set to the fixed contact M), and the manually operated advance switch S2 is activated. By setting it to ON, the generation of the address signal ADi of the address generator Tough is controlled. Therefore, the performer turns on this manually operated step switch S2, and then inputs the input device 1.
1 each of switches T1 to T5.01 to 05, N1 to N12
, R1 to R12, and NR as appropriate to adjust the variable resistor group 28, musical tone information can be successively written into the random access memory 9.

By the operation described above, random access memory 9
A case will be explained in which musical tone information for one song is written in the , and the musical tone information is automatically played. In FIG. 4, the write/read designation input terminal W/R of the random access memory 9
When the logical value "0" is input to the random access memory 9, the random access memory 9 is in a readable state as described above.

Further, as described above, the address generator 7 is automatically controlled by the time detection automatic address generator control device 5 at the time of reading (in FIG. 1, the manual/automatic changeover switch 6 is set to the fixed contact A). Additionally, in this embodiment, as described above, a synthesizer is used as the musical tone forming device IO, and this synthesizer mainly includes a voltage-controlled valve oscillator 35, a voltage-controlled filter 36, a voltage-controlled amplifier 37, and a sound system 38. It is made up of. Further, the voltage-controlled valve oscillator 35 is provided with an oscillator envelope waveform generator 32, and similarly, the voltage-controlled filter 36 is provided with a filter envelope waveform generator 3.
Similarly, the voltage controlled amplifier 37 is provided with an amplifier envelope waveform generator 34.

Assume now that a certain address in the random access memory 9 is designated by the address signal ADi output from the address generator turf. At this time, since the random access memory 9 is in a readable state, the musical tone information stored at the designated address is read out. Of the musical tone information read out, only the time information is input to the time detection automatic address generator 5 as shown in FIGS. 1 and 4.
The remaining scale information (octave information + note name information), rest information, and envelope control information are each input to a digital-to-analog converter (hereinafter referred to as D/A converter) group 31 via a latch circuit 30. . Musical tone information converted into analog signals by the D/A converter group 31 is inputted to envelope generators 32, 33, 34, a voltage-controlled optical oscillator 35, and a voltage-controlled filter 36 as appropriate.

Further, the time detection automatic address generator control device 5 receives the above-mentioned time information, and as shown in FIG.
2 outputs a time signal TS.

This time signal TS is generated by the envelope waveform generator 32, 33.
, 34 are input to the time signal input terminals T.

A synthesizer consisting of an envelope waveform generator 32, 33, 34, a voltage-controlled optical oscillator 35, a voltage-controlled filter 36, a voltage-controlled amplifier 37, and a sound system 38 is converted into an analog signal by a D/A converter group 31. Upon receiving musical tone information and a time signal TS output from a time detection automatic address generator control device 5, the musical tone stored in a random access memory 9 is accurately generated. When the sound is generated for a certain period of time determined by the time information stored in the random access memory 9, one pulse is generated from the output terminal Bl (see Fig. 1) of the time detection automatic address generator control device 5 as described above, and this pulse is generated as an address. The address generator 7 outputs the next address signal ADi. Therefore, the next address in the random access memory 9 is specified, and the same tone information reading operation is repeated thereafter.

Here, the latch circuit 30 stores the logical value "1" (rest instruction information) in the last bit* of each address of the random access memory 9 (that is, the tone information stored in the next address In order to prevent the generated musical note from suddenly disappearing due to the presence of a rest, it temporarily latches the musical note information and gradually reproduces the generated musical note in a natural way. It has the function of extinguishing.

FIG. 5 (A+ is a detailed diagram of the manually operated address generator control device 4, the time-detecting automatic address generator control device 5, and the address generator tofu in FIG. 1).

The manually operated address generator control device 4 is composed of an up/down designation switch SL and a manually operated advance switch S2. Up/down designation switch S1
One end is grounded, the other end is connected to the positive voltage source +V via a resistor, and the other end is connected to the up/down designation input terminal U of the counter 71 of the address generator 7.
/D is connected. Also, manually operated step switch S2
is connected on one side to a positive voltage source +V, and on the other side to a fixed contact M of the manual/automatic changeover switch 6 via a differentiating circuit consisting of a capacitor 41 and a resistor 42.

One end of the start switch 1 is grounded, the other end is connected to the positive voltage source V via a resistor, and the input end of the differentiating circuit 61 and the address generator 7 are connected to the other end.
is connected to the reset terminal R of the counter 71. The output side of the differentiating circuit 61 is connected to the first input terminal of the OR circuit 3 via a delay circuit 82 and an inverter 63. The output side of the inverter 63 is also connected to the reset terminal R of the oscillator 50 of the time detection automatic address generator control device 5 via a switch 85. A movable contact of a manual/automatic changeover switch 6 is connected to the second input terminal of the OR circuit 3, and the output side of the OR circuit 3 is connected to a counter 7.
It is connected to the counting input terminal C of No. 1.

The address generator 7 has a counter 71 and a decoder 72
The output side of counter 7 is decoder 7.
Connected to the input side of 2. The output side of the decoder 72 is connected to the address input side of the random access memory 9, as shown in FIG.

The time detection automatic address generator control device 5 is constructed as follows. The output side of an oscillator 50, which generates a clock pulse CP and whose oscillation frequency can be adjusted by a variable resistor 51, is connected on the one hand to the input side of a divider 52 and on the other hand to a D-type flip-flop 58.
The output side of the 0 divider 52 connected to the reset terminal R of is a counting circuit 53 consisting of a combination of a counter and a decoder.
is connected to the counting input terminal C of. Here, counting circuit 5
3 sequentially counts the pulses cp' input to its counting input terminal C, and connects one output line C1 (i
=1.2...n) is configured to output a logical value "1". In this embodiment, the frequency divider 52 is configured to output the clock pulse CP' at a period corresponding to a sixteenth note.
is formed. Each output line 01 to Cn of the counting circuit 53
is connected to the address input side of the read-only memory 54, and each output line R1,
R2 to Rn are connected to the input sides of corresponding AND circuits ANI to ANH, respectively, as shown. Here, the read-only memory 54 has a function equivalent to the OR circuit group shown in FIG. Output line R1~
In other words, the counting circuit 53 counts the first clock pulse cp' and outputs a logic value to the output line C1. When the value °゛1” is output, read-only memory 54
All of the output lines R1 to Rn output the logical value "1",
When the second clock pulse CP' is counted and a logic value "1" is output to the output line c2, the read-only memory 54
The output lines R2 to Rn output the logical value "1", and thereafter the read-only memory 54 outputs the logical value "1" in the same pattern.
" is output, and when the n-th clock pulse CP" is counted, only the output terminal Rn of the read-only memory 54 outputs the logical value "1".

Further, as shown in FIGS. 1 and 4, the time information read from the random access memory 9 is input to the decoder 55 of the time detection automatic address generator control device 5, and each output line D1 to Dn of the decoder 55 is inputted to the decoder 55 of the time detection automatic address generator control device 5. are connected to the input sides of AND circuits ANI to ANn, respectively, as shown. Here, the decoder 55 outputs a logical value "1" to the output lines D1 to Dn as shown in Table (6) for each time information read from the random access memory 9.

Table (6) Each output line of the AND circuits ANI to ANn is connected to the input side of the OR circuit 57, and the output side of the OR circuit 57 is connected to the input terminal of the D-type flip-flop 58.

The output terminal Q of the flip-flop 58 is connected to the reset terminal R of the counting circuit 53, the reset terminal R of the frequency divider 52, the input side of the differentiating circuit 590, the fixed contact A of the manual/automatic changeover switch 6, and the input terminal of the musical tone forming device 10. Each is connected to T. Further, the output side of the differentiating circuit 59 is connected to the reset terminal R of the oscillator 50.

A manually operated address generator control device 4 and a time detection automatic address generator control device 5 having the above configurations.
Next, the operation of the address generator tough will be explained.

When a performer writes musical tone information to the random access memory 9, as described above, the write/read designation switch 8 shown in FIG. 1 is set to the fixed contact W side. to make the random access memory 9 writable. Next, in order to control the address generator graph by the manually operated address generator control device 4, the manual/automatic changeover switch 6 is set to the fixed contact M.

Furthermore, after confirming that the switch 135 is in the "1" position, when the start switch 1 is turned on, the positive voltage +V applied to the reset terminal R of the counter 71 of the address generator 7 is grounded via the start switch 1. Therefore, the reset state of the counter 71 is released. At the same time, the differentiating circuit 61 differentiates this potential change from +■ volts to ground and generates one negative pulse.

This negative pulse is delayed by a minute time by the delay circuit 62 and then converted into a positive pulse by the inverter 63.
It is input to the counting input terminal C of the counter 71 via the OR circuit 3. Since the time at which this pulse is input to the input terminal C of the counter 71 is delayed by a minute time than the time at which the reset state of the counter 71 is released due to the action of the delay circuit 62, this pulse is reliably counted by the counter 71. This count value is converted into the first address signal ADI by the decoder 72, and the random access memory 9
The first address of the random access memory 9 becomes writable. In this state, the first musical tone information is stored at the first address of the random access memory 9 by appropriately operating various switches T1 to NR (FIG. 3) of the input device 11.

To write musical tone information from the second address onwards in the random access memory 9, turn on the step switch S2 of the manually operated address generator control device 4, and then turn on the step switch S2 of the input device 11.
This is done by operating various switches T1 to NR (FIG. 3). That is, when the stepwise switch S2 is turned on, a differentiating circuit consisting of a capacitor 41 and a resistor 42 captures the sudden voltage rise to +V volts at the fixed contact of the stepwise switch S2 and generates one pulse. This pulse is input to the counting input terminal C of the counter 71 via the manual/automatic changeover switch 6 and the OR circuit 3. Therefore, the counter 71 counts this pulse, and the decoder 72 outputs the second address signal AD2 to the random access memory 9.
Output. Therefore, the second
The address becomes writable, and the second musical tone information is written by turning on various switches T1 to NR of the input device 11 as appropriate. In this way, musical tone information is written into the random access memory 9 one after another.

In addition, if the performer makes a mistake in operating the input device 11 and writes incorrect musical tone information, this information can be corrected as follows.0 Manual operation address generator control device 4 up/down designation Switch S1 is set to the fixed contact side. As a result, the positive voltage +V applied to the counter 71 is grounded, so that the counter 71 is set to perform a subtraction operation, contrary to the normal addition operation. Subsequently, an address signal AD is output from the decoder 72 in which the address where the incorrect musical tone information is written is
The step switch S2 is turned on and the various switches T1 to NR of the input device 11 are operated until the correct musical tone information is stored in the random access memory 9 until specified by i.

A case will be described in which the musical tone information written in the random access memory 9 is read out by the musical tone information writing operation described above and the automatic performance is performed.

First, the performer turns on the write/read designation switch 8 shown in FIG. 1 to the fixed contact R side to put the random access memory 9 in a readable state. Next, in order to control the address generator turf with the time detection automatic address generator control device 5, a manual/automatic changeover switch 6 is used.
is recessed into the fixed contact A side.

Furthermore, after turning on the switch 65, the start switch 1 is turned on.
When set to input, the counter 71 of the address generator turf is set to
The reset state of is released, and the pulses generated by the differentiating circuit 61 are input to the counting input terminal C of the counter 71 with a minute delay due to the action of the delay circuit 62. Further, the pulse output from the differentiating circuit 61 is inputted to the reset terminal R of the oscillator 50 of the time detection automatic address generator control device 5 via the switch 55 after being delayed by a minute time. A counter 71 reliably counts the pulses and a decoder 72 stores the first pulse in the random access memory 9.
The second address signal ADI is output. Therefore, the random access memory 9 reads out the musical tone information stored at the first address thereof, and as described above, only the time information is read out from the time detection automatic address generator IIJ controller 5.
The other musical tone information is input to the musical tone forming device 1°. Therefore, the musical tone forming device 10 generates musical tones according to the input musical tone information as described above.

The time detection automatic address generator control device 5 processes the time information input to the decoder 55 as follows, counts the time of the generated musical tone, controls the generation of the address signal ADi of the address generator turf, and controls the musical tone forming device 10. The time information TS is output to the input terminal T of.

Since the switch 65 is set to close as described above,
A pulse generated from the differentiating circuit 61 when the start switch 1 is turned on is input to the reset terminal R of the oscillator 50 of the time detection automatic address generator control device 5. Therefore, at the same time that the address generator Taf outputs the first address signal ADI and the first musical tone information is read from the random access memory 9, the oscillator 50 starts generating the clock pulse CP.

This clock pulse CP is divided into clock pulses CP' by frequency division m52. In this embodiment, the frequency divider 52 uses a clock pulse C with a period corresponding to the length of a sixteenth note.
It is configured to output P'. This clock pulse CP' is input to the counting circuit 53, and the counting circuit 53 outputs a logical value "1" to the corresponding one-tree output line Ci in accordance with the count value of the clock pulse cP'.

As mentioned above, the read-only memory 54 is connected to the counting circuit 5.
39 Receives the logical value “1” sequentially output from the output line Ci (i = 1, 2・-n) and outputs the output terminals R1 to R
A logic output as shown in FIG. 6 is generated at n.

Now, assuming that the time information stored at the first address of the random access memory 9 is an eighth note, the table (
11), the decoder 55 has its output line D2.
The logical value “1” is output only when the other outputs MDI, D3~
A logic value "0" is output from Dn. Therefore, when the counting circuit 53 counts the first clock pulse CP' and the read-only memory 54 outputs the logical value "1" from all of the output lines Rt to Rn, the AND condition of the AND circuit AN2 is satisfied, so the OR circuit A logic value "1" is input to the D-type flip-flop 57, so a logic value "1" is input to the input terminal of the D-type flip-flop 5B, and the output terminal Q outputs a logic value "0".

Subsequently, the counting circuit 53 counts the second clock pulse CP' and outputs the output lines R2 to Rn of the read-only memory 54.
When the logic value "'1" is output, the AND condition of the AND circuit AN2 is satisfied as described above, so the OR circuit 5 is output.
A logical value "1" is inputted to the input terminal of the D-type flip-flop 58 via the input terminal 7. Therefore, the frisub flop 5
8 continues to output the logical value "O" as shown in FIG. 6(B). Subsequently, the counting circuit 53 outputs the third clock pulse CP'
The output lines R3 to Rn of the read-only memory 54 are counted.
When the logic value "1" is outputted to the AND circuit AN2, the AND condition of the AND circuit AN2 no longer holds true. Therefore, a logic value "0" is output to the OR circuit 57, and this logic value "O" is input to the input terminal of the D-type flip-flop 58. Therefore, D
The type flip-flop 58 is inverted and the output terminal Q is as shown in FIG.
As shown in B), 0w outputs the logical value “1” at this point.
The L portion circuit 59 generates one pulse in response to this change from the logical value "0" to the logical value "1". Since this pulse is input to the reset terminal R of the oscillator 50, the oscillator 50
The clock pulse CP output by the 0 oscillator 50 is immediately reset and starts generating a new clock pulse CP.
is input to the reset terminal R of the D-type flip-flop 58. Therefore, as shown in FIG. 6(B), the D-type flip-flop 58 is immediately reset and the output terminal Q becomes the logic value "0".
”. In this way, the time specified by the time information stored in the random access memory 9 is accurately detected, and the sixth
One pulse is generated as shown in Figure (B).

As described above, the output terminal i of the D-type flip-flop 5B
On the one hand, the pulses outputted from are input as a time signal TS to the input terminal T of the musical tone forming device 10, and on the other hand, the pulses are input to the counting input terminal C of the kakunta 71 of the address generator 7 via the manual/automatic changeover switch 6 and the OR circuit 3.
is input. Therefore, the musical tone generating device 1O stops generating the musical tone stored at the first address of the random access memory 9, and furthermore, the address generator 7 outputs the second address signal AD2. Furthermore, since this pulse is input to the reset terminal R of the frequency divider 52 and the counting circuit 53, both are reset at this point and are ready for the next time detection operation.

The random access memory 9 receives the second address signal AD2 output from the address generator turf and reads the second address signal AD2.
Reads the musical tone information stored at the address. The read musical tone information is generated by the time detection automatic address generator control device 5, which accurately detects the time specified by the time information and generates a pulse, just as the musical tone is generated at the first beat. Then, the musical tone stored in the second address of the random access memory 9 is generated from the musical tone forming device 10.

Subsequent musical tone generation operations are performed in exactly the same manner.

In addition, in the above explanation regarding the time detection operation, the case where an eighth note is read out as time information from the random access memory 9 has been explained, but when other notes are read out, time detection can be performed using exactly the same operation. It will be done. For example, when a quarter note is read out, when the counting circuit 53 counts the fifth clock pulse CP', the AND condition of the AND circuit AN4 no longer holds, and at this point the D-type flip-flop 58 is inverted. Then, the output terminal Q is a logical value “!
Since the D-type flip-flop 58 is then directly reset by the clock pulse CP output from the oscillator 50, the output terminal Q of the D-type flip-flop 58 outputs the logical value "O" again, and the result is One pulse is generated from the output terminal Q of the D-type flip-flop 58 as follows.

In the embodiments shown in FIGS. 3 to 6, a synthesizer is used as the musical tone forming device 1G, but the explanation is not limited to this. For example, the musical tone forming device may be a waveform memory read-out method. An electronic musical instrument or the like may also be used.

A second embodiment of the time-sensing automatic address generator control device 5 is shown in FIG. Encoded time information read from random access memory 9 is input to decoder 80 . Each output line D1 of the decoder 80
~Dn are respective delay circuits DLI, DL2...-Dt
, n. Each delay circuit DLI~D
The output side of Ln is connected to the input side of OR circuit 81, and the output side of OR circuit 81 is connected to the input side of differential circuit 820. Here, the decoder 80 has one output line Di (i=1, -"n
) is configured to output a logical value of “1” only when

For example, if the note specified by the time information is a sixteenth note, the logical value "11" is output to the first output line DI, and if it is an eighth note, the logical value "1" is output to the second output line D2. ”
is output, and in the case of a whole note, a logical value "1" is output to the n-th output line Dn. In addition, delay circuits DLI to DLn
is a logical value "!" that is input at a certain timing as shown below.
For example, the first delay circuit DLI delays the input logical value "1" by a time corresponding to a sixteenth note and outputs it, and the second delay circuit DL2 The third delay circuit DL3 outputs the logical value "1" with a time delay corresponding to an eighth note, and the third delay circuit DL3 receives the input logical value "1".
'' is delayed for a time corresponding to a dotted eighth note and outputted.The n-th delay circuit DLn then delays and outputs the input logic value "1" for a time corresponding to a whole note.

The operation of this time detection automatic address generator control device 5 having the above configuration will be explained. Now, assume that the note defined by the time information is an eighth note.

As described above, in this case, the logic value "1" is output only to the second output line D2 of the decoder 80. This logical value "1" is input to the second delay circuit DL2, delayed for a time corresponding to an eighth note, and then input to the differentiating circuit 82 via the OR circuit 81. Therefore, at this time, the differentiating circuit 82 generates one pulse in response to the change from the logical value "0" to the logical value "1". In this embodiment, this pulse is used as a stepping pulse for the time signal TS and the address generator turf.

(Effects of the Invention) As is clear from the above explanation, according to the automatic performance device for an electronic musical instrument of the present invention, the player can freely write songs into the storage device, and can also write a part of the song that has been written once. It is possible to provide an automatic performance device for an electronic musical instrument that can freely and easily change (modify) the following. Furthermore, even those who cannot play electronic musical instruments at all can enjoy automatic performance because they can store musical tone information, and have the effect of being able to freely compose, arrange, etc.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 (
A) and (B) are explanatory diagrams showing AND circuits and OR circuits used in this specification, FIG. 3 is a detailed diagram of the input device, and FIG. 4 is a detailed diagram of the random access memory and musical tone forming device.
Figure 45 (A) is a detailed diagram of the manually operated address generator control device, time detection automatic address generator control device, and address generator, Figure 5 (B) is a circuit diagram showing the read-only memory function, and Figure 6 (^) , (B) is a timing chart of the time detection automatic address generator shown in FIG. 5, and FIG. 7 is a detailed diagram showing a second embodiment of the time detection automatic address generator. 1... Start switch, 2... Delay circuit, 4...
・Manual operation address generator control device, 5... Time detection automatic address generator control device, 6... Manual/automatic changeover switch, 7... Address generator, 9... Random access memory, 10... Musical tone Forming device, 11... input device. Applicant Yamaha Co., Ltd.

Claims (1)

[Claims] (a) an input operation means for inputting musical tone information for automatic performance; (b) a storage device having a large number of addresses and capable of reading and writing for each address; (c ) address increment operation means for performing an address increment operation in either the address value increasing direction or the address value decreasing direction with respect to this storage device; (e) writing for writing musical tone information consisting of pitch information and time information in accordance with the operation of the input operation means into the address specified by the address specification means; Means (f) An automatic performance device for an electronic musical instrument, comprising: musical tone generating means for automatically generating musical tones by sequentially reading musical tone information written in the storage device.