JPH02210543A - Data processor - Google Patents

Abstract

PURPOSE:To shorten the delay time of a parity part by inhibiting the application of a selection means which selects one of optical data containing parities for a parity part having a large delay time. CONSTITUTION:A 1st selection means 12 which selects the optional one of plural data containing parities, a 1st memory means 20 which holds the selected data containing a parity are provided. Then a 2nd memory means 24 which holds the parity part of the data containing a parity which has a large delay time of the parity part, a 2nd selection mean 28 which performs the switch between a parity part 22 stored in the means 20 and the parity part stored in the means 24 and outputs selectively both parity parts are provided. Further more, the control parts 26 and 30 are provided to give an instruction to the means 28 to select the parity part stored in the means 24 when the data containing a parity having a large delay time of the parity part is selected by the means 12 and then written into the means 20. As a result, the delay time of the parity part is shortened when a parity is produced via a duplex computing element.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device that handles data with parity, and particularly relates to processing when the delay time of the parity part of data with parity is large.

[Conventional technology]

Generally, when creating parity for data calculated by an arithmetic unit, there is a method in which the arithmetic units are duplicated, one arithmetic unit is used to obtain the arithmetic data, and the other arithmetic unit is used for creating parity.

A circuit configured to write the data and parity determined by the duplication circuit described above into a storage device through a selection circuit is often used in a data processing device that handles data with parity.

[Problem to be solved by the invention]

When creating parity using a duplex circuit in a data processing device that handles data with parity, as described above,
Since the parity part of the data with parity was configured to be selected through the same selection means as the data part after passing through the parity generation circuit, there was a problem that the delay time was longer than that of the data part. Ta.

The present invention was made in view of these circumstances, and
It is an object of the present invention to provide a data processing device in which the delay time of the parity part of data with parity is reduced when parity is created by duplicating arithmetic units.

[Means to solve the problem]

In order to achieve the above object, the present invention includes a first selection means for selecting arbitrary data with parity from a plurality of data with parity, and a data with parity selected by the first selection means. a first storage means for holding a parity part of data with parity having a large delay time; a second storage means for holding a parity part of data with parity having a large delay time; and a parity part stored in the first storage means and a second storage means. a second selection means for selectively outputting the parity part by switching between the data and the parity part stored in the first selection means; The present invention is characterized in that it has a control section that instructs the second selection means to select the parity part stored in the second storage means when the second selection means selects the parity part stored in the second storage means.

According to the present invention, since the parity portion of the parity-attached data with a large delay time is not passed through the selection means for selecting any one of the parity-attached data, the arithmetic unit can be duplicated. When creating parity using the above method, the delay time of the parity section can be shortened.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of an embodiment of a data processing device according to the present invention. In this embodiment, it is assumed that 9-bit data, which is an 8-bit data section plus a 1-bit parity section, is handled. In the figure, the data processing device includes a decoder 10 that decodes a select signal 100 that selects any one of arbitrary data with parity, and a selector that selects specific data with parity based on information decoded by the decoder 10. 12 and data OPI
, OF2, a parity creation circuit 18 that creates parity based on the calculation output of the calculation unit 16, and a register 20 that holds the data part of the data with parity selected by the selector 12. A register 22 that holds the parity part of the data with parity, a register 24 that holds the parity created by the parity creation circuit 18, and a selector 12 are connected to the arithmetic unit 1.
A register 26 is set to logic "1" when the data ALU (0 to 7) output from the register 4 is selected and a set instruction is issued by the set signal 102; or register 2
4, an AND gate 30, and an inverter 32.

The selector 12 receives a select signal 100 by the decoder 10.
Data A (0 to 8, P
), B (0-8, P), C (0-8, P),...
...X (0 to 8, P), or data A
Select one of LU (0 to 7).

Here, data ALU (0 to 7) is data ○P1, OF
This is the result of computing 2 by the computing unit 14.

Furthermore, when the set signal 102 issues a set instruction, the data with parity outputted from the selector 12 has its data portion stored in the register 20 and its parity portion stored in the register 20.
It is now written to . The arithmetic unit 16 is a duplication of the arithmetic unit 14, and creates parity based on the calculation output of the arithmetic unit 16.

Further, a new parity created by the parity creation circuit 18 is set in the register 24 when a set instruction is issued by the set signal 102, and at other times, the previously created parity is held.

In the above configuration, the select signal 100 is the data ALU
The operation of the data processing apparatus when the selection of (0 to 7) is instructed and the set signal 102 issues a set instruction will be described.

Now, when the select signal 100 instructs the selection of data ALU (0 to 7), the selector 12 receives the output of the decoder 10 and outputs the data ALU (0 to 7) from the arithmetic unit 14.
~7) and select this selected data ALU (0~7).
7) is set in the register 20, and the contents of the register 20 are output to the output terminal 0UT (0-8). At the same time, the calculation results ALU (
0 to 7) is created by the parity creation circuit 18 and set in the register 24. At this time, the select signal 100 instructs selection of data ALU (0-7) and the set signal 102 issues a set instruction, so data of logic "1" is set in the register 26.

On the other hand, since the logic "1" is set in the register 26, the selector 28 selects the parity written in the register 24 from among the parities written in the registers 22 and 24, and outputs the output terminal OUT (P). Output to.

Therefore, according to this embodiment, the data of the parity section having a long delay time can be written directly to the register 24 without reversing the selector 12, and the delay time in data processing of the parity section can be shortened.

〔Effect of the invention〕

As explained above, in the present invention, the parity portion of the parity data with a large delay time is not passed through the selection means for selecting any of the parity data, so the arithmetic unit is duplicated. When parity is created using this method, the delay time of the parity part, which has a long delay time, can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of a data processing device according to the present invention. 10...Decoder, 12.28...Selector, 14.16...Arithmetic unit, 18...Parity creation circuit, 20.22.24.26/Old ··register.

Claims (1)

[Claims] A first selection means for selecting arbitrary data with parity from among a plurality of data with parity, and a first storage for holding the data with parity selected by the first selection means. means, a second storage means for holding a parity part of data with parity having a large delay time in the parity part, and a parity part stored in the first storage means and a parity part stored in the second storage means. a second selection means for selectively outputting the parity part by switching between the parity parts; and a second selection means for selectively outputting the parity part; A data processing device comprising: a control section that instructs the second selection means to select a parity section stored in the second storage means.