JPH02210698A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain matching with the manufacturing process of a masking ROM and to reduce a chip area by constituting a redundant cell array of a floating gate type electrical PROM with one layer of polysilicon. CONSTITUTION:A field oxide film 27 is formed on a P-type substrate 28, and a floating gate FG with one layer of polysilicon is formed on the film. An inter-layer insulation film 26 is formed on the gate FG, and a word line WL is formed via the film 26. Furthermore, a diffusion layer 29 which becomes a spare bit line BLs is formed, and a transistor area 30 which becomes the redundant cell RMC of the electrical PROM is comprised. The cell RMC accumulates an electric charge in the gate FG by a voltage applied between the word line WL and the spare bit line BLs, and stores data for a defective cell instead of an ordinary cell array 21. Thereby, the matching with the manufacturing process of the masking ROM can be obtained, and the increment of the chip area can be suppressed.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology (Figs. 9 to 12) Means and Action Embodiment for Solving Problems First Embodiment (Figs. 1 to 5) Figure) Second Embodiment (Figures 6 to 8) Effects of the Invention [Summary] This invention relates to a semiconductor memory device, and particularly to a semiconductor memory device having a redundancy function suitable for a mask ROM.
The purpose of the present invention is to provide a semiconductor memory device having a redundant circuit suitable for the manufacturing process of the present invention and capable of suppressing an increase in chip area. In the semiconductor memory device, the redundant cell has a source or a drain connected to a bit line side. S transistor and one electrode is the M
A capacitor is connected to the gate of the IS transistor, and the other electrode is connected to the word line side.

[Industrial application field]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a redundant circuit function suitable for a mask ROM.

As semiconductor memories become smaller and have larger capacities, the number of defective cells in the semiconductor memory manufacturing process also increases. Due to the existence of such defects, even though there are many non-defective parts, the entire chip is judged to be defective, resulting in a decrease in yield. Therefore, in order to save chips from such defects, semiconductor memories are provided with redundant circuits.

The redundant circuit programs the address of a defective cell detected during a wafer probing test among the memory cells of a semiconductor memory (hereinafter referred to as a normal cell array) into a defective cell address memory, and when the defective cell is accessed, Based on the programming data of the defective cell address memory, the defective cell is replaced with a redundant memory cell to make the chip accessible and rescue the chip. Programming methods can be roughly divided into a first method of cutting a polysilicon fuse with a laser, a second method of reducing the resistance of high-resistance polysilicon with a laser, and a third method of blowing out the fuse with an excessive current. be.

At present, the above redundant circuit technology is DRAM.

It is only applied to memory that can be written and read afterward, such as SRAM and EFROM, and the mask R
It is not applied to O”M.The reason is that the mask RO
While writing data to M is performed during the manufacturing process of the mask ROM, data for defective cells is written to redundant cells during the wafer probing test after the manufacturing process, and it is not possible to write data to the redundant cells during the wafer probing test. Because it is possible.

The present invention relates to the application of redundant circuit technology to this mask ROM.

[Conventional technology]

Hereinafter, conventional redundant circuits will be described using SRAM, which is a writable memory, and mask RAM, which is not writable, as examples.

SRAM redundant circuit FIG. 9 shows an outline of a conventional SRAM redundancy circuit.

First, the access operation to the normal cell array 3 during normal operation will be explained. External address data ADD is applied to row address buffer 1 and column address buffer 4, respectively.

Row address buffer 1 and column address buffer 4 each amplify external address data ADD from TTL level to MOS level, generate address signals A, A of positive phase and reverse phase, and send them to row decoder 2 and column decoder 5. send to

Row decoder 2 and column decoder 5 decode each address signal A, A and select the designated word line WL and bit line BL. In this way, the memory cell Me at the intersection of the selected word line WL and bit line BL
is specified and a read operation is performed. Note that the write operation is basically the same as above, but the write data
The signal flows from lo to the output buffer 12, the data switching circuit 9, the column decoder 5, and the sense amplifier 6.

Next, if there is a defective cell due to a bit line defect in the normal cell array 3, the address of the defective cell is known at the time of the wafer probing test, so it is stored in advance in the defective cell address memory 7 (details will be described later). (See Figures 10 and 11).

If the external address data ADD is for a defective cell, the address comparison circuit 8 compares the defective address signals F, F from the defective cell address memory 7 with the address signals A, A, and a match signal ACC is sent to the data switching circuit 9.
is output to.

The output of the match signal ACC means that the memory cell MC accessed by the external address data ADD is a defective cell, so the data switching circuit 9 selects the redundant sense amplifier 10 instead of the data from the column decoder 5. The data is switched to the data from the redundant cell RMC of the redundant cell array 11 through the redundant cell array 11.

In this way, the data of the defective cell is replaced with the data of the redundant cell RMC, and even if there is a defective cell in the normal cell array 3, the chip can operate as a good product in appearance. The case of writing is the same as above, and the data flow is as shown above.

In the above configuration, the portion surrounded by a broken line is a redundant circuit.

In the redundant circuit described above, the same method is used to store the defective cell address in the defective cell address memory 7 and to program replacement data into the redundant cell array 11. Examples are shown in FIGS. 10 and 11.

FIG. 10 shows that the polysilicon fuse f is blown by an excessive current i, and the logic becomes "0" when the polysilicon fuse f is blown.
An example of storing logic "1" without blowing is shown. When blowing, input the blowing signal "H" level to the gate of drive transistor Q1 (NMO8) to turn on drive transistor Q1. Then, 71 sources Polysilicon fuse f1 drive transistor Q5GN due to s pressure Vcc
On route D! An excessive current i flows. This excessive current i causes the polysilicon fuse f to melt. After that, the drive transistor Q
By cutting off l, the potential at the output terminal OUT is pulled down to the vss level via the pull-down resistor R1, and a redundant signal of logic "0" is output. On the other hand, if it does not blow out, turn off the drive transistor Q1.
The output terminal OUT should be connected to a pull-down resistor Rp.
Since it is kept at high impedance by the power supply voltage V. It outputs 0 and becomes a redundant signal of logic "1".

A plan view of the above fuse pattern is shown in FIG. A polysilicon fuse f is formed in the bottom layer, and Ag wiring 15.16 is formed at each end via contact holes 13.14.
is connected. The thin line portion is the fusing portion 17 .

Redundant circuit for mask RAM A prototype example of a redundant circuit for mask ROM is shown in FIG. However, it has the following drawbacks and has not been put into practical use. Note that in FIG. 12, the same parts as in FIG. 9 are given the same reference numerals, and the explanation thereof will be omitted.

This redundant circuit combines data read out from the normal cell array 3 via the sense amplifier 6 and the redundant sense amplifier 1.
0 from the redundant cell RMC read out via ECC (ErorCorreeNng Code
) The correct data is generated using the circuit 19 and outputted from the output buffer 20. Redundant cell R
Data written to the MC is performed in a process step, and is generated in advance using a Hamming code based on data written to the normal cell array 3.

[Problem to be solved by the invention]

The problem with applying redundant circuit technology to mask ROMs is that the chip area increases excessively, exceeding the allowable range, and reducing the significance of the LSI. The reason is as follows.

First of all, mask ROM takes a completely different manufacturing process from DRAM and SRAM in that data is written during the wafer process. Therefore, when trying to store a defective cell address, the defective cell address memory 7
It is necessary to add the redundant cell array 11 and the mask ROM in a process different from that of the mask ROM.

Second, even if the redundant cell array 11 were formed using polysilicon fuses f as shown in FIGS. 10 and 11, the redundant cell array 11 would be The area occupied becomes excessive, and the area of the entire chip becomes excessive.

In the method of programming using polysilicon fuses f, as shown in FIG. This is due to an increase in the area of Redundant cell R
Since MC requires more than the number of bits, it is expected that the overall chip area will increase considerably.

On the other hand, as shown in FIG. 12, a device using an FCC circuit has also been proposed. According to this method, since the programming of the redundant cells RMC of the redundant cell array 11 is performed during the manufacturing process, both the normal cell array 3 and the redundant cell array 11 can be constructed from mask ROMs.

However, a large number of bits is required, and the area of the redundant cell array 11 becomes too large in this case as well. For example, 1
Since 5 redundant bits are required for 6 bits, the redundant cell array 11 is usually 5/1 of the cell array 3.
As many as 6 areas are required, and an increase in the area of the entire chip cannot be avoided.

For these reasons, redundant circuit technology for mask ROMs has not yet been established.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device equipped with a redundant circuit that is suitable for a mask ROM manufacturing process and can suppress an increase in chip area.

[Means to solve the problem]

In order to solve the above problems, the present invention provides a semiconductor memory device comprising a normal cell array and a redundant cell that can replace a defective part in the normal cell array, wherein the redundant cell has a source or a drain that is bit-bit. M connected to the line side
It is configured to include an IS transistor and a capacitor having one electrode connected to the gate of the MIS transistor and the other electrode connected to the word line side.

[Effect]

According to the present invention, the redundant cell (RMC) is
Since the redundant cell (RM
C) The area per piece is smaller than that of a conventional polysilicon fuse (f
) can be made much smaller. Therefore, increase in chip area can be suppressed.

〔Example〕

Next, embodiments according to the present invention will be described based on the drawings.

First Embodiment FIG. 1 shows a first embodiment of the present invention. FIG. 1 shows a redundant circuit for relieving defects caused by pit line defects. In FIG. 1, parts that overlap with those in FIG. 9 (conventional example) are given the same reference numerals and explanations will be omitted.

The difference between FIG. 1 and FIG. 9 is that the normal cell array 2
1 is composed of a mask ROM, and the redundant cell array 22 is composed of a floating gate type EFROM. Note that 23 is a row decoder for selecting the spare bit line BL8 of the redundant cell array 22, and 24 is a write circuit.

FIG. 2 shows the configuration of the normal cell array 21. Figure 2 (a
) is a plan view of the memory cell MC, and FIG. 2(b) is a cross-sectional view thereof. This figure 2(a).

As shown in (b), the mask ROM is usually formed of a polysilicon layer. Therefore, redundant cell array 2
2 without significantly changing the manufacturing process of the normal cell array 21, it is necessary to form it with a polysilicon layer like the normal cell array 21, and programming of the redundant cell RMC corresponding to the defective cell is required. To do this a posteriori, the memory must be writable.

Therefore, in the present invention, the redundant cell array 22 is
This is a ROM, and the EPROM is formed of a polysilicon layer. FIG. 2(a) is a plan view of the redundant cell RMC of the redundant cell array 22 in this embodiment, FIG. 2(b) is a sectional view thereof, and FIG. 3 is a normal EPR.
An explanatory diagram of the correspondence between OM and EFROM of the present invention is shown.

As shown in FIGS. 2(a) and 2(b), a field oxide film (SiO2) 27 is formed on a P-type substrate 28, and a floating gate FG of a polysilicon layer is formed on it. . An interlayer insulating film (SiO2) 26 is formed on the bloating gate FG, and a word line WL is formed via this interlayer insulating film 26. 29 is a diffusion layer (N) forming the spare bit line BL8;
0 is a transistor region that becomes a redundant cell RMC.

The above redundant cell RMC is an EPROM shown in FIG. 2(C).
is electrically equivalent to That is, since the word line WL is arranged to face the floating gate FG via the interlayer insulating film 26, it is equivalent to the control gate CG, and the floating gate FG is formed on the transistor region 30 via the field oxide film 27. It is a floating gate. Figure 2 (b) and (c)
), the interface between the floating gate FG on the transistor region 30 and the field oxide film 27 is point A, and the interface between the floating gate FG on the diffusion layer 29
The interface between the field oxide film 27 and the field oxide film 27 corresponds to point B.

The redundant cell RMC formed in this way is controlled by the voltage applied between the word line WL and the spare bit line BLs.
Charges are accumulated in the floating gate FG, and data for the defective cell is stored in place of the normal cell array 21.

Thus, according to the first embodiment, it is possible to form a redundant cell RMC that satisfies the requirements of being able to be formed with a single polysilicon layer and being writable, thereby achieving the intended purpose. .

The above is an example of the structure of the redundant cell RMC itself of the redundant cell array 22. Next, an example of the matrix structure of the redundant cell array 22 will be described. For example, 1
Assuming a 6M bit mask ROM, the cell array 21 will normally be constructed of 4K (rows) x 4K (columns). Under this condition, in order to rescue one bit line BL, it is necessary to use a 4K (row) x 1 (column) redundant cell array 2.
2 should be formed. However, the redundant cell array 22
The redundant cell RMC is the memory cell M of the normal cell array 21.
A larger area is required compared to C (Fig. 2 (a), (
b)). Therefore, it is actually difficult to create a 4K (row)×1 (column) redundant cell array 22. Therefore, the redundant cell array 22 is configured as a 512 (row) x 8 (column) cell array, and data in 8 columns is transferred to the row address buffer 1.
Row address signal A, A-AA from 0 0
11' 11 is used to decode the data into one column of data by the row decoder 23. By doing so, it is possible to suppress an increase in the area of the redundant cell array 22.

Note that the mask ROM normally has an 8-bit output. Therefore, the defective cell address memory 7 needs to store not only addresses that should be redundant, but also information on which bit of the 8-bit output is defective, and this information A, A to A23. Needless to say, the data switching circuit 9 uses A23 and M to replace the defective bits of the normal cell array 21 with the output data of the normal cell array 21.

Next, FIG. 4 shows a normal cell array 21 and a redundant cell array 2.
2 shows a connection circuit diagram. The cell system commonly used in mask ROMs at present is called the NAND type. Fourth
As shown in the figure, the cell array 21 normally has 8 (in some cases, 16) cell transistors QlO=Q17
are connected in series to form one block. Then, this one block is connected to the block select word line WL
With the block select cell transistor QIB driven by ns and the block select word line WLB8 as the word line WL of the redundant cell array 22, an address signal corresponding to selecting eight series cell transistors Qlo to Q17 is used. Redundant cell array 22
bit line BL3 is selected.

In this case, the redundant cell RMC is an MIs transistor Q2I whose source (or drain) is connected to the bit line BL3.
and a MIS capacitor Q3o, one electrode of which is connected to the gate of the MIS transistor Q21, and the other electrode of which is connected to the wand wire W L Bs.

By the way, since the redundant cells RMC usually require a larger area than the memory cells MC of the cell array 21, the redundant cells RMC cannot be arranged in the same way as the memory cells MC. Therefore, as shown in FIG.
are arranged at a pitch equal to four memory cells MC. By doing this, the number that can be arranged is reduced to 1/4, so four columns are arranged. This example shows the case of bit line relief. When selecting redundant bit lines RBLo-RBL4, word lines WLo-WL3゜WL4 to WL7
Signals A and A to select one word line from among
t to the redundancy row decoder 23, and the four bit lines RB
Select one tree of Lo-RBL3.

Second Embodiment FIG. 6 shows a second embodiment of the present invention. This second embodiment shows a redundant circuit for relieving defects caused by defective word lines. In FIG. 6, parts that overlap with those in FIG. 1 are given the same reference numerals, and their explanation will be omitted.

The difference in FIG. 6 from FIG. 1 is that a redundant cell array 31 is provided on the row side of the normal cell array 21, and correspondingly a defective cell address memory 7 and an address comparison circuit 8 are provided.
The processing operation is performed based on the address signal from the row address buffer 1, and the arrangement of the redundant cells RMC in the redundant cell array 31.

When saving one word line WL, 1 (row) x 4K
(Column) of redundant cell arrays 31 are arranged parallel to word lines WL. Then, based on the defective cell address data from the defective cell address memory 7 and the row address data from the row address buffer 1, the address comparison circuit 8 detects that the defective word line is selected, and the word line of the redundant cell array 31 is detected. Replace with WL.

In the redundant cell array 31, as in the first embodiment, a problem arises in that the redundant cells RMC of the redundant cell array 31 require a larger area than the memory cells MC of the normal cell array 21. Therefore, as shown in Figure 7, RMC-R
Four MC4s are arranged vertically in the column direction. As a result, the pitch of the redundant cells RMC in the column direction is four times that of the memory cells MC, but it is within the width of four MC-MC4, so many redundant cells RMC can be arranged.

On the other hand, when the normal cell array 21 made of mask ROM and the redundant cell array 31 made of EPROM are mixed in this way, the voltage of the bit line BL becomes a problem. This is because the operating voltage of the memory cell MC is normally about 2V, whereas the write voltage of the redundant cell RMC needs to be about 12V. Therefore, if the bit line BL is directly connected, there is a risk that the memory cell MC will be destroyed. For this reason, in this embodiment, each bit line B is connected between the redundant cell array 31 and the normal cell array 21 as shown in FIG.
An isolation transistor Q5□ is interposed in L, and this Q
5 is switched by the write control signal φRW to disconnect it at the time of writing.

Although each of the first and second embodiments described above is an example of application to a redundant memory, the idea of the present invention may also be applied to the defective cell address memory 7. By doing so, the manufacturing process for the entire memory can be made common.

〔Effect of the invention〕

As described above, according to the present invention, since the redundant cell array is formed by a floating gate type EFROM made of a single layer of polysilicon, the redundant circuit of a semiconductor memory is compatible with the manufacturing process of a mask ROM and can control an increase in chip area. can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the first embodiment of the present invention, and FIG.
) is a plan view of the normal cell array, FIG. 2(b) is a cross-sectional view of the normal cell array, FIG. 3(a) is a plan view of the redundant cell array, and FIG. 3(b) is a cross-sectional view of the redundant cell array. (
C) is an explanatory diagram of the correspondence between the redundant cell array and the EPROM, FIG. 4 is a connection circuit diagram of the normal cell array and the redundant cell array, FIG. 5 is a layout diagram of the redundant cell array in the case of bit line relief, and FIG. 6 is the diagram of the arrangement of the redundant cell array of the present invention. 7 is an explanatory diagram of the arrangement of the redundant cell array, FIG. 8 is a connection circuit diagram between a normal cell array and a redundant cell array, FIG. 9 is a block diagram of a conventional SRAM redundant circuit, and FIG. 10 is a block diagram of the second embodiment. FIG. 11 is a structural diagram of a conventional defective cell address memory, and FIG. 12 is a block diagram of a redundant circuit of a conventional mask ROM. 21... Normal cell array 22... Redundant cell array 26... Interlayer insulating film 27... Field oxide film 28... P type substrate 29... Diffusion layer 30... Transistor region 31... Redundant Cell array WL...Word line BL...Bit line BLs...Spare bit line CG...Control gate FG...Floating gate 24 degrees Green area Explanatory diagram of normal cell array Fig. 2 30 Transistor 28 Substrate j Explanatory diagram of redundant cell array Fig. 3 Fig. Connection circuit between normal cell array and redundant cell array Medical use 8
Figure 9 Conventional SRAM redundant circuit block for medical use Figure Figure Figure Figure Figure

Claims (1)

[Claims] 1. A semiconductor memory device comprising a normal cell array and a redundant cell that can replace a defective portion in the normal cell array, wherein the redundant cell has a source or drain connected to a bit line side. A semiconductor memory device comprising: a MIS transistor; and a capacitor, one electrode of which is connected to the gate of the MIS transistor, and the other electrode of which is connected to a word line side. 2. Claim 1, further comprising a defective cell address memory for storing an address of a defective portion in the normal cell array, the defective cell address memory having: an MIS transistor and a memory cell formed by the MIS transistor. The semiconductor memory device described above. 3. The semiconductor memory device according to claim 1, wherein the normal cell array is a mask ROM. 4. The semiconductor memory device according to claim 1, wherein the redundant cells are formed adjacent to the normal cell array, and an arrangement interval of the redundant cells is larger than an arrangement interval of the normal cell array. 5. In the semiconductor memory device according to claim 4, the plurality of redundant cells arranged in series in parallel with the bit line are arranged such that the number of cells is one integer divided from the number of cells arranged in the normal cell array;
A semiconductor memory device characterized by an integer multiple of these arranged in parallel. 6. In the semiconductor memory device according to claim 4, the plurality of redundant cells arranged in series in parallel with the word line are arranged such that the number of cells is one integer divided from the number of cells arranged in the normal cell array,
A semiconductor memory device characterized by an integer multiple of these arranged in parallel.