JPH02210700A - Method for generating test data of mask rom integrated circuit - Google Patents

Abstract

PURPOSE:To shorten test time and to reduce the delivery date of a product by performing a test by using a truth table also with the one by parity. CONSTITUTION:Truth value data is generated based on calculation data of 'H' level, and it is stored in a memory 14 for file after editing. Next, the calculation of even parity is performed at unit of one address, and also, the number of bits of 'H' level, the number of bits of 'H' level at every output pin, and a leakage measured value are calculated, then, test data for all the bits can be generated. After that, the edit of the test data for all bits are performed, and also, the edit of parity test data is performed. Thus, the parity test data is generated in addition to the generation of the test data for all bits, and furthermore, the test data is generated by adding the number of bits of 'H' level at every output pin. Since such method can be performed only by adding a few number of processings such as parity calculation, etc., the test time can be shortened, and the delivery date of the product can be reduced.

Description

[Detailed Description of the Invention] [Summary] A method for testing a mask ROM integrated circuit, particularly a method for creating test data for testing a mask ROM integrated circuit through data processing, which reduces test time and improves mask ROM integration. With the purpose of contributing to shortening the delivery time of circuit products, truth value data is created for each output pin of the mask ROM integrated circuit in address units based on the data written to the mask ROM integrated circuit, and the created truth value data is All-bit test data of the mask ROM integrated circuit is created based on the truth value data, and parity data is calculated for each address, and the created all-bit test data is edited and the calculated parity data is calculated. Parity test data is edited based on the data, and both the edited all bit test data and parity test data are stored in the mask ROM.
It is configured to be the final test data for the integrated circuit.

[Industrial application field]

The present invention relates to a method for testing a mask ROM integrated circuit, and more particularly to a method for creating test data for testing a mask ROM integrated circuit through data processing.

The amount of mask ROM integrated circuits used has increased by 2.5% due to higher performance, higher reliability, lower cost, etc. In addition, with the rapid development of Japanese language information processing, the amount of large-capacity mask ROM integrated circuits used as memory for generating Kanji patterns in printers, CRT displays, etc. is increasing. Under these circumstances, there is a demand for shorter delivery times for mask ROM integrated circuit products.

[Prior art and problems to be solved by the invention]

FIG. 6 shows a typical test data creation procedure for a mask ROM integrated circuit.

As shown in the figure, the test data of the mask ROM integrated circuit is transferred from the write data file 61 to the mask ROM integrated circuit based on the processing procedure defined by the control data 62
Read the data written in the integrated circuit and perform data processing (input data processing 63), ■ create truth value data based on the data processing and store it in the truth value data file 64, and ■ perform processing specified by control data 65. Based on the procedure, read the truth data from the truth data file 64 and edit it, calculate input/output bin information, leak measurement values, etc. and create all-bit test data (all-bit test data creation). Process 66), and (1) storing all the created bit test data in the test data file 67. The mask ROM integrated circuit is tested by using this all-bit test data and measuring the operation of each bit to see if data is correctly written into the mask ROM.

Since testing of mask ROM integrated circuits is performed at each stage from chip formation to product shipment, the test for all bits is repeated several times. Mask RO
In the current situation where M-integrated circuits are becoming mega-sized, the amount of data involved is enormous and the testing time is also increasing. For example, testing an 8M scale mask ROM integrated circuit on a wafer takes about 20 seconds per chip, and if we were to produce 100,000 units per month and cover this with one tester, it would take 22 days. It turns out. However, this is not possible in actual operation.

The present invention was created in view of the problems in the prior art, and an object of the present invention is to provide a test data creation method that can shorten test time and, in turn, contribute to shortening the delivery time of mask ROM integrated circuit products. It is said that

[Means to solve the problem]

In order to solve the problems in the prior art described above, a method for creating test data for a mask ROM integrated circuit according to the present invention is as follows:
As shown in the principle diagram of FIG. 1, based on write data D1 to the mask ROM integrated circuit, truth value data D is written for each output pin of the mask ROM integrated circuit in address units.
processing 1 for creating the mask ROM 2 based on the created truth value data;
Create all bit test data O1 of the integrated circuit and 1
Process 2 to calculate parity data D4 in address units
and a process 3 of editing the created all-bit test data and parity test data based on the calculated parity data, and the edited all-bit test data D, l and the parity test. Data D41
Both of these are the final test data D of the mask ROM integrated circuit.

Further, in a preferred embodiment, when calculating the above-mentioned parity data, data on the number of logically high level or logically low level pits is calculated for each output pin of the mask ROM integrated circuit, and the data on the number of logically low level pits is calculated. The data may be added to the final test data.

[Effect]

According to the method of the present invention, the amount of data in the parity test file is 1/n when the number of output bits is n compared to the amount of data in the test file for all bits (truth table). Therefore, two test files, the truth table data and the parity data, can be created in a slightly longer time than it takes to create one truth table test file.

Therefore, when testing a mask ROM integrated circuit, a test using a truth table and a test using parity can be used together, so that the test time can be significantly shortened. This contributes to shortening the delivery time of mask ROM integrated circuit products.

Further, in a preferred embodiment, each output pin has a logical high level (“H” level) or a logical low level (“H” level).
By calculating the total number of bits (L" level), the reliability of the test using parity data can be improved.

Note that other structural features and details of the operation of the present invention will be explained using the embodiments described below with reference to the accompanying drawings.

〔Example〕

FIG. 2 shows an example of a system configuration for implementing the present invention.

In the figure, 11 is the central processing unit (CPtJ), 12 is the CP
13 is a memory for storing a program that defines the process to be executed by CPU Ull; 14 is a memory for storing data written in the mask ROM integrated circuit and CPU II;
A file memory for storing various data created based on the processing of (15) is a printer that outputs the data in the memory 14 in the form of a list as necessary; Indicates the system bus that connects the

The CPU II has the function of processing input data to create a truth table (data), and performing test data creation processing to create all-bit test data and parity test data, which is a feature of the present invention. .

Next, the processing performed by the CPU II in FIG. 2 will be explained with reference to the flowcharts in FIGS. 3 and 4. Note that FIG. 3 shows input data processing, and FIG. 4 shows test data creation processing according to the present invention.

(1) Input data processing (see FIG. 3) First, in step 21, the control data read based on the reading of the card by the card reader 12, that is, the instructions for the processing procedure for creating truth value data, is decoded. In this case, the control data includes the product name, user number, data type, and editing instruction. In step 22, the decoded control data is stored in the program memory 13. In the next step 23, the read data is the one read from the last card (YE
S) or not (NO), and if the determination result is YES, proceed to step 24; if the determination result is No, return to step 21, and thereafter repeat the above-mentioned process until the final card is reached. .

In step 24, the write data of the integrated circuit is read from the file memory 14 in code units. Note that the code unit corresponds to data for a plurality of addresses. In the next step 25, it is determined whether there is any data to be read, that is, whether reading of the write data has been completed (YES) or not (NO). If the determination result is YES, the process proceeds to step 31, and the determination is made. The result is N
If the answer is O, the process proceeds to step 26. In step 26, a checksum is performed in units of one address (8 bits in this embodiment), and the number of bits at the "H" level is calculated, and in step 27, truth value data is created based on the calculated data, and is stored in the file memory 14.

In the next step 28, it is determined whether the created truth value data corresponds to the final address (YES) or not (NO), and if the determination result is YES, the process returns to step 24; If so, the process returns to step 26 and the above-described process is repeated.

In step 31, the created truth value data is edited and stored in the file memory 14.

Furthermore, in step 32, the truth value data (truth table) is outputted as a list to the printer 15 as required.

In this way, input data processing ends (end)
.

(2) Test data creation process (see Figure 4) Step 41
-43 are similar to steps 21-23 described above. That is, control data read through the card reader 12 is decoded, stored in the program memory 13, and the process is repeated until the final card is reached.

In step 44, the truth value data stored in the file memory 14 through the input data processing described above is read in code units. In the next step 45, it is determined whether reading of the truth value data has been completed (YES) or not (No).
If the determination result is YES, the process proceeds to step 51, and if the determination result is NO, the process proceeds to step 46. In step 46, the even parity (bits) is calculated for each air address, and the number of bits at the "H" level is calculated, and the calculated data is temporarily stored in the file memory 1.
Store in 4.

In the next step 47, the "H" level focus number is calculated for each output bin and stored in the file memory 14. In step 48, a leak measurement value is calculated and stored in the file memo 4, and in step 49, test data for all bits is created. In the next step 50, it is determined whether the data created in steps 46 to 49 corresponds to the final address (YES) or not (NO), and if the determination result is YES, the process returns to step 44, and if the determination result is NO. If so, the process returns to step 46 and the above-described process is repeated.

In step 51, bin information is created and temporarily stored in the file memory 14. Next step 5
In step 2, all the created bit test data are edited, and the even parity (bit) data calculated in step 46, the focus number data of the “1(” level) and the output pin calculated in step 47 are edited. The parity test data is edited based on the "H" level bit number data for each data, and the edited test data is stored in the file memory 14.Furthermore, in step 53, the entire parity test data is sent to the printer 15 as necessary. A list of bit test data and parity test data is output.In this way, the test data creation process is completed (end).

As explained above, in this embodiment, when creating test data, in addition to the conventional creation of all-bit test data, based on even parity calculated for each address (parity test data The test data for the mask ROM integrated circuit is obtained by adding data on the number of bits of "H level" for each output pin.In this case, data access is performed by creating an all-bit data file. Since it is possible to use it as is and only require a small addition of processing such as parity calculation, the processing time can be suppressed to about 10% or less compared to the conventional method.

FIG. 5 shows an example of the parity test data creation process in FIG. 4.

In the example shown in the figure, the number of output bits is 8 (output bins OO to 07).
The case is shown below. In the figure, the part PD surrounded by the broken line is ~
PD represents parity test data; PD.

is the data of the edited even parity bit, PD2 is the data of the number of "H" level bits in the even parity, PD
3 indicates data on the number of "H" level bits for each output pin. In the example shown in the figure, the number of parity bits (PD5) is 178 of the total number of bits (truth data), but generally, when the number of output bits is n, the number of parity bits is 1/n of the total number of bits. becomes.

In other words, two test files, one for truth table data and one for parity data, can be created in slightly more time than it takes to create one test file for all bits (truth table) data. . This makes it possible to significantly shorten the test time for mask ROM integrated circuits, which in turn makes it possible to shorten the delivery time of mask ROM integrated circuit products.

Furthermore, when calculating even parity, if a bit inversion occurs in the even parity due to erroneous processing, for example, in the example of FIG. 5, two addresses #0000
If a bit inversion occurs in the even parity of #0001, the data PD of the even parity bit is rlool
ooloJ, so the data PDt with the number of bits of 0H" level in even parity is the same data "3" as in the case of the original correct data r01010010J.
is instructed. This cannot be said to be preferable from the viewpoint of reliability of tests using parity data.

To cope with this, in this embodiment, as described above, data PD of the number of "H" level bits for each output pin is created as parity test data together with other data PD+ and PDz. Therefore, when bit inversion occurs in even parity, data PD! Even if the data PD specifies the same data, the data PD specifies different data, so the reliability of the test using parity data can be improved.

Note that although the above-described embodiment is configured to calculate even parity (bits) from truth value data, it may be configured to calculate odd parity (bits) conversely.

Also, in the above embodiment, the number of "H" level bits is calculated for each output bin, but the same effect can be obtained even if the number of "H" level bits is calculated conversely. .

[Effects of the Invention] As explained above, according to the method for creating test data for a mask ROM integrated circuit of the present invention, test time can be significantly shortened by using test data created based on the method. This contributes to shortening the delivery time of mask ROM integrated circuit products and is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a principle diagram showing a method for creating test data for a mask ROM integrated circuit according to the present invention, FIG. 2 is a diagram showing an example of a system configuration for implementing the present invention, and FIG. FIG. 4 is a flowchart showing the test data creation process according to the present invention performed by the CPU in FIG. 2; FIG. 5 is a diagram showing an example of the parity test data creation process in FIG. 4. , FIG. 6 is a flowchart showing a typical test data creation procedure for a mask ROM integrated circuit. (Explanation of symbols) D,...Write data, D2...Truth value data, D,...All bit test data created, D4...
Calculated parity data, D3''...Edited all-bit test data, D41...Edited parity test data, D,...Final test data, l...Truth value data 2... A process of creating all bit test data and calculating parity data. 3... A process of editing all bit test data and parity test data.

Claims (1)

[Claims] 1. Write data to mask ROM integrated circuit (D_1
), create truth value data (D_2) for each output pin of the mask ROM integrated circuit in address units (1)
, the mask ROM based on the created truth value data.
Create all-bit test data (D_3) of the integrated circuit, and calculate parity data (D_4) for each address (2), edit the created all-bit test data, and edit the calculated parity data. (3), and both the edited all-bit test data (D_3') and parity test data (D_4') are transferred to the mask RO.
A method for creating test data for a mask ROM integrated circuit, characterized in that the test data is final test data (D_5) for an M integrated circuit. 2. When calculating the parity data, calculate the data of the number of logically high level or logically low level bits for each output pin of the mask ROM integrated circuit, and use the calculated data as the final 2. The test data creation method according to claim 1, wherein the test data is added to the test data.