JPH02210833A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02210833A JPH02210833A JP3151189A JP3151189A JPH02210833A JP H02210833 A JPH02210833 A JP H02210833A JP 3151189 A JP3151189 A JP 3151189A JP 3151189 A JP3151189 A JP 3151189A JP H02210833 A JPH02210833 A JP H02210833A
- Authority
- JP
- Japan
- Prior art keywords
- film
- titanium nitride
- contact hole
- tungsten
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 28
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 20
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 16
- 239000010937 tungsten Substances 0.000 claims abstract description 16
- 238000009792 diffusion process Methods 0.000 claims abstract description 10
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 5
- 239000001301 oxygen Substances 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 4
- 238000000034 method Methods 0.000 claims description 20
- -1 oxygen ions Chemical class 0.000 claims description 4
- 239000000758 substrate Substances 0.000 abstract description 9
- 230000004888 barrier function Effects 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 238000010438 heat treatment Methods 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 238000004544 sputter deposition Methods 0.000 abstract description 4
- 239000002019 doping agent Substances 0.000 abstract description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract 1
- 229910052698 phosphorus Inorganic materials 0.000 abstract 1
- 239000011574 phosphorus Substances 0.000 abstract 1
- 238000002844 melting Methods 0.000 description 8
- 230000008018 melting Effects 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 229910000967 As alloy Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 150000002926 oxygen Chemical class 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に微細化され
た半導体素子の高アスペクト比のコンタクト部に、高精
度に、信頼性、耐熱性のある金属膜を埋め込む方法に関
する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, and in particular, it can be applied to a high aspect ratio contact portion of a miniaturized semiconductor element with high precision, reliability, and heat resistance. It relates to a method of embedding a certain metal film.
半導体装置の微細化、高密度化に伴い、素子の電気特性
の高信頼化が強く求められている。素子間を結合する技
術、あるいは素子のコンタクト孔に金属膜を埋め込む配
線技術としては、従来蒸着法、あるいはスパッタ法等が
用いられていた。As semiconductor devices become smaller and more densely packed, there is a strong demand for higher reliability in the electrical characteristics of elements. Vapor deposition, sputtering, or the like has conventionally been used as a technique for coupling elements or as a wiring technique for burying a metal film in a contact hole of an element.
しかるに、上述した従来の方法により微細化された高ア
スペクト比のスルーホール部を金属膜で埋め込もうとし
た場合、該スルーホール部は完全には埋め込まれず、ス
ルーホール段部において該金属膜の切断が生じ、素子の
信頼性を著しく低下させていた。そこで最近金属膜をＣ
ＶＤ法で堆積して配線切れを防止しようという研究がな
されるようになった。ところが下地がＳｉ基板等の拡散
層の場合には、高融点金属膜堆積後の高温熱処理工程に
おいて高融点金属膜は半導体拡散層と激しいシリサイド
化反応を生じ、コンタクトを破壊するという欠点があっ
た。また拡散層中のドーパントが熱処理を施すことによ
り高融点金属中に拡散することによりコンタクト抵抗が
増大するという欠点もあった。However, when attempting to fill a high aspect ratio through-hole portion miniaturized by the above-mentioned conventional method with a metal film, the through-hole portion is not completely filled, and the metal film is partially filled at the stepped portion of the through-hole. Cutting occurred, significantly reducing the reliability of the device. Therefore, recently metal films have been
Research has begun to be carried out to prevent wiring breakage by depositing it using the VD method. However, when the base is a diffusion layer such as a Si substrate, there is a drawback that the high-melting point metal film undergoes a violent silicidation reaction with the semiconductor diffusion layer during the high-temperature heat treatment process after depositing the high-melting point metal film, destroying the contact. . Another disadvantage is that the dopant in the diffusion layer is diffused into the high melting point metal by heat treatment, resulting in an increase in contact resistance.
本発明の目的はこれらの欠点を除去し、金属と半導体間
で相互拡散の生じない、電気的に低抵抗で安全な半導体
装置の製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate these drawbacks and provide a method for manufacturing a semiconductor device that is electrically low in resistance and safe, in which interdiffusion does not occur between metal and semiconductor.
上記目的を達成するため、本発明による半導体装置の製
造方法は、半導体素子の拡散層上に絶縁膜を形成し、そ
の絶縁膜の一部に開口したコンタクト孔に金属を埋め込
む半導体装置の製造方法において、フォトレジストをマ
スクに薄い窒化チタン膜を全面に形成する工程と、その
上から該窒化チタン膜中に酸素イオンを高濃度にイオン
注入する工程と、リフトオフ法により窒化チタン膜を該
コンタクト孔の中にのみ残す工程と１選択タングステン
ＣＶＤ法により該窒化チタン上にのみタングステン膜を
形成する工程と、その上を通る金属配線を形成する工程
とを具備するものである。In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes forming an insulating film on a diffusion layer of a semiconductor element, and filling a contact hole opened in a part of the insulating film with metal. , a step of forming a thin titanium nitride film on the entire surface using a photoresist as a mask, a step of implanting oxygen ions at a high concentration into the titanium nitride film from above, and a lift-off method to form the titanium nitride film in the contact hole. The method includes a step of forming a tungsten film only on the titanium nitride by a one-selective tungsten CVD method, and a step of forming a metal wiring passing over the tungsten film.
次に１本発明について図面を参照して説明する。 Next, one embodiment of the present invention will be explained with reference to the drawings.
第１図（ａ）、 （ｂ）、 （ｃ）は本発明の一実施例
を説明するための工程を工程順に示す断面図である。FIGS. 1(a), 1(b), and 1(c) are cross-sectional views showing steps for explaining an embodiment of the present invention in order of process.
まず、第１図（ａ）に示すように、半導体素子が形成さ
れた３−１５Ωｌのシリコン基板１１上に絶縁膜１２を
形成する。しかる後に絶縁膜１２の所望の領域にリソグ
ラフィ工程を通して、フォトレジスト１３をマスクに絶
縁膜１２のバターニングを行い、コンタクト孔１４を開
孔する０次に第１図（ｂ）に示したようにレジスト１３
を残した状態で全面にヒ素等のドーパントをイオン注入
し、拡散層１５を形成する。First, as shown in FIG. 1(a), an insulating film 12 is formed on a silicon substrate 11 of 3-15 Ωl on which a semiconductor element is formed. Thereafter, a desired region of the insulating film 12 is subjected to a lithography process to pattern the insulating film 12 using the photoresist 13 as a mask, and a contact hole 14 is formed as shown in FIG. 1(b). resist 13
A dopant such as arsenic is ion-implanted into the entire surface while leaving a diffusion layer 15.
この拡散層は予め形成しておいたものを使用してもよい
。その後、バリアメタルとして３００−２０００人の窒
化チタン膜１６をスパッタ法で全面に形成する。This diffusion layer may be formed in advance. Thereafter, a 300-2000 titanium nitride film 16 is formed as a barrier metal over the entire surface by sputtering.
次に拡散に対するバリア効果を高めるためにその上から
該窒化チタン膜１６中に１ＯＥ１６／ａＪ以上の酸素イ
オン注入１７をシリコン基板との界面近傍に高濃度にイ
オン注入する。その後、リフトオフ法によリコンタクト
孔１４の底部の半導体基板１１上にのみ該窒化チタン膜
１６を残し、残りの金属膜は除去する１次に、注入され
たイオンの活性化を行うため＋１１００−９００°Ｃの
熱処理を施す、この状態でタングステン膜成長前のバリ
ア膜の形成が完成する。この酸素イオン注入１７の注入
により形成した窒化チタンの効果により極めて優れた電
気特性が実現できる。引き続き第１図（ｃ）に示したよ
うに選択ｗ −ｃｖ。Next, in order to enhance the barrier effect against diffusion, oxygen ions 17 of 1OE16/aJ or more are implanted into the titanium nitride film 16 at a high concentration near the interface with the silicon substrate. Thereafter, by a lift-off method, the titanium nitride film 16 is left only on the semiconductor substrate 11 at the bottom of the re-contact hole 14, and the remaining metal film is removed. A heat treatment is performed at 900° C. In this state, the formation of the barrier film before tungsten film growth is completed. Due to the effect of the titanium nitride formed by this oxygen ion implantation 17, extremely excellent electrical characteristics can be achieved. Subsequently, select w-cv as shown in FIG. 1(c).
法を用いてコンタクト孔内にだけ０．３−１．５ｐのタ
ングステン膜１８をコンタクト孔の上部まで埋め込む６
次に、アルミ膜、又はタングステン膜等の金属膜をスパ
ッタ法により半導体基板上に全面に形成した後、パター
ニングして、上部配線層１９を形成する。このようにし
、て作製された窒化チタン、タングステンの二層の埋め
込み構造からなる金属層は、コンタクト孔の下部に形成
された窒化チタン膜１６のバリア効果により配線形成後
の８００−９００℃程度の高温の熱処理にも耐えること
ができる。A tungsten film 18 of 0.3-1.5p is buried only in the contact hole to the top of the contact hole using a method 6.
Next, a metal film such as an aluminum film or a tungsten film is formed over the entire surface of the semiconductor substrate by sputtering, and then patterned to form an upper wiring layer 19. Due to the barrier effect of the titanium nitride film 16 formed at the bottom of the contact hole, the metal layer made in this way and consisting of a two-layer buried structure of titanium nitride and tungsten is heated to about 800-900°C after wiring formation. It can also withstand high temperature heat treatment.
以上、素子のコンタクト孔を高融点金属膜で埋め込む耐
熱素子の場合に関して述べたが１本発明は通常のアルミ
ニウム配線の場合にも適用される。The above description has been made regarding the case of a heat-resistant element in which the contact hole of the element is filled with a high melting point metal film, but the present invention is also applicable to the case of ordinary aluminum wiring.
この場合には、埋め込む金属がタングステンに代り、ア
ルミニウムになるがコンタクト孔の下部に形成する金属
は上述した窒化チタン膜の他にタングステン、モリブデ
ン、チタン等の高融点金属でもよい０本構造の素子では
、従来アルミニウムとシリコンの間で問題になっていた
アロイスパイクや元素の相互拡散等のマイグレーション
問題が解決することにより素子の長期信頼性が飛躍的に
向上する。In this case, the metal to be buried is aluminum instead of tungsten, but the metal formed at the bottom of the contact hole may be a high melting point metal such as tungsten, molybdenum, or titanium in addition to the titanium nitride film mentioned above. By solving migration problems such as alloy spikes and interdiffusion of elements, which have traditionally been a problem between aluminum and silicon, the long-term reliability of the device will be dramatically improved.
本発明の方法により形成された配線は通常のＬＳＩの作
製工程に従い最終工程へと進められ、高信頼性の配線を
具備した集積回路が完成する。The wiring formed by the method of the present invention is advanced to the final process according to the normal LSI manufacturing process, and an integrated circuit having highly reliable wiring is completed.
尚、実施例では高融点金属としてタングステン膜を用い
たが、モリブデン、タンタル等の高融点金属膜あるいは
低温で使用するデバイスの場合にはアルミニウムを用い
てもよい、また、アルミニウムの場合にはバリアメタル
としてタングステン。In the examples, a tungsten film was used as the high melting point metal, but a high melting point metal film such as molybdenum or tantalum, or aluminum may be used for devices used at low temperatures. Tungsten as metal.
モリブデン等の高融点金属の他それらのシリサイドを用
いてもよい。In addition to high melting point metals such as molybdenum, silicides thereof may also be used.
以上、説明したように本発明によれば、半導体基板上の
コンタクト孔に二層構造の金属層を形成することにより
、安定で高信頼性の配線構造を得ることができ、集積回
路の設計、製造に多大な効果がある。As described above, according to the present invention, by forming a two-layer metal layer in a contact hole on a semiconductor substrate, a stable and highly reliable wiring structure can be obtained, and it is possible to design an integrated circuit. It has a great effect on manufacturing.
第１図（ａ） 、 （ｂ） 、 （ｃ）は本発明の一実
施例を工程順に示す断面図である。FIGS. 1(a), 1(b), and 1(c) are sectional views showing an embodiment of the present invention in the order of steps.
Claims (1)
縁膜の一部に開口したコンタクト孔に金属を埋め込む半
導体装置の製造方法において、フォトレジストをマスク
に薄い窒化チタン膜を全面に形成する工程と、その上か
ら該窒化チタン膜中に酸素イオンを高濃度にイオン注入
する工程と、リフトオフ法により窒化チタン膜を該コン
タクト孔の中にのみ残す工程と、選択タングステンＣＶ
Ｄ法により該窒化チタン上にのみタングステン膜を形成
する工程と、その上を通る金属配線を形成する工程とを
具備することを特徴とする半導体装置の製造方法。(1) In a semiconductor device manufacturing method in which an insulating film is formed on the diffusion layer of a semiconductor element and metal is embedded in a contact hole opened in a part of the insulating film, a thin titanium nitride film is coated over the entire surface using a photoresist as a mask. a step of implanting oxygen ions at a high concentration into the titanium nitride film from above, a step of leaving the titanium nitride film only in the contact hole by a lift-off method, and a step of selectively implanting the titanium nitride film into the contact hole.
A method for manufacturing a semiconductor device, comprising the steps of: forming a tungsten film only on the titanium nitride by method D; and forming a metal wiring over the tungsten film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3151189A JPH02210833A (en) | 1989-02-10 | 1989-02-10 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3151189A JPH02210833A (en) | 1989-02-10 | 1989-02-10 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02210833A true JPH02210833A (en) | 1990-08-22 |
Family
ID=12333237
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3151189A Pending JPH02210833A (en) | 1989-02-10 | 1989-02-10 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02210833A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5312774A (en) * | 1991-12-05 | 1994-05-17 | Sharp Kabushiki Kaisha | Method for manufacturing a semiconductor device comprising titanium |
| US5379718A (en) * | 1992-12-25 | 1995-01-10 | Sharp Kabushiki Kaisha | Method for forming a titanium thin film |
| US5700717A (en) * | 1995-11-13 | 1997-12-23 | Vlsi Technology, Inc. | Method of reducing contact resistance for semiconductor manufacturing processes using tungsten plugs |
-
1989
- 1989-02-10 JP JP3151189A patent/JPH02210833A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5312774A (en) * | 1991-12-05 | 1994-05-17 | Sharp Kabushiki Kaisha | Method for manufacturing a semiconductor device comprising titanium |
| US5379718A (en) * | 1992-12-25 | 1995-01-10 | Sharp Kabushiki Kaisha | Method for forming a titanium thin film |
| US5700717A (en) * | 1995-11-13 | 1997-12-23 | Vlsi Technology, Inc. | Method of reducing contact resistance for semiconductor manufacturing processes using tungsten plugs |
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