JPH02210865A - Field-effect transistor of e/d constitution - Google Patents

Abstract

PURPOSE:To make it possible to realize easily a field-effect transistor(FET) of an E/D constitution by a method wherein insulators or semiconductors having a large energy forbidden band width are arranged between a semiconductor layer and a Schottky electrode, which are provided on a semiconductor substrate, in a lattice type. CONSTITUTION:In a Schottky junction between a gate 5 and an active layer 2, lattices 3 are formed of an insulating film and channels in bulk parts under the lattices 3 are opened and shut by depletion layers 8, which are generated by metal-semiconductor junctions in the gaps of the lattices 3, from their sides. By changing the widths of the lattices 3, an adjustment of a threshold voltage is also possible. Moreover, as the layers 8 of a metal semiconductor field-effect transistor (a MESFET) are formed thin on the side of a source of the transistor and are formed thick on the side of a drain of the transistor, the threshold voltage varies by the mask-alignment deviation of the lattices 3 with the gate 5 in a current direction if the lengths of the lattices 3 are shorter than a gate length. Therefore, the lengths of the lattices 3 are made longer than the gate length. Thereby, the method of E/D constitution which is easily applicable even to the MESFET is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a field effect transistor whose active layer is formed by epitaxial growth.

[Conventional technology]

Field-effect transistors (FETs) whose active layer is formed by epitaxial growth usually have only one threshold voltage from one active layer, so they are composed of enhancement type (EFET) and depletion type (DFET). As a conventional example of an E/D structure that is difficult to adopt an E/D configuration, see Japanese Patent Application Laid-open No. 168677/1982 and Proceedings of the 49th Japan Society of Applied Physics Academic Conference (1988, Autumn), page 938. A method of realizing the depletion type by increasing the thickness of the spacer layer between the channel and the gate is discussed.

[Problem to be solved by the invention]

A method of realizing an E/D configuration by thickening the spacer layer between the gate and the channel and realizing a depletion field effect transistor is to create a FET with a spacer layer (
There is a problem that only HEM'l', DMT, IGFE"l', etc.) can be applied.

For example, if you try to realize a depletion mode MESNET (DFET) by bringing an undoped semiconductor to the interface between the gate and active layer in a MESFET,
There is a problem in that special measures are required to separate the active layer and the undoped layer.

Furthermore, if the undoped semiconductor layer and the active layer are a heterojunction, if the undoped layer has a small bandgap, the Schottky characteristic will deteriorate, and if the undoped layer has a large bandgap, a depletion type will form. There is a problem that makes it difficult.

The purpose of the present invention is to provide an E
/Dvt formation method is provided.

[Means to solve the problem]

Enhancement type MESF)! : In '1', the channel is closed by the depletion layer generated at the Schottky junction between the gate and the active layer, so if an insulator is used instead of the Schottky electrode, it will be pinned at the interface and no current will flow. Since current flows in the bulk, it becomes possible to realize a depletion type. However, since the interface between a compound semiconductor and an insulator is unstable due to the process, it is difficult to obtain a threshold voltage with good reproducibility. If it is, the logic amplitude becomes too large and there is a problem that it becomes unbalanced with EFE'l'.

Therefore, in one aspect of the present invention, a lattice is formed using an insulating film, and the channel in the bulk portion under the lattice is laterally opened and closed by a depletion layer generated at the metal-semiconductor junction of Rlft of the lattice. It is also possible to adjust the threshold voltage by changing the width of the grid.

[Effect]

In the E/D elliptical configuration path, E F E "I" is used for driving and DFET is used for load, so high conductance is required for EFET, but 1) There is no need to increase the conductance of FET. Therefore, the conditions for forming the active layer are set to optimize E F E '1'.

In order to realize a DF'ET, a lattice is formed between the active layer and the gate metal using an insulator or an n-type semiconductor with a large forbidden band width. The gate bias is Ov under the grating.
However, since a channel is created through which current flows, a depletion layer extends from the gap in the lattice (the interface where the gate and active layer meet).

In order to close this channel, a gate bias must be applied in the negative direction.

The threshold voltage of the D FET can be adjusted by the size of the grid.

〔Example〕

FIGS. 1 and 2 show a GaAg MESFET (
Metal Semiconductor Field Effect Transistor: Matal SemiconductorFi
FIG. 2 shows a cross-sectional view of an element part of the ELDS Effect Transistor.

In both figures, (a) is a cross-sectional view from the front, and (b) is a cross-sectional view from the side. It is possible to use other compound semiconductors other than the present example, and MIS (metal insulator semicon ring: Metal In5ula
tor Sem1conductor) FET structure is also possible.

Enhancement type F E '1'' in Figure 1, which is a normal FET.Depression type F in Figure 2
In ET, there is a width Q of 2 pm between the gate metal and the active layer.
, 5iOz3 with a height of 0.1 pm is formed into a striped lattice with a pitch of 0.8 μm.

The length of the grating is such that a margin of 0.3 μm or more is set aside for the gate length in consideration of the accuracy of phosphorography.

In addition to 5iOz, the lattice 3 is made of an insulator such as CnFz,
It is also possible to form using a semiconductor with a large energy bandgap such as n-type AQGaAs.

J1+N4 is formed by selective epitaxial growth on the active layer 2 formed by epitaxial growth, but it can also be formed by ion implantation.

The threshold voltage of a depletion type FET (DF'ET) shifts to the negative side as the width of the grid 3 becomes larger, so that it becomes possible to adjust the threshold voltage.

The depletion layer of MESFET is thin on the source side and thick on the drain side, so if the length of the grating is shorter than the gate length, the threshold voltage will vary due to misalignment of the masks in the current direction of the grating 3 and gate 5. Therefore, the length of the grating 3 was decided to be larger than the gate length.

FIG. 3 shows the I-V characteristics of the DFE '1'. FIG. The figure (b) shows the I as -V gs characteristics, and in region (1), the channel under the lattice and the channel under the lattice gap are both on. In region (II), the channels below the lattice gaps are in the off state and the channels below the lattice are in the on state. In region (nt), both are in the off state.

The conductance in the region (11) increases as the lattice gap becomes smaller.

4 and 5 show the process steps for a single E/D MESFET divided into EFET, D)'E'r, and (a) to (d) are front views.

On the semi-insulating GaAs substrate 1, MBE (Molecular Beam Epitaxy) is applied.
amEpitaxy), the carrier density is approximately I x 10
"cs-" n-GaAs 2 is grown to a thickness of about 40 nm. If the grating 3 were to be formed of n-type AflGaAs, A n Ga As would also be grown, but this is not used here as there is no suitable selective etching solution.

5ins3 is deposited to a thickness of about 80 nm by plasma CVD (chemical vapor deposition) (a).

Leave only the area that will become the active layer or resistance layer.

It is scraped off by wet etching using another hydrofluoric acid solution (b).

In the enhancement type FET, 5i on the active layer 2
023 is removed. In a depletion type FET, the length is 0.4 of the gate length plus the alignment margin of the lithography process.
A striped grating 3 with a width of 0.2 μm is formed by adding 0.2 μm.
Formed at intervals of 8 μm (C).

As Schottky gate metal, WSio, number about 2
After depositing by 0 nm sputter deposition, only the gate part is left and the other parts are removed by dry etching to form a goo layer (d).The cross-sectional view at this time is (d).
e).

A 5ift (l!l wall) is formed next to the gate, and using this sidewall as a mask, n+GaAs4 is selectively grown by metal organic chemical vapor deposition (MOCVD).In order to form the ohmic electrode 6, the electrode 5iOz was deposited to a thickness of 300nm as a spacer layer in areas other than 6, and 60nm of AuGe alloy (Ge weight ratio 8%) was deposited to form an ohmic electrode.
m vacuum evaporated, and W (
After depositing 10 nm of tungsten (Tungsten) and Ni (Nickel), 120 nm of Au on top of the vacuum evaporation, the spacer layer was lifted off, leaving the ohmic electrode 6, and alloying heat treatment was performed at 400°C for 5 minutes in a hydrogen atmosphere. (f)
Here, to simplify the drawing, the spacer layer is omitted.

Thereafter, a wiring process is performed to complete a field effect transistor having an E/D configuration according to the present invention.

In Fig. 6 and Fig. 7, the peterojunction M E S F' E
In this embodiment, in order to improve the Schottky characteristic between the active layer 2 and the gate 7, an undoped A Q Ga A s 7 is placed between the active layer 2 and the gate 7. Sandwiched by 12 nm.

Figure 1.6 is an enhancement type, normal heterojunction MESFET. FIG. 7 shows a depletion type, and it is also possible to use n-type GaAs, Si, etc. for the grating 3.

The process step is MBE growth on a semi-insulating GaAs substrate or buffer layer.

Undoped AnGaAtx, n-GaAs in order 15.
After stacking 12.30 nm, only the active layer is left by wet etching.The carrier concentration of the active layer is 3XI.
O” (!l-6, and n-GaAs in the lattice is 10”
It is determined in the range of l to 10 cm-, taking into consideration the threshold value required for the circuit. Since the height is 30 nm, the lattice is completely depleted due to the Schottky barrier of the gate, and no parasitic channel is formed.

Use undoped AfiGaAs7 as a stopper.

In the enhancement type, n-GaAs3 is completely removed, and in the depletion type, a lattice is formed with n-GaAg3.

A Schottky gate 5 is formed, and a source/drain 4 is formed.
The process steps for forming the ohmic electrode 6 and attaching the ohmic electrode 6 are the same as in the previous embodiment, and the wiring step is performed to complete the E/D structure heterojunction FET of this embodiment.

〔Effect of the invention〕

In FETs whose active layers are formed by epitaxial growth, it is difficult to manufacture FETs with different threshold voltages, but the present invention has the effect of easily realizing F l'' T with an E/D configuration.

Furthermore, the present invention applies not only to the Schottky junction type T' E 'r but also to the one-inversion type (7)
'1', IGFHT, etc.).

Since the threshold voltage of a DFET can be adjusted by changing the size of the grid, it is also possible to form FETs with three or more different threshold voltages on the same substrate.

The method of sandwiching the insulating film as a lattice at the interface between the gate and the active layer prevents the logic amplitude from becoming too large compared to the case of sandwiching the film across the entire surface.

[Brief explanation of the drawing]

FIGS. 1 and 2 show the E/D configuration of one embodiment of the present invention.
Front cross-sectional view (a) and side cross-sectional view (
b), FIG. 3 is a DF E 'l' (7) I-V characteristic diagram, and FIGS. 4 and 5 are GaAsMH according to an embodiment of the present invention.
Side cross-sectional view showing the process steps of 3FET (a ” d
) and a front sectional view (e”f), and FIGS. 6 and 7 are a front sectional view (a) and a side sectional view (a) and a side sectional view ( b)
It is. 1... Semiconductor substrate or buffer layer, 2... n −
Q a As (active layer), 3... Lattice-shaped insulator or semiconductor, 4... fig-GaAs (lease/drain), 5... Schottky gate, 6... A
u-Ge (source/drain metal), 7... undoped AjGaAs. 8...Depletion layer. 1P-4 5th mouth 3rd day ((Z)

Claims (1)

[Claims] 1. An enhancement type field effect transistor having a Schottky electrode on a first semiconductor layer formed on a semiconductor substrate, and the first semiconductor layer and the Schottky electrode formed on the same semiconductor substrate. and a depletion type field effect transistor formed by arranging an insulator or a semiconductor with a large energy bandgap in a lattice shape between the two. 2. An enhancement type field effect transistor formed on a semiconductor substrate, having a second semiconductor having a larger forbidden band width than the first semiconductor on a first semiconductor, and having a Schottky electrode thereon; A field effect transistor having an E/D configuration, comprising a depletion type field effect transistor made by arranging an insulator or a semiconductor in stripes on the second semiconductor layer.