JPH02210880A - Quantum interference effect element - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention relates to the structure of a quantum interference effect element, and aims to facilitate the manufacturing process and to use LS as a planar structure.
The present invention relates to a device structure that facilitates the implementation of integrated integration.

[Conventional technology]

A conventional example of a quantum interference effect element is the IEDM Technical Digest.

1986, pp. 76-79 (IEDM, Tac
QUIT (Quantum Interference Transistor) as discussed in J. H., Dig, (198B), pp76-79)
(transistor).

[Problem to be solved by the invention]

There are the following problems in putting the above QUIT into practical use as it is.

(1) Ga A grown on the AllGaAss layer
Since the s layer tends to have "distortion", the first channel and the second
In devices that use minute channels, such as zero-line devices, where the quality of the crystals in the channels in each stage may not be the same, distortion in the crystal has a large effect.

(2) When considering the process steps, 1
After growing the first stage channel and the A Q GaAs layer on it and etching the A Q GaAs layer, the second stage channel and the A Q GaAs layer on it are grown, and the crystal growth process is completed. This is not preferable in terms of throughput since it is necessary to perform the process twice or more.

(3) A that separates the first channel and the second channel
The problem is misalignment between the GaAs and the gate.

(4) If the number of input terminals is N, the number of channels that branch into one is (N+1), and the crystal growth process is also (N+
1) times are required. This makes it difficult to provide multiple inputs in practice.

[Means to solve the problem]

In order to use homogeneous QUIT channels with multiple branches, it is necessary to use a device fabrication that allows multiple channels to be formed simultaneously in the same crystal growth process.For this reason, in the present invention, In this case, a plurality of channels are arranged on the same plane. This has the advantage that the crystal growth process does not need to be divided into two or more steps, and the throughput of device manufacturing is improved.

In order to create a plurality of branched channels, for example, the middle of one channel can be carved out using a technique such as FIB (Focused Ion Beam) or dry etching. This also has the effect of allowing multiple inputs.

After making a hole in the middle of one channel to make it branch, separate gate electrodes must be provided in order to give different potentials to each branched channel. Considering the alignment accuracy in
One possible method is to separate the gate at the same time as the channel is branched. Considering the ease of the process, the latter method is advantageous.

[Effect]

According to the present invention, since a part of the channel forming layer in one channel is removed to form a non-channel region and the channel is branched, each channel becomes homogeneous and the reproducibility of the operating voltage is improved. . Furthermore, this eliminates the need to perform the crystal growth process for channel formation more than once, improving device fabrication throughput. Furthermore, since the branched channels are arranged on the same plane, the construction of the integrated circuit is facilitated.

Simplifying the process steps also facilitates the configuration of multiple inputs.

By cutting the gate together when cutting the channel, it becomes possible to give separate potentials to the single branched channel. Also, whereas conventional QUIT has a gate on only one channel, each channel has a gate, so it is also possible to perform quantum interference using one-dimensional electron gas or a two-dimensional electron gas in a state close to it. becomes.

Note that conductance can be increased by making the planar dimension of the non-channel region as small as possible.

As an upper limit of operable dimensions, in the length direction, this device will operate even if the non-channel region is provided up to the front of the source/drain electrode.As for the upper limit in the width direction, there are two cases depending on the difference in the depth of the non-channel region. Divided into. That is, when the non-channel region penetrates the entire channel layer, the dimension is such that the depletion layer channel extending from the end of the channel layer in the width direction by its surface level is blocked and no current flows.

In addition, if the non-channel region does not penetrate the channel layer, the originally small current, that is, the current that flows under the non-channel region without being branched, increases as the width of the non-channel region increases, and finally modulation by gate voltage becomes difficult. This dimension is the upper limit.

Further, the planar shape of the non-channel region may be any shape such as an ellipse, a quadrilateral, an ellipse, or the like.

〔Example〕

As an example of the present invention, Ga As and A Q Ga
Q U I T (Quantu
mInterferenceTransltor)
The element is shown.

It is also possible to use a combination of other semiconductors or a combination of a semiconductor and an insulator.

FIG. 1 shows the device structure, and FIG. 2 shows the manufacturing process steps.

Fig. 1(a) is a schematic perspective view, and Fig. 1(b) is a top view.Although the sectional view taken along line AA' in Fig. 1 is omitted in Fig. 1(c), Actually, in order to lower the source/drain 4 contact resistance, ions are implanted into the source/drain 4 part to remove the undoped GaAs directly below.
+ -GaAg.

The distance between the source and drain must be small enough for electrons to conduct pallidically.

When the temperature is 4.2, the mobility of two-dimensional electron gas is 10'
c+j/V-s, and the Fermi velocity is 107cn
/s, the drain voltage is several mV
Therefore, the channel length must be 1 μm or less. Just set the operating temperature a little higher.

The channel length must also be shortened accordingly.

The channel width must be small enough that electrons occupy only the lowest subband states.

Considering the depletion layers at both ends, it is necessary to set the electron concentration IQ11 to 0.1 μm or less. If the electron concentration is increased, the length must be shortened accordingly.

Undoped GaAs that conducts electrons in a parisistic manner
If a hole 9 is made in the center of the channel 1 by FIB or X-ray lithography, the electrons will diverge before the hole 9 and merge again to form #148M.

Since the width of the channel is also sufficiently small, electrons conduct along the heterointerface with N-AQGaAg2, which has a low potential, while maintaining monochromaticity.

In the region of the branched channel, two-dimensional electron gas is generated at the hetero interface due to the influence of n + -GaAs3, but by applying a negative voltage to the gates 5 and 6, the two-dimensional electron gas can be eliminated. Therefore, n+ −G a A
The carrier concentration of s3 is determined by the operating setting voltage of the gate 5.6.

(0) shows a cross-sectional view of a channel branched by hole 9. Since electrons pass through a low potential region near the hetero interface, hole 9 does not need to completely divide 1-GaA5l, and N- Cut AQGaAs2 to 1-GaA+sl
It is enough to expose the

When the gate voltages are respectively Vol and Vow, the gate length is the gate length, the electron velocity in one direction is V, and the blank constant is h, the electrons that are conducted along the hole and synthesized are at each gate. It is modulated by voltage and has a phase difference φ expressed by a linear equation.

φ=2 x a (VOR-Vat)/v・h
-(1) Therefore, the conductance between the source and drain is affected by the periodicity coefficient expressed by the following equation (see FIG. 11(d)).

G=Go(1+<cosφ>) ・(2)
Here, 〉 indicates the collective average of electrons.

When ignoring the effects of parasitic resistance, GO is proportional to the source-drain voltage. However, since electrons are conducted pallisically, the upper limit of the drain voltage is about 30 mV, which is smaller than the optical phonon energy. The upper limit of the gate voltage is the voltage that generates two-dimensional electron gas, and n A Q
Adjustments are made by the concentrations of GaAs2 and n+ GaAs3.

According to the present invention, it is possible to produce a semiconductor element that generates a phase difference φ by applying a voltage to the two gates 5 and 6 and performs conductance modulation. Pallistic conduction and modulation without carrier accumulation make it possible to have extremely high operating frequencies.

FIG. 2 shows one process step of the present invention.

Approximately 3 undoped Oa ts 1 on a semi-insulating substrate
0 nm, n-AQGaAs2 about 20 nm, n
+ -G a As 3 to about 10 nm, MBE (Molecular Beam Epitaxy: Molecular
(a), leaving only the gate, source, and drain parts, n+ -G
By wet etching after removing the aAs3.

A heterojunction active layer of @O, OS μm and length 1 μm is processed (b).

The one covered with WSi (tungsten silicide) as Schottky metal, leaving only the gate part (Q)
It is a diagram.

A hole 9 is made in the center of the channel by FIB or x#I lithography, and the gate 5 and n+-GaAg3°H-AQ GaAs2 are separated at the center to form a non-channel region.

Here, the size of the hole 9 is determined from the source to the current direction.
It can be made larger up to the drain electrodes 7 and 8, but in the width direction, the smaller the width, the better the characteristics of the element, so n÷-
Make it as small as possible to the extent that G a As 3 can be completely separated.

In order to lower the contact resistance, the source/drain portions are ion-implanted to form an n-type intermediate layer 10, as shown in FIG. 3(d).

By attaching source and drain ohmic electrodes and performing a wiring process, the quantum interference effect device according to the present invention is completed.

FIG. 3 shows an embodiment using a process step different from that in FIG. 2, and in this embodiment, it is possible to reduce the parasitic resistance of the source and drain.

Undoped GaAs 1,n-A Q on semiconductor substrate
After growing GaAs2 (a), the n-^ΩGaAs2 is etched at the source/drain portion, and the undoped GaAs 1 is etched down to the device dimensions (b).The device dimensions are a channel length of 0.5 μm,
The channel width is 0.06 pm and the height is 0.03 μm.

(c
), and after depositing WSi to a thickness of approximately 0.03 μm as a gate, only the gate portion is left (d).

After making a hole 9 in the center of the channel, a sonis drain ohmic electrode is deposited and a wiring process is performed.

(Effects of the invention) A quantum interference effect device can be easily produced by the present invention 1
The branched channels are crystallically homogeneous and AQ
Since it is not necessary to grow a GaAs layer on the GaAs layer, it is easy to obtain a high quality device.

Furthermore, since the number of crystal growth layers can be reduced, not only the process becomes easier, but also the reproducibility of device characteristics is improved.

In addition, a plurality of gates are required, which is disadvantageous for an element having four or more terminals, but since the potential of each channel can be set individually, it has the effect of increasing reliability. Furthermore, in the present invention, all branched channels are arranged on the same plane, making it easier to construct an integrated circuit.

[Brief explanation of the drawing]

No. 11 is a perspective view, a plan view, and a cross-sectional view of a quantum interference effect element according to an embodiment of the present invention, and a characteristic diagram showing the relationship between the potential difference between two gate potentials and the conductance. Cross-sectional view showing an example device fabrication process, No. 3v4
FIG. 3 is a cross-sectional view showing a process of another embodiment of the present invention. 1-i-GaAs, 2-n-ARGaAs
, ;l・n+-GaAs, 4...n÷-GaAs,
5... High melting point metal (first gate), 6... High melting point gold m (second gate), 7.8... Source or drain electrode, 9... Hole, 10... Ion implantation n layer, 11...Sin! or SiN, 12... Schottky metal. 74'1IllA Todorohan+ /1% ball-game l
concave eye

Claims (1)

[Claims] 1. A first semiconductor layer that is not intentionally doped on a semiconductor substrate and serves as a channel, and a first semiconductor layer that has an n-type conductivity type to provide a low potential region in the first semiconductor layer. 1. A quantum interference effect element, comprising: a second semiconductor layer; the second semiconductor layer is notched to branch electrons flowing through a channel and join them again; 2. The semiconductor device according to claim 1, wherein the second
The gate is divided by a cut in the semiconductor layer of
A quantum interference effect element characterized by applying a different potential to each branched channel.