JPH02210902A - Integrated high frequency amplifier - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

(Industrial Application Field) The present invention relates to a high frequency amplifier, and particularly to an integrated high frequency amplifier integrated on the same semiconductor substrate.

[Conventional technology]

An example of a conventional high-frequency amplifier is "Electronic Information and Communication Handbook 1988 Edition, Section 2 Microwave/Millimeter Wave Circuit Components, 5.4 Examples, Figure 64.7-39 pages (549 pages)"
is shown. For example, as shown in FIG. 9, a conventional high-frequency amplifier circuit includes a matching circuit including a MOSFET, a capacitor for cutting off direct current, and a strip line. More specifically, in order to match the output impedance of the front-stage MOSFET and the input impedance of the rear-stage MOSFET, series and parallel strip lines of about a quarter wavelength are used. At 3 GHz, the above-mentioned quarter wavelength is 6.
When the dielectric material is 7 mm and Sin, it reaches 12°7 mm. When these high frequency amplifier circuits are integrated on the same semiconductor substrate, the size of the semiconductor chip is determined by the length of these strip lines. Therefore, conventional high-frequency amplifier circuits have been mainly integrated when the operating frequency is higher than 3 GHz, and when the operating frequency is below 3 GHz, so-called hybrid mounting has been performed in which individual transistors are mounted on a printed circuit board or the like. In such a case as well, the matching inductor has a circuit configuration that uses an inevitably existing transmission line, that is, a strip line, as shown in FIG. In that case, the characteristics of the circuit configuration are that the front stage MOSF
A bonding wire or a strip line is used to connect the output of the ET and the input of the subsequent MOSFET, and the impedance conversion effect of the strip line is used.

[Problem to be solved by the invention 1] In the above-mentioned conventional technology, especially when the frequency is 3GH2 or less, the above-mentioned inductor is a strip line that is longer than the semiconductor chip and is used by bending it multiple times, or an integrated inductor is used. . As a result, the inductor becomes a thin and long line, and its series resistance becomes too large to be ignored. In particular, in the case of power amplifiers where large high-frequency currents flow,
The problem is that the series resistance significantly reduces the efficiency of the power amplifier. Furthermore, if a wide line is used to reduce the series resistance, there is a problem in that the area of the inductor becomes significantly large. A first object of the present invention is to integrate the above-mentioned high-frequency amplifier circuits on the same semiconductor substrate, and furthermore, from the integrated high-frequency amplifier,
The goal is to reduce the integration of the inductor as much as possible, or to make it unnecessary to integrate it into a semiconductor chip, thereby providing an integrated high-frequency amplifier with extremely low loss of high-frequency power using a limited chip area. It is to be. Furthermore, the threshold voltage of MOSFETs has large manufacturing variations, which causes variations in the characteristics of integrated amplifiers, particularly in power gain and efficiency. Therefore, a second object of the present invention is to absorb variations in the threshold voltage of the integrated high-frequency amplifier, thereby providing an integrated high-frequency amplifier with less variation in power gain and efficiency. Furthermore, the capacitance of the bonding pads used to connect the integrated high-frequency amplifier with external circuits has the problem of making the input selectivity higher than necessary and increasing the dispersion of the input standing wave ratio. There is a problem in that the loss of output power is large and the efficiency is reduced. Accordingly, a third object of the present invention is to reduce the capacitance of the bonding pad, which poses a problem in the manufacture of the integrated high frequency amplifier. It is an object of the present invention to provide an integrated high-frequency amplifier that reduces variations in input standing wave ratio and reduces power efficiency. [Problems to be Solved by the Invention] In the above-mentioned prior art, the frequency is particularly 3 G f (2
In the following cases, the inductor is a strip line that is longer than the semiconductor chip and is bent multiple times, or an integrated inductor is used. As a result, the inductor becomes a thin and long line, and its series resistance becomes too large to be ignored. In particular, in the case of power amplifiers where large high-frequency currents flow,
The problem is that the series resistance significantly reduces the efficiency of the power amplifier. Furthermore, if a wide line is used to reduce the series resistance, there is a problem in that the area of the inductor becomes significantly large. Therefore, a first object of the present invention is to integrate the above-mentioned high-frequency amplifier circuit on the same semiconductor substrate, and further to reduce the integration of the above-mentioned inductor from the integrated high-frequency amplifier as much as possible, or to integrate the above-mentioned inductor into a semiconductor chip. The object of the present invention is to provide an integrated high-frequency amplifier with extremely low loss of high-frequency power using a limited chip area. Furthermore, the threshold voltage of MOSFETs has large manufacturing variations, which causes variations in the characteristics of integrated amplifiers, particularly in power gain and efficiency. Therefore, a second object of the present invention is to absorb variations in the threshold voltage of the integrated high-frequency amplifier, thereby providing an integrated high-frequency amplifier with less variation in power gain and efficiency. Furthermore, the capacitance of the bonding pads used to connect the integrated high-frequency amplifier with external circuits has the problem of making the input selectivity higher than necessary and increasing the dispersion of the input standing wave ratio. There is a problem of increasing output power loss and reducing efficiency. Therefore, a third object of the present invention is to reduce the capacitance of the bonding pad, which is a problem in the manufacture of the integrated high frequency amplifier. It is an object of the present invention to provide an integrated high-frequency amplifier that reduces variations in input standing wave ratio and reduces power efficiency.

[Means to solve the problem]

In order to achieve the above first object, in the present invention,
The impedance conversion effect of the strip line is not used, and instead, the impedance conversion ratio of the first capacitor and the second capacitor is used. In other words, the front stage MOSFE
The first capacitor is used to cut off the output of T and the input of the subsequent stage MOSFET, and the second capacitor is the first capacitor.
The input capacitor of the FET or the capacitor at the input terminal is used as a second capacitor, and its impedance conversion ratio is used. Therefore, the first capacitor is
Conventionally, capacitance as large as possible has been used for the purpose of blocking DC and passing high-frequency signals, but in the present invention, in addition to the above-mentioned DC blocking, a finite capacitance is provided. . Further, in the present invention, a single inductor is connected between the midpoint of the first capacitor and the second capacitor and the ground or ground terminal for tuning. This inductor uses a bonding wire that connects the semiconductor chip to an external circuit. Furthermore, in the present invention, the first and second capacitors are integrated in two layers on the same semiconductor substrate, and two capacitors can be formed in one capacitor area. Chip area can be reduced. In addition, regarding the second capacitor, there is an advantage that the input capacitance of the subsequent MOSFET can be used, and the insufficient amount can be integrated. Therefore, the first capacitor may be larger than the second capacitor. In that case, they are integrated in multiple layers on the same semiconductor substrate, and their parallel connection is used as the first capacitor. Furthermore, in the present invention, a MOSFET with a small channel width to which only direct current is applied is formed on the same semiconductor chip, and the gate bias voltage is set so that the drain current becomes a predetermined value. - The same voltage as the bias voltage is used as the gate bias voltage of the MOSFETs for the above-mentioned front-stage and rear-stage amplifiers. Further, in the integrated high-frequency amplifier of the present invention, a PN junction is formed directly under the bonding pad and a reverse bias is applied to this to reduce the capacitance directly under the bonding pad.

[Operation] In the means for achieving the first object, the inductances of the first capacitor, the second capacitor, and the bonding wire are tuned so that the output of the subsequent amplifier becomes large at a predetermined frequency. be done. That is, the first capacitor and the second capacitor are
The output impedance of m is determined to match the input impedance of the subsequent stage amplifier, and the selectivity at the windowed frequency is determined to be large. Therefore, crotch matching is achieved with an integrated capacitor and only one bonding wire, and high frequency amplifier integration is easily achieved without integrating inductances with large losses. Furthermore, since the first capacitor and the second capacitor are stacked, there is no series-parallel parasitic capacitance or inductance. Therefore, their impedance characteristics are similar and act as ideal impedance converters. Furthermore, since a MOSFET to which only direct current is applied has a small channel width, its drain current is extremely small. Therefore, in order to set the drain current to a predetermined value,
A predetermined control voltage can be applied via a large resistor, which does not require a large amount of power.Also, within the same semiconductor chip, the variation in threshold voltage is small, so the same gate bias voltage can be used. However, the bias current of the small MOSFET and the bias current of the front-stage and rear-stage amplifiers are proportional to each other. Therefore, the bias currents of the front-stage and rear-stage amplifiers can be set with small power. Furthermore, if the PN junction directly under the bonding pad is reverse biased, the capacitance of the PN junction becomes smaller due to the expansion of the depletion layer. Since this capacitance is in series with the capacitance directly below the bonding pad, the overall capacitance can be reduced. [Examples] The present invention will be explained below with reference to Examples. FIG. 1 shows a basic embodiment of the invention. Here, 1 is a semiconductor chip that integrates two MOSFETs whose source is grounded and the first capacitor, and 2 is a bonding/bonding chip.
In the inductance of the wire, 5 is an input terminal, 6 is an output terminal, and 8 is a power supply terminal. Here, the matching of the output impedance of the front-stage MOSFET and the input impedance of the rear-stage MOSFET is based on the first
The ratio of the capacitance component of the capacitor 3 and the above-mentioned input impedance is used, and the inductance 2 of the gate bonding wire of the subsequent MOSFET is used for tuning. Therefore, in the present invention, even after the semiconductor chip is manufactured, the frequency band can be adjusted by the inductance 2 of the bonding wire. Conventionally, the capacitor 3 has been required to be as large as possible for the purpose of blocking direct current and passing high frequency signals between the front stage and the rear stage. However, in the present invention, corresponding to the impedance conversion ratio,
It can be sufficiently small and can be easily integrated into the same semiconductor chip. 7 is a bias terminal, which is also used as a fine adjustment terminal, so that the frequency adjustment by the inductance 2 of the bonding wire can be further finely adjusted after the amplifier is manufactured. In FIG. 2, a second capacitor 4 is added when the input capacitance of the subsequent MOSFET is small. If the capacitance is small, the inductance needs to be large in order to tune to a specific frequency. Since the length of the bonding wire is limited, it is difficult to increase its inductance. In such a case, increasing the capacitance can eliminate the increase in inductance. This allows tuning to be performed without increasing the length of the bonding wire. In FIG. 3, when the inductance 2 of the bonding wire is insufficient, the insufficient inductance 2 is integrated into a semiconductor chip. Here, 9 is an inductor formed on the surface of the same semiconductor chip using a wiring metal such as aluminum or a gate forming material such as polysilicon or molybdenum. In FIG. 4, a dual gate MOSFET is used instead of the MOSFET described above, and the gain is controlled by the voltage applied to the second gate terminal 10. This eliminates the variation in input impedance that occurs when the gain is controlled by the gate bias voltage of the MOSFET. Furthermore, since the second gate operates as a grounded gate, oscillation is likely to occur unless it is grounded with low impedance. In order to prevent this, in this embodiment, the capacitor 11 is integrated within the same semiconductor chip. This eliminates the impedance of the bonding wire that would exist if it were grounded outside the semiconductor chip, thereby reducing the grounding impedance. In the case of a dual gate MOSFET, the on-resistance is large, resulting in a decrease in power efficiency. Therefore, the front stage can be a dual gate MOSFET, and the rear stage with a large output power can be a MOSFET with high power efficiency. FIG. 5 shows two differential MOSFETs with a common source and the differential MOSFET described above, instead of the MOSFET described above.
It consists of a MOSFET whose drain is connected to the source of
A differential amplifier is used in which the source of the MOSFET is grounded. Here, 32.33 is the first capacitor, and 34.35 is the second capacitor. Moreover, input terminals 5-2 and 5-3 are differential input terminals. Complementary signals are input. The input terminal 5-1 controls the bias current of the differential MOSFET and the gain of the differential amplifier. Also, if one of the input terminals 5-2 or 5-3 is grounded and a signal is input from the other, complementary signals can be obtained from the output of the differential amplifier, so this can be used as a preamplifier of the push-pull amplifier. It can also be used as Furthermore, if a signal is input from the input terminal 5-1 and the input terminal 5-2 or 5-3 is used as a complementary DC bias terminal, the dual gate MO
This is a gain control amplifier with a larger gain control range, especially a larger gain attenuation, than an SFET. FIG. 6 shows an integrated MOSFET 12 having a channel width of about 1/1/100 to 1/100 of that of the front-stage and rear-stage amplifiers for the purpose of bias control. The gate of the MOSFET 12 is connected to the drain, and a bias control voltage is applied from a bias control terminal 15 through a resistor 13. The voltage applied to the MOSFET 12 is applied by a resistor 14 to the gates of the front-stage and rear-stage amplifiers. When the bias control voltage is higher than the threshold voltage of the MOSFET 12, the MOSFET is
Determine the current of 12. The bias currents of the front-stage and rear-stage amplifiers are set in proportion to the current of MOSFET I2, and these are the so-called idling currents of the front-stage and rear-stage amplifiers. This uses the current mirror effect of MOSFET, and can reduce variations in power gain and efficiency when the amplifier is operating at high output. On the other hand, the bias control voltage is
When the voltage is lower than the threshold voltage of 2, the current of the MOSFET 12 becomes almost zero, and the bias control voltage is directly applied to the gates of the front and rear stage amplifiers. That is, when the voltage is lower than the threshold voltage, the front-stage and rear-stage amplifiers simultaneously become class C amplifiers, and the power gain can be significantly attenuated. As a result, the integrated high-frequency amplifier according to the present invention is not affected by variations in threshold voltage when performing high-output operation. Gain attenuation control necessary for the high frequency amplifier can be reliably performed. Figure 7 shows a dual gate M○5FET as the front stage amplifier.
, which shows the case where a MOSFET is used as a post-stage amplifier. The bias voltage of the first gate of the front stage dual gate MO5FET is fixed, and the gain control of the front stage is performed by the second gate applied voltage. Since the input impedance of the previous stage is thereby fixed, it is possible to eliminate fluctuations in input matching that occur in the case of gain control by the first gate. In this example, the front stage dual gate MOSFE
For the purpose of controlling the gain of T, a dual-gate MOSFET 16 having a channel width of about one-several to several-hundredths of that of the previous-stage dual-gate MOSFET is integrated. The first gate of the dual gate MOSFET 16 is set to a high potential supplied from the bias terminal 19, the second gate is connected to the drain, and the resistor 1 is connected to the bias control terminal 15.
A bias control voltage is applied via 7. The second gate voltage of the dual gate MOSFET 16 is applied to the second gate of the preceding stage dual gate MOSFET by a resistor 18. The applied voltage of the second gate is the dual gate MOSFET
Since the power amplifier operates with a large amplitude, gain control is realized by the magnitude of the saturation current. Since the front-stage dual-gate MOSFET and the dual-gate MOSFET 16 are integrated on the same semiconductor chip, the saturation current has a proportional relationship corresponding to the reduction ratio of the dual-gate MOSFET. Therefore, the second gate voltage that gives the saturation current of the dual gate MOSFET 16 is obtained, and this is applied to the previous dual gate MOSFET 16.
The saturation current can be set by applying it to the second gate of the OSFET. That is, the bias control voltage is set to V
apc, the value of resistor 17 is R17, dual gate MOS
If the drain voltage of FET16 is Vx, if the first gate is set to a high potential, the dual gate MO
The saturation current Ix of SFET16 is (Vap c-Vx)
/R17. Therefore, Ix is approximately determined by the bias control voltage, resulting in the second gate applied voltage V
x is also determined. This voltage is the previous stage dual gate MOSF
This is the voltage applied to the second gate of ET. As a result, the saturation current, and therefore the gain, can be determined by the bias control voltage without being affected by threshold voltage variations. FIG. 8 shows an embodiment of the cross-sectional structure of the present invention. In this embodiment, two lateral offset gate MOSFETs 20. 21 and 1st. A second capacitor is formed. Here, the P-type high concentration silicon substrate is grounded, and the second capacitor connects the P-type cavity concentration diffusion layer 25 passing through the P-type low concentration layer to a lower electrode,
The surface protective film is a dielectric, and the gate forming film 22 selectively formed on the surface protective film is an upper electrode. Further, the first capacitor has an upper electrode 22 of the second capacitor as a lower electrode, a first insulating film covering the lower electrode as a dielectric, and a first insulating film selectively formed on the upper part of the insulating film. The first metal film 23 is used as an intermediate electrode, the second insulating film covering the upper part of the intermediate electrode 23 is used as a dielectric, and the second metal film 24 is selectively formed on the upper part of the insulating film.
The intermediate electrode 23 is configured as a two-part electrode, and the intermediate electrode 23 is
It is connected to the drain of the ET 20, and the lower electrode 22 and the upper electrode 24 are connected to the gate of the subsequent MOSFET 21. Furthermore, since the series resistance component of the first and second capacitors is small, the tuning selectivity may become higher than necessary. This adds a slight resistance component. That is, by reducing the area of the P-type cavity concentration diffusion M25, the series resistance of the second capacitor can be added. Further, the P-type cavity concentration diffusion layer 25
By controlling the concentration to be low, the series resistance of the second capacitor can be optimally finely adjusted during the manufacturing process. In addition, in this embodiment, the first capacitor is configured above the second capacitor and is shielded from grounding, so the proportion of the output of the previous stage MOSFET 21 that is grounded is extremely small, and almost all outputs are grounded. is transmitted to the second capacitor. Furthermore, since the second capacitor can be a capacitor between the gate and source of the subsequent MOSFET 21, the shortfall can be made up by integrating the second capacitor, and the second capacitor can generally be made smaller than the first capacitor. In this embodiment, a first capacitor is integrated on a small second capacitor by a two-layer structure, so that the chip area can be reduced. Further, when the first capacitor cannot obtain the necessary capacitance even with the two-layer structure, an insulating film covering the upper part of the second capacitor is selectively formed to be thin. In addition, in this embodiment, input and output bonding
By forming N-type diffusion layers 27 and 28 directly under the pads 29 and 30 and keeping them at a high potential by the input gate bias voltage or the output drain voltage, the input and output bonding pads and the semiconductor This reduces the capacitance that exists between the substrates. This prevents the selectivity of the input matching circuit from becoming unnecessarily high, and further reduces output power loss caused by current flowing through the bonding pad capacitance at the output terminal. . FIG. 10 is the chip pattern of FIG. 5. Here 36.3711.43 are striped M
OSFET is shown. 36 and 38 are differential MOSFETs of the front-stage differential amplifier, 37 and 39 are bias current control MOSFETs of the front-stage differential amplifier connected in parallel, 40 and 42 are differential MOSFETs of the rear-stage differential amplifier, and 41 and 4
3 is a MOSFET for bias current control of the rear-stage differential amplifier connected in parallel. Further, 32 and 33 are first capacitors, and 34 and 35 are second capacitors. The first capacitors 32 and 33 are stacked on top of the second capacitors 34 and 35, respectively, so that the chip area can be reduced. Further, the capacitors are arranged symmetrically with respect to the center of the chip in correspondence with the positive and negative phases of the differential amplifier, and the front-stage amplifier and the rear-stage amplifier are separated by the arrangement positions of the capacitors, and the chip This sufficiently suppresses the feedback of unnecessary internal signals. This eliminates the instability that occurs in high gain amplifiers. FIG. 11 shows a circuit diagram of an embodiment in which a high frequency amplifier is constructed using an integrated high frequency amplifier chip according to the present invention. Here, 1 corresponds to that shown in FIG. 36 is an input terminal, 37 is an input matching circuit, 38 is an output terminal, and 39 is an output matching circuit. Matching between the front stage and the rear stage is performed by a pre-designed integrated capacitor and the inductance of the bonding wire 2. The variations in the integrated capacitor and bonding wire can be finely adjusted by the capacitor 40. As described above, by using the integrated high frequency amplifier chip according to the present invention, it is extremely easy to perform crotch matching, and the frequency band can be changed over a wide range. In addition, if you use the present invention, you can simply arrange the power supply terminal and fine adjustment terminal.
Two or more stages of amplifiers can also be constructed in the blank position of one stage amplifier, and the substantial increase in area is small. the result,
The area conventionally required for the interstage matching circuit and bias circuit can be significantly saved.

【Effect of the invention】

In this way, the present invention uses impedance conversion using integrated capacitors, so strip lines,
Alternatively, compared to the case of using inductance, power loss due to the resistance component can be reduced. Furthermore, the present invention has the advantage that only one inductor needs to be connected for tuning, which simplifies the adjustment. As this inductor, a bonding wire with a small resistance component that connects the semiconductor chip to an external circuit can be used, and high frequency power loss can be reduced. Furthermore, since the existing bonding wires are used, there is no need for integration on the semiconductor chip, and the chip area can be reduced. Further, since the bonding wire is connected to an external circuit, there is an advantage that even after the amplifier is manufactured, errors in the inductance and variations in semiconductor chip manufacturing can be finely adjusted from the external circuit. Furthermore, in the integrated high-frequency amplifier of the present invention, the capacitor is integrated in multiple layers, and the subsequent MOSFET
There is an advantage that the input capacitance of ET can be used, and the chip area can be reduced. Furthermore, the integrated high-frequency amplifier of the present invention can absorb variations in the threshold voltage of MOSFETs during semiconductor chip manufacturing, thereby reducing variations in power gain and efficiency during high-output operation. ,
Gain control can be performed. Also dual gate MO
Using SFETs or differential amplifiers can eliminate input impedance fluctuations associated with gain control.
As a result, the manufacturing yield of the input matching circuit can be improved. Furthermore, in the integrated high-frequency amplifier of the present invention, since the capacitance directly under the bonding pad is reduced,
The selectivity of the input matching circuit does not become higher than necessary, thereby making it possible to reduce variations in input standing wave ratio and reduce output power loss. As described above, the present invention facilitates the integration of high-frequency tank H bases particularly in the frequency range below 3 GHz, and also facilitates adjustment, improves manufacturing yield, and improves power efficiency. , the gain control function has been improved, and high stability has been maintained.

[Brief explanation of the drawing]

1 to 7 are circuit diagrams of a high frequency amplifier according to an embodiment of the present invention. FIG. 8 is a sectional view of the circuit of FIG. 2, FIG. 9 is a circuit diagram of a conventional high frequency amplifier circuit, and FIG. FIG. 5 is a plan view showing the chip pattern of the circuit, and FIG. 11 is a layout diagram of circuit element groups showing an example of use of the integrated amplifier circuit chip of the present invention. Explanation of symbols 1... Semiconductor chip, 2... Bonding wire, 3.4... Capacitor, 5.5-1.5-2.5-
3...Input terminal, 6.6-1.6-2...Output terminal, 7.7-1.7-2.7-3...Bias terminal, 8
．． 8-1.8-2... Power supply terminal, 9... Inductor, 10... Second gate terminal, 11... Capacitor,
12...MOSFET, 13.14...Resistance, 15
...Bias control terminal, 16...Dual gate MO5FET, 17.18...Resistor, 19...Bias terminal, 20.21...MOSFET, 22...
Gate forming film, 23.24... Metal film, 25.26.
...P-type foveal concentration diffusion layer, 27.28...N-type diffusion layer,
29.30... Bonding pad, 31... Strip line, 32.33... First capacitor, 34.35... Second capacitor, 36... Input terminal, 37...・Input matching circuit, 38...output terminal,
39...Output matching circuit. 40... Capacitor Figure 2 Figure 9 Figure F $7 Figure 7 ρ f''-2, r-/

Claims (1)

[Claims] 1. MOSFET or dual gate MOSFET
T, or two differential MOSFEs with a common source
and a first capacitor, each of which includes at least two amplification sections each including a differential amplifier configured with a MOSFET whose drain is connected to the source of the differential MOSFET, and a first capacitor;
In a high frequency amplifier in which one end of the capacitor is connected to an output terminal of a front-stage amplifier section and the other end is connected to an input terminal of a rear-stage amplifier section, the amplifier section and the capacitor are formed on the same semiconductor substrate; An integrated high-frequency amplifier characterized in that a tuning circuit is formed by the input impedance of a rear-stage amplifier section and a bonding wire connected to the input terminal. 2. Claim 1, wherein a second capacitor is formed between the input terminal of the latter-stage amplifying section of the semiconductor substrate and ground.
The integrated high frequency amplifier described in Section 1. 3. The integrated high-frequency amplifier according to claims 1 and 2, wherein the front and rear stages of the amplifying section are configured with MOSFETs, dual gate MOSFETs, or a combination of the differential amplifiers. 4. Claims 1, 2 and 4, wherein a third capacitor is formed on the semiconductor substrate and connected between the second gate of the dual gate MOSFET or the control gate of the differential amplifier and ground. The integrated high frequency amplifier according to item 3. 5. Claims 1, 2, and 3, wherein an inductor is formed on the semiconductor substrate and connected between the input terminal of the post-stage amplification section and the bonding pad of the input terminal.
and the integrated high-frequency amplifier according to item 4. 6. A plurality of resistors and a third amplifying section are formed on the semiconductor substrate, and the gate terminals of the amplifying section and each of the amplifying sections are connected by the resistor, and the third amplifying section has a plurality of resistors. Claims 1, 2, 3, and 4 set a voltage equal to or proportional to the gate bias voltage as the gate bias voltage of each of the amplification sections.
6. The integrated high-frequency amplifier according to paragraphs 1 and 5. 7. The first capacitor has a first metal film selectively formed on the top of the surface protection film of the semiconductor substrate as a lower electrode, an insulating film covering the top of the metal film as a dielectric, and the insulating film as a dielectric. A second metal film selectively formed on the upper part of the second metal film is configured as an upper electrode, the upper electrode is connected to the output terminal of the first stage amplification part, and the lower electrode is connected to the input terminal of the second stage amplifier part. Claims 1 and 2 are characterized in that:
6. The integrated high-frequency amplifier according to items 1, 3, 4, 5, and 6. 8. The integrated high frequency amplifier according to claim 7, wherein the lower electrode is formed using a gate forming film. 9. An integrated high frequency amplifier according to claims 7 and 8, characterized in that the insulating film is selectively formed thin. 10. The lower electrode of the first capacitor is selectively formed on the surface protection film of the semiconductor substrate using a gate formation film, and the first insulating film covering the upper part of the gate formation film is formed as a dielectric. a first layer formed as a body and selectively formed on the top of the insulating film.
A metal film is used as an intermediate electrode, a second insulating film covering the upper part of the metal film is used as a dielectric, a second metal film selectively formed on the upper part of the insulating film is configured as an upper electrode, and the intermediate Claims 1, 2, 3, and 4, wherein the electrode is connected to the output terminal of the front-stage amplifier, and the lower electrode and the upper electrode are connected and connected to the input terminal of the rear-stage amplifier. 6. The integrated high-frequency amplifier according to paragraphs 5 and 6. 11. The semiconductor substrate is composed of a P-type low concentration layer grown on a P-type high concentration silicon substrate, and the second or third capacitor is a portion reaching the P-type high concentration silicon substrate from the surface of the semiconductor substrate. A highly concentrated P-type diffusion layer is formed, this is used as a lower electrode, a surface protection film covering the surface of the semiconductor substrate is used as a dielectric, and a metal film is selectively formed on the top of the surface protection film. An integrated high frequency amplifier according to claims 1 to 10, wherein the upper electrode is an upper electrode. 12. The integrated high frequency amplifier according to claim 11, wherein in the second capacitor, the area of the heavily doped P-type diffusion layer is smaller than the area of the upper electrode. 13. Claim 11, characterized in that in the second capacitor, the concentration of the P-type high concentration diffusion layer is lower than the concentration of the P-type high concentration diffusion layer in the third capacitor. The integrated high frequency amplifier described. 14. Form an N-type diffusion layer directly under the bonding pad corresponding to the input terminal of the front-stage amplifier section or the output terminal of the rear-stage amplifier section, and make the potential of the N-type diffusion layer higher than the potential of the semiconductor substrate. An integrated high-frequency amplifier according to any one of claims 1 to 13, wherein the integrated high-frequency amplifier is maintained at a potential. 15. A first arrangement group consisting of the above-mentioned front-stage amplification section, a second arrangement group consisting of the above-mentioned rear-stage amplification section, and the first arrangement group,
Claim 1 characterized in that a third arrangement group is formed of the second and third capacitors, and the third arrangement group separates the first arrangement group and the second arrangement group. 15. An integrated high-frequency amplifier according to items 1 to 14.