JPH0221148B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a CMOS semiconductor device.

In conventional MOS semiconductors, the source and drain
Gate channel length less than 2μm using As
Although NMOS type semiconductor devices are mass-produced,
In a CMOS type semiconductor device equipped with a Pch transistor using ¹¹ B for the source and drain and an Nch transistor using ³¹ P for the source and drain, the source/drain diffusion depth (hereinafter referred to as xj)
Because it is difficult to control the depth of the gate channel, the gate channel length limit due to punch-through is approximately 3 μm. However, CMOS semiconductor devices have the disadvantage that they are inferior to NMOS semiconductor devices in terms of miniaturization.

In order to eliminate the drawbacks of the prior art, the present invention enables shallow control of xj and includes a Pch transistor using ¹¹ B for the source and drain and an Nch transistor using ³¹ P for the source and drain. Provided is a CMOS type semiconductor device having a gate channel length of 2 μm or less.

Hereinafter, it will be explained in detail using examples.

Figure 1 shows the manufacturing process of polycrystalline silicon gate CMOS ^{semiconductor} devices according to the ^conventional method and the present invention. ₂ thermal diffusion annealing, while according to an embodiment of the invention the surface layer is annealed by lamp heating for a few seconds.

FIG. 2 is a cross-sectional view of a polycrystalline silicon gate Pch transistor, and the diffusion depth of the source and drain is indicated by xj (B). The source and drain are made of boron B.

FIG. 3 is a cross-sectional view of a polycrystalline silicon gate Nch transistor, and the diffusion depth of the source and drain is indicated by xj (P). Source and drain are phosphorus P
It is formed of.

The cross-sectional structure of the transistor of the present invention is xj (B)
and xj (P) are respectively xj of the conventional transistor
(B) and xj (P) about 0.5μm shallower, so Pch,
The gate length for both Nch and Nch is reduced by about 1 μm, making it possible to create a CMOS semiconductor device with a gate length of just under 2 μm.

Figures 4 to 9 show the sheet resistance and xj when lamp heat annealing is performed for several seconds at a surface wafer temperature of 1300°C, and are compared with the sheet resistance and xj when _N2 thermal diffusion annealing is performed. are doing.

Figure 4 shows the correlation between the sheet resistance and lamp heating time when boron 4×10 ¹⁵ cm ^-2 40 KeV was implanted. 7 is the sheet resistance when N ₂ thermal diffusion annealing is performed at 1000°C for 20 minutes, which is approximately 27Ω/□ or less. If lamp heating is performed for 6 seconds, it will be comparable to thermal annealing.

Figure 5 shows the correlation between the sheet resistance and lamp heating time when 4×10 ¹⁵ cm ^-2 40 KeV of phosphorus was injected. 8 is the sheet resistance when N ₂ thermal diffusion annealing is performed at 1000°C for 20 minutes, which is approximately 22Ω/□. If lamp heating is performed for 6 seconds, it will be comparable to thermal annealing.

FIG. 6 shows the correlation between xj (B) and lamp heating time when boron 4×10 ¹⁵ cm ⁻² ·40 KeV was implanted. 9 is xj (B) when N ₂ thermal diffusion annealing is performed at 1000° C. for 20 minutes, which is approximately 1 μm.

FIG. 7 shows the correlation between xj (P) and lamp heating time when 4×10 ¹⁵ cm ⁻² 40 KeV of phosphorus was injected.
10 is xj (P) when N ₂ thermal diffusion annealing is performed at 1000° C. for 20 minutes, which is approximately 1 μm.

Figure 8 shows xj (B) when boron is 4×10 ¹⁵ cm ^-2
This is a correlation between the energy and the implantation energy, and lamp heating can provide xj (B) 0.4 μm.

FIG. 9 shows the correlation between xj (P) and implantation energy when phosphorus is 4×10 ¹⁵ cm ⁻² , and lamp heating can provide xj (P) of 0.4 μm.

In FIGS. 8 and 9, annealing was performed with lamp heating for 6 seconds.

From the above, by using lamp heating annealing, activation is greater than N ₂ diffusion annealing, and the diffusion depth of both Pch and Nch transistors can be controlled to xj = 0.4 μm, and gates of both Pch and Nch are less than 2 μm. It is possible to provide a CMOS type semiconductor device with a long time.

[Brief explanation of drawings]

Figure 1: Manufacturing process of CMOS semiconductor devices according to the conventional method and the present invention, Figure 2: Polycrystalline silicon gate
Cross-sectional structure diagram of a Pch transistor. Figure 3: Cross-sectional structural diagram of a polycrystalline silicon gate Nch transistor.
Figures 4 to 9...Experimentally measured values of sheet resistance and xj when lamp heating annealing is performed. 1... Polycrystalline silicon, 2... Pch source/drain boron diffusion layer, 3... Element isolation region, 4...
...nWell region, 6...Nch source/drain phosphorus diffusion layer region, 7... _N2 thermal diffusion annealing 1000℃20
Sheet resistance when performing 8... _N2 thermal diffusion annealing at 1000℃ for 20 minutes,
9... _N2 thermal diffusion annealing at 1000℃ for 20 minutes xj (B), 10... _N2 thermal diffusion annealing at 1000℃
xj (P) after 20 minutes.

Claims (1)

[Claims] 1. The impurity diffusion depth of the source and drain constituting the integrated circuit is 0.5 μm or less, and the gate width is
In a method for manufacturing an insulated gate field effect transistor element of 2 μm or less, boron ions are implanted into the source and drain, and then the sheet resistance of the impurity diffusion layer is reduced by lamp heating.
A method for manufacturing an insulated gate field effect transistor element, comprising a step of annealing to 27Ω/□ or less. 2 The impurity diffusion depth of the source and drain constituting the integrated circuit is 0.5 μm or less, and the gate width is
In a method for manufacturing an insulated gate field effect transistor device with a size of 2 μm or less, after ion-implanting phosphorus into the source and drain, the sheet resistance of the impurity diffusion layer is reduced to 27% by heating with a lamp.
1. A method for manufacturing an insulated gate field effect transistor device, comprising a step of annealing to Ω/□ or less. 3 The impurity diffusion depth of the source and drain constituting the integrated circuit is 0.5 μm or less, and the gate width is
In a method for manufacturing an insulated gate field effect transistor element of 2 μm or less, boron is ion-implanted into the source and drain of a P-ch transistor, phosphorus is ion-implanted into the source and drain of an N-ch transistor, and then impurity diffusion is performed by lamp heating. A method for manufacturing an insulated gate field effect transistor element, comprising the step of annealing the sheet resistance of the layer to 27Ω/□ or less.