JPS601862A - Manufacturing method of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an MO8 type B"BT. It is particularly effective in highly integrated LSIs comprising complementary MO8 FETs.

Conventionally, in the manufacture of LSIs consisting of silicon gate complementary MO8 FITs, the source and drain regions of P-type M@5-NETs are coated with a high concentration (1, OX1016crn'').
2 or more) 11B ions are implanted and the Le type M0 day FIT
High concentration (t OX I D
Rough 5A8 ions are implanted over "cm-", and the ion-implanted layer is annealed at high temperature for a long time (for example, 1000° C. for 30 minutes). However, although 11B and 7688 are 100% activated by high-temperature and long-time annealing, the 11B implanted diffusion layer spreads laterally and in depth, resulting in a large junction depth of 0.5 μm or more, and the source This caused the punch-through of the drain and prevented the miniaturization of the P-type MO8-FFiT. In addition, in the T6A8 ion implantation layer, the mass of the implanted ions is larger than that of the silicon substrate, which causes crystal defects due to ion collision during implantation, and the leakage current in the curved junction is large.In order to recover the defects and reduce the leakage current, High temperature annealing is absolutely necessary. Therefore, with the conventional complementary M08/F'FtT manufacturing method, miniaturization is not possible and it is not possible to manufacture an L8 process with less leakage current due to defects.

The present invention eliminates such conventional drawbacks, and provides a complementary N0/F structure that has less leakage current due to defects and can be miniaturized.
The purpose is to provide a method for manufacturing ET.

In order to achieve the above object, in the present invention, P-type M□5-F
BF in the source/drain region of IT.

31p ions were implanted into the source/drain regions of the n-type MO8 FIT at a concentration of 1x1ot'□-2 or more, and the ion-implanted layer was annealed at a temperature below 900°C. A feature of this method is that it is performed at a low temperature for a short time of less than 1 minute.

Hereinafter, it will be explained in detail using examples. Table 2 is a flow chart of conventional complementary MO8 FF1iT manufacturing. Well field film, gate film, and PolyS
After forming the i-gate electrode, P-type MO8@Fl! IIB ions are implanted into the sonis self-drain region of iT, and N-type MO8.
After implanting 16AB ions into the source-drain of the FTiT, a high-temperature, long-term heat treatment was performed using a diffusion furnace to recover and activate the crystals of the ion-implanted layer. In the conventional manufacturing method, as shown in Figure 1 (in order to activate ILB ions, high-temperature heat treatment of 900°C or higher is required;
Since the mass number of 8B is large, the silicon substrate surface is seriously damaged, and a high temperature and long time heat treatment annealing is required to reduce the leakage current of the diffusion bond due to the damage. However, conventional high temperature and long time heat treatment (e.g. 1000°C30
In the case of 2), the diffusion length of boron becomes large, the diffusion junction depth and the transverse wave become large, and the punch-through between the source and drain limits the downsizing of the P-type MOB-FET.

Table 1 is a flow chart of complementary MOEI-FFiT fabrication according to the present invention. After forming the well field film, gate film, and Pe1y8i gate electrode, P-type MO8
・BP and ions are added to the source and drain regions of the FET.
Injection of X 10'' cm-2 or more, N1M0E]・
1X 31F ions in the source/drain region of FF1T
After the 10 is implantation, low-temperature, short-time heat treatment is performed using a halogen lamp, graphite heater, etc. to recover crystals and activate the ion-implanted layer. In the present invention, B
The reason why 1×10 16 m2 or more of F is implanted is because it is necessary to make the implanted layer amorphous. Also 31P
For the same reason, it is possible to implant more than 16tm of I , or 31p
Ions can be activated 100% by heat treatment at 800° C. or higher. The correlation between annealing temperature and sheet resistance in FIG. 1 is when the ion implantation dose is 1.0×1Q”cnr2 and the annealing time is 10 seconds.

Therefore, the ion-implanted layer made amorphous by BF2 or 1lip ion implantation can be annealed by heat treatment at a low temperature of 900° C. or lower and for a short time of less than 1 minute. 90
Heat treatment for less than 1 minute at a temperature of 0°C or less causes no boron diffusion redistribution, and moreover, it is of the Le type.

Since the mass number of P-type ions is not significantly different from 81,
Low-temperature, short-time heat treatment reduces leakage current in diffusion bonding. Therefore, the manufacturing method of the present invention provides a complementary MO[
3-Provide FFiT.

Table 1 Flow chart of complementary MO8-FInT manufacturing according to the present invention Table 2 Flow chart of conventional complementary MOEI-FFiT manufacturing

[Brief explanation of the drawing]

Fig. 1: A diagram showing the correlation between the sheet resistance of the diffusion layer and the annealing temperature obtained by short-time annealing using a halogen lamp. Tempe-vafuri J Annea"n #th
l (2)

Claims (1)

[Claims] LSI consisting of silicon gate complementary MO8 FIT
During manufacturing, the source/drain regions of the P-type MO86FKT are implanted with BF2 ions of 1×1018 crn-2 or more, and the source/drain regions of the Le-type MO8-FFiT are formed by implanting 31p ions or more than 1×10” cm−2 of the BF2 ions. A method for manufacturing a semiconductor device, characterized in that the ion-implanted layer is annealed at a low temperature (900° C. or lower) and for a short time (1 minute or less).