JPH02211665A - Solid-state image sensing device - Google Patents
Solid-state image sensing deviceInfo
- Publication number
- JPH02211665A JPH02211665A JP1033125A JP3312589A JPH02211665A JP H02211665 A JPH02211665 A JP H02211665A JP 1033125 A JP1033125 A JP 1033125A JP 3312589 A JP3312589 A JP 3312589A JP H02211665 A JPH02211665 A JP H02211665A
- Authority
- JP
- Japan
- Prior art keywords
- receiving element
- solid
- conductor
- layer
- light receiving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims description 17
- 238000003384 imaging method Methods 0.000 claims description 13
- 239000010409 thin film Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 30
- 239000004065 semiconductor Substances 0.000 description 13
- 239000010408 film Substances 0.000 description 10
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 229910052782 aluminium Inorganic materials 0.000 description 8
- 238000004544 sputter deposition Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明は、固体撮像装置受光部と配線との間の段差構造
に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a step structure between a light receiving section of a solid-state imaging device and wiring.
[発明の概要]
本発明は、絶縁性基板上に作製された固体撮像装置にお
いて、受光素子と該受光素子から配線される導電体との
間でできる段差部を少くとも2方向以上設けることによ
り、受光素子の膜質及び導電体のスパッタ方向によって
できる段差部の抵抗成分を小さくすることができ、受光
素子の膜質及び導電体のスパッタ方向に依存しない、高
品質の固体撮像装置を特製できるようにしたものである
。[Summary of the Invention] The present invention provides a solid-state imaging device fabricated on an insulating substrate by providing a stepped portion between a light receiving element and a conductor wired from the light receiving element in at least two directions. , it is possible to reduce the resistance component of the stepped portion caused by the film quality of the light-receiving element and the sputtering direction of the conductor, and it is possible to custom manufacture a high-quality solid-state imaging device that does not depend on the film quality of the light-receiving element and the sputtering direction of the conductor. This is what I did.
[従来の技術]
従来の固体撮像装置は受光素子と該受光素子から配線さ
れる導電体との間にできる段差部は一方向だけであった
。第2図(a)に従来の受光素子の平面図を示す。第2
図(b)は第2図(a)の平面図において、A−a間を
切断した断面図及び薄膜トランジスターを示す。同図(
a)において、lはa−5i:H12は透明電極(IT
Oなと)、3はアルミ電極である。同図(a)の破線B
−b間において切断した図が同図(C)である。同図(
c)より1のa−3i:H層と、3のアルミ電極層から
できる段差部は一方向だけである。[Prior Art] In a conventional solid-state imaging device, a stepped portion formed between a light receiving element and a conductor wired from the light receiving element is only in one direction. FIG. 2(a) shows a plan view of a conventional light receiving element. Second
FIG. 2(b) is a cross-sectional view taken along line A-a in the plan view of FIG. 2(a), and shows a thin film transistor. Same figure (
In a), l is a-5i: H12 is a transparent electrode (IT
3 is an aluminum electrode. Broken line B in figure (a)
The figure (C) is a diagram cut along the line -b. Same figure (
From c), the stepped portion formed between the a-3i:H layer 1 and the aluminum electrode layer 3 is only in one direction.
しかし、前述の従来技術では、段差部を導電体でステッ
プカバレッジ性良く被うためには、導電体の厚みの2倍
以下に、段差部の厚さが形成されていなくてはならない
。例えば受光素子をPin構造のa−5i:Hで形成し
た場合、a−3iHをエツチングする場合、n層のエツ
チングレイトがP層、i層に比較して遅いため、最上層
のn層がせり出しとなって残ってしまう。このせり出し
状に残ったn層に導電体をスパッタする場合、段差部が
1方向の場合スパッタ方向により、せり出しの導電体の
膜厚が、平坦な導電体層の膜厚に比較して1/10程度
になってしまう。固体撮像装置の様に光を微少な電気に
変換するような装置の場合には、ひさし部の導電体に大
きな抵抗をもつことにより、充分な電流を流すことがで
きず、明出力波形がなまってしまう。(以後この波形な
N波形と呼ぶ)またN波形を抑え込む条件でデポすると
、暗電流が大きくなってしまう。そこで本発明はこのよ
うな問題点を解決するもので、その目的とするところは
、設計上でプロセスマージンを得ることができ、信頼性
の高い固体撮像装置を提供するところにある。However, in the above-mentioned conventional technology, in order to cover the step portion with the conductor with good step coverage, the thickness of the step portion must be twice or less than the thickness of the conductor. For example, when the photodetector is formed of a-5i:H with a Pin structure, when etching a-3iH, the uppermost n layer protrudes because the etching rate of the n layer is slower than that of the p and i layers. It remains. When sputtering a conductor onto the n-layer that remains in the protruding shape, if the stepped portion is in one direction, depending on the sputtering direction, the thickness of the protruding conductor will be 1/1/2 of the thickness of the flat conductor layer. It will be about 10. In the case of devices that convert light into minute amounts of electricity, such as solid-state imaging devices, the large resistance of the conductor in the eaves prevents the flow of sufficient current, resulting in a distorted bright output waveform. It ends up. (Hereafter, this waveform will be referred to as the N waveform.) Furthermore, if the deposition is performed under conditions that suppress the N waveform, the dark current will increase. The present invention is intended to solve these problems, and its purpose is to provide a highly reliable solid-state imaging device that can provide a process margin in design.
[課題を解決するための手段]
本発明の固体撮像装置は、絶縁性基板上に、受光素子と
該受光素子を駆動させる薄膜トランジスタとを形成して
成る固体撮像装置において、該受光素子から配線される
導電体と該受光素子の間でてきる段差部を少くとも2方
向以上で段差部を導電体で被覆したことを特徴とする。[Means for Solving the Problems] A solid-state imaging device of the present invention is a solid-state imaging device in which a light receiving element and a thin film transistor for driving the light receiving element are formed on an insulating substrate. The step portion formed between the conductor and the light receiving element is characterized in that the step portion is covered with a conductor in at least two directions.
〔作 用1
本発明の上記の構成によれば、導電体層のスパッタ方向
、あるいは、受光素子の膜質に依存しないで、ある方向
においては、段差被覆性の極めて良好な段差部を導電体
層で形成することができる。これにより、N波形を抑え
ることができ、膜質に依存しない。つまりa−5i:H
層デポ条件で暗電流を抑える条件にだけ着目すれば、N
波形を抑えることができ、またa−3i:H層のデポ条
件についても大きなマージンを得ることがてきる。[Function 1] According to the above-described structure of the present invention, the conductor layer can cover the step portion with extremely good step coverage in a certain direction, regardless of the sputtering direction of the conductor layer or the film quality of the light receiving element. can be formed with. Thereby, the N waveform can be suppressed and does not depend on film quality. In other words, a-5i:H
If we focus only on the conditions for suppressing dark current under layer deposition conditions, N
The waveform can be suppressed, and a large margin can be obtained regarding the deposition conditions of the a-3i:H layer.
〔実 施 例1
第1図(a)は本発明の実施例における受光素子の平面
図を示す。同図(b)は同図(a)のA−8間の構造断
面図及び薄膜トランジスタを示し、同図(c)は同図(
a)のB−b間の構造断面図を示す。ここでは、多結晶
シリコン薄膜トランジスタ及び、a−3i:H(水素化
アモルファスSi)受光素子を用いた場合の実施例を述
べる。同図(a)においてlはa−5i:H12は透明
電極・(ITOなど)、3はアルミ電極である。ITO
とa−5i:Hは同図(a)の様に、同一線上に重なる
部分が一部存在して、同一線より内側に約4μm=10
LLmにアルミ電極が存在する構造となっている。[Embodiment 1] FIG. 1(a) shows a plan view of a light receiving element in an embodiment of the present invention. Figure (b) shows a cross-sectional view of the structure along A-8 in Figure (a) and the thin film transistor, and Figure (c) shows Figure (c).
A structural sectional view taken along line B-b in a) is shown. Here, an example will be described in which a polycrystalline silicon thin film transistor and an a-3i:H (hydrogenated amorphous Si) light receiving element are used. In the same figure (a), l is a-5i: H12 is a transparent electrode (such as ITO), and 3 is an aluminum electrode. ITO
and a-5i:H, as shown in the same figure (a), there is a part that overlaps on the same line, and about 4 μm = 10 on the inside of the same line.
It has a structure in which an aluminum electrode exists at LLm.
同図(b)において、4は絶縁性基板、5は多結晶シリ
コン、6はゲート酸化膜、7はゲート電極、8は層間絶
縁膜、9はP型半導体層でボロンをドープしたa−3i
t−+t Cx:H,10は■型半導体層でa−5i:
HlllはN型半導体層てノンをドープしたa−3it
−xc:Hである。なおXの値は0<x≦1をとる。1
のa−3j:Hは9.10.11の3層つまりP−i−
n構造から成っている。In the figure (b), 4 is an insulating substrate, 5 is polycrystalline silicon, 6 is a gate oxide film, 7 is a gate electrode, 8 is an interlayer insulating film, and 9 is a P-type semiconductor layer doped with boron.
t-+t Cx:H, 10 is a ■-type semiconductor layer a-5i:
Hll is an N-type semiconductor layer doped with non-containing a-3it.
-xc:H. Note that the value of X is 0<x≦1. 1
a-3j:H is the 3rd layer of 9.10.11, that is P-i-
It consists of n structure.
同図(c)は同図(a)のB−b間の構造断面図を示す
が、同図(a)と同図(C)より、lのa−3i・H層
とアルく電極層3からできる段差部は、3方向となって
いる。Figure (c) shows a cross-sectional view of the structure between B-b in Figure (a). The stepped portion formed from 3 is in 3 directions.
受光素子を形成する各層の膜厚は本実施例において、第
1図(b)で9のP型半導体層が500人、10の1型
半導体層が8000人、11のN型半導体層が500人
にした。3のアルミ電極層が被覆する段差部は、900
0人となり一般にアルミ電極層に必要とされる膜厚は4
500Å以上必要とされるが、本実施例においてアルミ
電極層の膜厚は4500人〜lumにした。In this example, the thickness of each layer forming the light receiving element is 500 for the P-type semiconductor layer 9, 8000 for the 1-type semiconductor layer 10, and 500 for the N-type semiconductor layer 11 as shown in FIG. 1(b). Made into a person. The step portion covered by the aluminum electrode layer of No. 3 is 900
0 people, and the film thickness required for the aluminum electrode layer is generally 4
Although a thickness of 500 Å or more is required, in this example, the thickness of the aluminum electrode layer was set to 4500 lum.
11のn型半導体層を形成する際、暗電流を抑えるため
にメタン(CH4)を導入しているが、メタン量が多く
なるに従いa−3i・Hをエツチングする際のn型半導
体層のエツチングレイトが遅くなり、n型半導体層のせ
り出しが大きくなる。また逆にn型半導体層のせり出し
を小さくするために、メタン量を抑えると逆に暗電流が
大きくなり、1100LL口のセン勺−て暗電流が1×
J O−” Aを超えS/N比を悪化させてしまう結果
となる。メタン量とデボ時間を変化させて、明出力波形
のなまり方、あるいは暗電流を評価した結果を表1、表
2に示す。When forming the n-type semiconductor layer of No. 11, methane (CH4) is introduced to suppress dark current, but as the amount of methane increases, the etching of the n-type semiconductor layer when etching a-3i/H increases. The rate becomes slower and the protrusion of the n-type semiconductor layer becomes larger. Conversely, if the amount of methane is suppressed in order to reduce the protrusion of the n-type semiconductor layer, the dark current will increase, and the dark current will increase by 1×
This results in a deterioration of the S/N ratio by exceeding J O-"A. Tables 1 and 2 show the results of evaluating the bright output waveform rounding or dark current by varying the amount of methane and the debo time. Shown below.
表1 N波形発生率
表2 暗電流発生率
(> I X 10−” A)
表1、表2からN波形の発生率及び暗電流発生率が低い
のは、メタン量が400SCCMで、デボ時間が170
secの場合が望ましい条件であるが、この条件におい
ても暗電流が1〜2%発生してしまう。そこで受光素子
部を図1 (a)(b)(c)の様な構造にした場合
、暗電流発生率については表2と変化がないものの、N
波形発生率については、表1のいかなる条件においても
N波形の発生を抑えることができた。Table 1 N waveform occurrence rate Table 2 Dark current occurrence rate (> I is 170
sec is a desirable condition, but a dark current of 1 to 2% occurs even under this condition. Therefore, when the light-receiving element part is structured as shown in Figure 1 (a), (b), and (c), although the dark current generation rate is unchanged from Table 2, N
Regarding the waveform generation rate, the generation of N waveforms could be suppressed under any of the conditions shown in Table 1.
つまり、CH4量とデボ時間の関係で暗電流をすべて抑
え込む条件はないが、暗電流が発生しないすべての条件
で、N波形を抑えることができた。これにより、設計上
からプロセスマージンを高めることができ、高信頼性の
固体撮像装置を提供することができた。In other words, although there are no conditions for suppressing all dark current due to the relationship between the amount of CH4 and the debo time, it was possible to suppress the N waveform under all conditions in which dark current does not occur. As a result, it was possible to increase the process margin from a design standpoint, and it was possible to provide a highly reliable solid-state imaging device.
以上述べた様に、本発明によれば、以下に述べる様な発
明の効果が得られる。As described above, according to the present invention, the following effects of the invention can be obtained.
■受光素子の膜生成条件に依存しないで、N波形出力を
抑えることができる。(2) The N waveform output can be suppressed without depending on the film formation conditions of the light receiving element.
■AJ2導電層のスパック方向に依存しないで、導電体
の厚みの2.5倍、段差部の厚みがあっても、ある方向
においては、段差部をステップカバレッジ性よく被覆す
ることができるため、N波形出力を抑えることができる
。■Independent of the spuck direction of the AJ2 conductive layer, even if the thickness of the stepped portion is 2.5 times the thickness of the conductor, the stepped portion can be covered with good step coverage in a certain direction. N waveform output can be suppressed.
■設計上プロセスマージンを高めることができ、N波形
ばかりでなく暗電流も抑えることができる。■Process margin can be increased in design, and not only N waveform but also dark current can be suppressed.
第1図(a)は本発明の固体撮像装置の受光素子の平面
図である。第1図(b)は第1図(a)のA−a間で切
断した場合の断面図及び該受光素子と接続する薄膜トラ
ンジスタの断面図である。
第1図(c)は第1図(a)のB−b間を切断した場合
の断面図である。
第2図(a)は従来の固体撮像装置の平面図である。第
2図(b)は第2図(a)の受光素子をA−a間で切断
した場合の断面図及び該受光素子と接続する薄膜トラン
ジスターの断面図である。
第2図(c)は第2図(a)のB−b間を切断した場合
の断面図である。
a−5i:H
・透明電極
・・アルミ電極
絶縁性基板
多結晶シリコン
ゲート酸化膜
ゲート電極
層間絶縁膜
P型半導体層
工型半導体層
N型半導体層
以
上FIG. 1(a) is a plan view of a light receiving element of a solid-state imaging device of the present invention. FIG. 1(b) is a sectional view taken along line A-a in FIG. 1(a), and a sectional view of a thin film transistor connected to the light receiving element. FIG. 1(c) is a sectional view taken along line B-b in FIG. 1(a). FIG. 2(a) is a plan view of a conventional solid-state imaging device. FIG. 2(b) is a cross-sectional view of the light-receiving element of FIG. 2(a) taken along line A-a, and a cross-sectional view of a thin film transistor connected to the light-receiving element. FIG. 2(c) is a sectional view taken along line B-b in FIG. 2(a). a-5i:H ・Transparent electrode...Aluminum electrode Insulating substrate Polycrystalline silicon gate oxide film Gate electrode interlayer insulating film P-type semiconductor layer processing type semiconductor layer N-type semiconductor layer and above
Claims (1)
膜トランジスタとを形成して成る固体撮像装置において
、該受光素子から配線される導電体と該受光素子の間で
できる段差部を少くとも2方向以上で段差部を導電体で
被覆したことを特徴とする固体撮像装置。In a solid-state imaging device comprising a light-receiving element and a thin film transistor for driving the light-receiving element formed on an insulating substrate, at least two steps are formed between the conductor wired from the light-receiving element and the light-receiving element. A solid-state imaging device characterized in that a stepped portion is covered with a conductor in a direction or more.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1033125A JP2780181B2 (en) | 1989-02-13 | 1989-02-13 | Solid-state imaging device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1033125A JP2780181B2 (en) | 1989-02-13 | 1989-02-13 | Solid-state imaging device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02211665A true JPH02211665A (en) | 1990-08-22 |
| JP2780181B2 JP2780181B2 (en) | 1998-07-30 |
Family
ID=12377902
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1033125A Expired - Fee Related JP2780181B2 (en) | 1989-02-13 | 1989-02-13 | Solid-state imaging device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2780181B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6062155A (en) * | 1983-09-16 | 1985-04-10 | Seiko Epson Corp | Image sensor |
| JPS62299068A (en) * | 1986-06-18 | 1987-12-26 | Seiko Epson Corp | solid state imaging device |
-
1989
- 1989-02-13 JP JP1033125A patent/JP2780181B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6062155A (en) * | 1983-09-16 | 1985-04-10 | Seiko Epson Corp | Image sensor |
| JPS62299068A (en) * | 1986-06-18 | 1987-12-26 | Seiko Epson Corp | solid state imaging device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2780181B2 (en) | 1998-07-30 |
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