JPH02211735A - bit synchronizer - Google Patents

Abstract

PURPOSE:To quickly synchronize an output signal with an input signal by selecting and outputting the output signal of a shift register, whose phase difference from the input signal is smallest, in accordance with counted values of respective up/down counters. CONSTITUTION:The phase of the input signal and those of output signals of a shift register 14 are compared with each other, and plural up/down counters 171 to 17n are counted up or down in accordance with the phase difference and the phase delay or advance. The output signal of the shift register 14 whose phase difference from the input signal is smallest is selected and outputted. Thus, the phase difference between the input signal and plural output signals of the shift register 14 is detected in a short time, and the output signal is quickly synchronized with the input signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a bit synchronization device used in digital mobile communications and the like.

Conventional technology FIG. 2 shows the configuration of a conventional bit synchronizer.

In FIG. 2, 21 is an input signal NRZ (No.
nReturn-to-Zero) signal input terminal 22 differentiates the NFtZ signal from the input terminal 21 and outputs a pulse that rises when the NRZ signal is inverted (hereinafter referred to as NRZ inversion pulse). 23 is an oscillator that oscillates a signal with a frequency synchronized with the NRZ signal input to the input terminal 21; This is a shift register that outputs a signal of =n).

Further, as will be described later, 25 is a selector that selects one of the output signals of the shift register 24 and outputs it to the output terminal 27 under the control of the up/down counter 26. The inverted pulse from the differentiator 22 is compared with the phase of the current output signal selected by the selector 25, and if the phase of the output signal is delayed, it is counted down; Count up if progress is being made.

Next, the operation of the above conventional example will be explained.

In FIG. 2, the up/down counter 26 controls the selector 25 to select the next signal of the shift register 24 whose phase is advanced from the current output signal when counting down by a predetermined number; When a predetermined number is counted up, the selector 25 is controlled to select the next signal from the shift register 24 whose phase is delayed from the current output signal.

Therefore, by repeating the above operation, a signal synchronized with the phase of the NRZ signal input to the input terminal 21 is output from the output terminal 27.

Problems to be Solved by the Invention However, in the conventional bit synchronizer described above, when the up/down counter 26 counts down or up by a predetermined number, the next signal whose phase is delayed or the next signal whose phase is advanced is Since synchronization is achieved by selecting a signal and repeating this operation, the synchronization acquisition time is Furthermore, when the S/N ratio of the NRZ signal input to the input terminal 21 deteriorates, the phase comparison characteristic of the up/down counter 26 deteriorates from a solid line to a broken line, as shown in FIG. There is a problem that an error occurs in the count value and the synchronization acquisition time increases.

SUMMARY OF THE INVENTION In view of the above-mentioned conventional problems, it is an object of the present invention to provide a bit synchronization device that can synchronize with an input signal at high speed.

Means for Solving the Problems In order to achieve the above object, the present invention compares the phases of an input signal and an output signal of a shift register, and counts up or down depending on the phase difference and phase lag or phase lead. Provide multiple up/down counters,
According to the count value of each up/down counter, the output signal of the shift register having the smallest phase difference with the input signal is selected and output.

Operation With the above configuration, the present invention detects the phase difference between the input signal and the plurality of output signals of the shift register in a short time, so that synchronization with the input signal can be achieved at high speed.

In addition, by considering the count value of each up-down counter according to the characteristics of the up-down counter depending on the S/N ratio of the input signal, it is possible to select the output signal of the shift register with the smallest phase difference with the input signal. can.

EXAMPLES Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a bit synchronization device according to the present invention.

In FIG. 1, 11 is an input signal M〃(Non
(Return-to-Zero) (The D input terminal 12 differentiates the NFtZ signal from the input terminal 11 and outputs a pulse (hereinafter referred to as r@Z inversion pulse) that rises when the M times signal is inverted. 13 is an oscillator that oscillates a signal with a frequency synchronized with the M times signal input to the input terminal 11; 14 is an oscillator 1;
a shift register 15 that outputs a plurality of (=n) signals whose phase difference with the NRZ signal is sequentially determined by the signal from 3;
selects one of the output signals of the shift register 14 and outputs it to the output terminal 1 under the control of the phase determiner 18 as described later.
This is a selector that outputs to 6.

1711172 to 17n respectively compare the phase of the Z inversion pulse from the differentiator 12 and the output signal of the shift register 14, and count down when the phase of the output signal is delayed, and on the other hand, count down when the phase of the output signal is advanced. This is an up/down counter that up-counts when the phase determination unit 18 is present and outputs the count value to the phase determiner 18.

Next, the operation of the above embodiment will be explained.

In FIG. 1, when the m signal is input to the input terminal 11, up/down counters 171, 172 to 17n respectively compare the phase of the NRZ inversion pulse from the differentiator 12 and the output signal of the shift register 14, and output the output signal. When the phase of the output signal is delayed, the count is counted down, and when the phase of the output signal is ahead, the count value is calculated based on the phase difference and the S of the NRZ signal as shown in Figure 3.
The value corresponds to the phase comparison characteristic based on the /N ratio.

Incidentally, the up/down counter is M as shown in FIG.
〃If the double signal S/N ratio is poor, accurate counting is performed when the phase difference of the signals being compared is ±90 degrees, but if the phase difference of the signals being compared is ±90 degrees,
The closer it gets to ±180 degrees, the lower the count will actually be.

Therefore, the phase determiner 18 uses the up/down counter 17
The count values of 1 to 17n/2 are added, and the up-down counter 171, which is the starting point of this addition, is changed to the next up-down counter 172.
Add the count value of ~17(n/2)+t and similarly,
The up counter 17, which is the starting point of addition, is sequentially changed, and the sum of the count values of n/2 consecutive up/down counters 17 is determined.

Next, the phase determiner 18 determines the up/down counter 17 that is the starting point of addition when the above-mentioned added value becomes the maximum, and calculates the output signal of the shift register 14 corresponding to the up/down counter 17, that is, the Z-fold signal. The selector 15 is controlled to select the output signal of the shift register 14 whose phase difference is closest to 0 degrees.

Therefore, the m signal input to the input terminal 11 can be synchronized at high speed, and even when the 87N ratio of the m signal input to the input terminal 11 has deteriorated, the NRZ signal can be synchronized at high speed. Can be done.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, the present invention includes a plurality of up/down counters that compare the phases of an input signal and an output signal of a shift register, and count up or down according to the phase difference and phase lag or phase lead. , and the output signal of the shift register with the least phase difference from the input signal is selected and output based on the ° count value of each up/down counter, so it is possible to synchronize with the input signal at high speed. .

Further, by considering the count value of each up-down counter according to the characteristics of the up-down counter based on the 87N ratio of the input signal, it is possible to select the output signal of the shift register having the smallest phase difference with the input signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the bit synchronization device according to the present invention, and FIG. 2 is a block diagram showing an embodiment of the bit synchronization device according to the invention.
Z signal input terminal, 12...differentiator, 13...oscillator, 14...shift register, 15...selector, 1
6... Synchronization signal output terminal, 171-17n... Up/down counter, 18... Phase determiner. Figure counter

Claims (2)

[Claims] (1) An oscillator that outputs a signal synchronized with an input signal, a shift register that outputs a plurality of signals with sequentially different phase differences from the input signal depending on the signal from the oscillator, and one of the output signals of the shift register. a selector that selects and outputs the input signal; a plurality of up/down counters that respectively compare the phases of the input signal and the output signal of the shift register and count up or down according to the phase difference and the phase delay or phase lead; and means for controlling the selector to select and output the output signal of the shift register having the smallest phase difference with the input signal based on the count value of an up-down counter. (2) The control means adds the count values of consecutive half up/down counters, and selects the output signal of the shift register corresponding to the up/down counter as the starting point of addition when the added value becomes the maximum. The bit synchronization circuit according to claim 1.