JPH02211749A - Speed changing circuit - Google Patents

Abstract

PURPOSE:To attain the emission of an ES memory and the compression of a circuit scale by converting parallel data synchronized with a first clock signal to serial data synchronized with a second clock signal by using a holding means and a conversion means. CONSTITUTION:Introduced parallel data is held by the holding means 113 synchronizing with the first clock signal, and is outputted to the conversion means 119. The conversion means 119 converts the parallel data supplied from the holding means 113 to the serial data synchronizing with the second clock signal, then, outputs it. Thus, since the parallel data synchronized with the first clock signal can be converted to the serial data synchronized with the second clock signal by using the holding means 113 and the conversion means 119, the ES memory can be omitted, and the circuit scale can be compressed.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a speed conversion circuit that matches the phase of communication frames between an internal processing system and a transmission system in a communication device, etc., and aims to reduce the circuit scale. In a speed conversion circuit that converts parallel data introduced based on a clock signal into serial data based on a second clock signal asynchronous with the first clock signal,
a first timing generation means for outputting a first clock signal; a holding means for holding parallel data in synchronization with the first clock signal; a second timing generation means for outputting a second clock signal; The apparatus is configured to include converting means for synchronously taking in parallel data held by the holding means, and converting and outputting serial data.

[Industrial application field]

The present invention relates to a speed conversion circuit that matches the phase of communication frames between an internal processing system and a transmission system in a communication device or the like.

[Prior Art] In data communications, an operating clock signal within a communication device and a line transmission lock signal are generally asynchronous. Therefore, when transmitting and receiving data, it is necessary to perform speed conversion in order to adjust the phase of communication data.

FIG. 4 shows the configuration of a communication device equipped with a conventional speed conversion circuit. Speed conversion processing is performed on both reception and transmission.

The receiving unit 211 extracts a transmission lock signal from the data received from the line and supplies it to the timing pulse generation circuit 517. In response to this transmission lock signal, timing pulse generation circuit 517 outputs a write reset (WR) signal for instructing initialization of the write address and a write clock (WC) signal based on the transmission lock signal. The received data is sent to elastake store (based on these signals).
ES) is written to memory 215. The timing pulse generation circuit 515 outputs a read reset (RR) signal for instructing initialization of a read address and a read clock signal (RC) based on an operation clock signal within the device. The signals written in the ES memory 215 are these RRs.
It is read out based on the signal and the RC signal. Speed conversion is performed by asynchronous write and read operations based on the transmission lock signal on the line side and the operating clock signal within the device.

The speed-converted received data is written to a random access memory (RAM) 525 via the S/P converter 217 under the control of the CPU 521, for example.

During transmission, the transmitted data is stored in read-only memory (
ROM) 523 or RAM 525. This transmission data is written into the ES memory 513 in response to the WR multiplied signal output by the timing pulse generation circuit 515 and the WC signal based on the operating clock signal within the device. The signal written in the ES memory 513 is read out in response to the <RC signal based on the RR signal output from the timing pulse generation circuit 517 and the transmission lock signal on the line side, and is transmitted from the transmitter 221.

In this way, the received data and the transmitted data are subjected to speed conversion via the ES memory 215 or ES memory 513, and the phase of the frame is adjusted.

[Problem to be solved by the invention]

By the way, in the above-mentioned conventional speed conversion circuit, ES memories are used on the receiving side and the transmitting side to perform speed conversion.

This BS memory has a function of temporarily storing input data until it is read out based on a clock signal on the output side, and also has a function of controlling reading/writing timing, so that the configuration becomes complicated and the circuit scale becomes large. Therefore, a speed conversion circuit using such an ES memory also has a problem in that the circuit scale becomes large.

The present invention was created in view of these points, and an object of the present invention is to provide a speed conversion circuit whose circuit scale is reduced.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the speed conversion circuit of the present invention. In order to achieve the above object, the speed conversion circuit of the present invention includes first timing generation means 111, second timing generation means 115, holding means 13, and conversion means 119.

In the figure, first timing generation means 111 outputs a first clock signal.

The holding means 113 holds parallel data in synchronization with the first clock signal.

The second timing generation means 115 outputs a second clock signal.

The conversion means 119 takes in the parallel data held by the holding means 113 in synchronization with the second clock signal, converts it into serial data, and outputs it.

Therefore, the apparatus as a whole is configured to convert parallel data supplied based on the first clock signal into serial data based on the second clock signal asynchronous with the first clock signal.

(Function) The introduced parallel data is held in the holding means 113 in synchronization with the first clock signal, and is output to the conversion means 119.

The converting means 119 converts the parallel data supplied from the holding means 113 into serial data in synchronization with the second clock signal and outputs the serial data.

In the present invention, the holding means 113 and the converting means 11
9 converts parallel data synchronized with the first clock signal into serial data synchronized with the second clock signal, so the ES memory can be omitted and the circuit scale can be reduced.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of a speed conversion circuit in one embodiment of the present invention.

(2) Here, and (1) show the correspondence between the embodiment of the present invention and FIG. 1 (.

The first timing generation means 111 corresponds to the timing pulse generation circuit 231.

The holding means 113 is a D-type flip-flop (D-FF).
It corresponds to 321.

The second timing generation means 115 corresponds to the timing pulse generation circuit 233.

The converting means 119 corresponds to the shift register 323.

The first cross signal corresponds to the latch clock signal 251.

The second clock signal corresponds to the load clock signal 253 and the shift clock signal 255.

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

2, and in FIG. 2, the speed conversion circuit according to the embodiment of the present invention includes the receiving section 211. Synchronous circuit 213. ES memory 215, series-
Parallel (S/P) converter 217. Two D-FFs 311 and 313. Parallel-serial (P/S) converter 219. The transmission section 221 includes two timing pulse generation circuits 231 and 2331, a phase comparator 2351, and a selection section 351.

Further, the P/S converter 219 includes a D-FF 321 and a shift register 323. Note that the same reference numerals as in FIG. 4 indicate the same circuit parts.

The receiving unit 211 extracts a transmission lock signal from the data received from the line and supplies it to the timing pulse generation circuit 233. Further, received data via the receiving section 211 is supplied to a synchronization circuit 213, and frame synchronization is detected. The detection result is supplied to the timing pulse generation circuit 233.

The timing pulse generation circuit 233 outputs the WR multiplied signal and the WC signal to the ES memory 215 based on the line side transmission lock signal and frame synchronization detection. The received data is written into the ES memory 215 from the address indicated by the WR multiplication signal in synchronization with the WC signal. The timing pulse generation circuit 231 outputs an RR multiplied signal and an RC signal based on an operating clock signal within the device. The signal written in the ES memo IJ 215 is read from the address indicated by the RR multiplied signal in synchronization with the RC signal, and is supplied to the S/P converter 217. As a result of operation with these asynchronous WC and RC signals, the speed of the signals is converted.

The speed-converted signal is converted from serial data to parallel data by the S/P converter 217.

If the addresses for writing to and reading from the ES memory 215 match, signal errors occur due to bit slips and the like. The phase comparator 253 inputs and compares the WR signal and the RR multiplied signal, and performs control to shift the timings of both signals if they are close in time. Based on the control of the phase comparator 235, the timing pulse generation circuit 231 outputs an RR multiplied signal so that the read and write timings are not close to each other.

In transmission, in this embodiment, a case will be considered in which 8-bit parallel data is converted into serial data in units of 16 bits. Two D-FF311 for 16-bit processing
and 313.

Further, the operation timing of each component is shown in FIG.

A frame pulse (see FIG. 3(a)) which becomes a "low" logic level at the beginning of one frame is supplied from the bus.

The signal supplied from the bus is, for example, parallel data as shown in FIG. 3(b), in which one frame consists of a plurality of time slots (one time slot has 8 bits).

The speed conversion circuit of this embodiment uses time slot 2 (time slot 2 of the 0th frame is ``2°'', time slot 2 of the 1st frame is ``21J'', and so on, and so on.
2□J, '2tJ+...) data is to be extracted.

Data from the bus is sent to two D-FFs 311 and 313.
is input. Time slot 2 of each frame is extracted from this data to generate 16-bit data. For this purpose, the timing pulse generation circuit 231
The FF 311 is supplied with a clock signal that becomes a high logic level in time slot 2 of an even frame as shown in FIG. 3(C).
1 to the D-FF 313 is supplied with a clock signal which becomes a high logic level at times l near 7 to 2 of an odd frame as shown in FIG. 3(d).

The D-FFs 311 and 313 hold and output signals in synchronization with the rising edge of the clock signal supplied from the timing pulse generation circuit 231.

From D-FF311, time slot 2 of even frame
data (see FIG. 3(e)) is output. This data is held until the next clock signal goes to a "high" logic level. Further, the D-FF 313 outputs data of time slot 2 of an odd frame (see FIG. 3(f)). This data is held until the next clock signal goes to a high logic level. D-FFs 311 and 313
A total of 16 bits of parallel data, each with 8 bits (8 lines), is output from the D-F in the P/S converter 219.
Supplied to F321.

This 16-bit data is sent to the timing pulse generation circuit 23.
1 outputs a latch clock signal 251 (Fig. 3 (g)
(see) is held in the D-FF 321 in synchronization with the rising edge of the signal. The latch clock signal 251 is, for example, a D-FF
While time slot 2° is output from 3L1 and time slot 21 is output from D-FF313 (near the center)
is controlled so that it is output. The D-FF 321 outputs 16-bit parallel data, which is held and output until the latch clock signal 251 rises next.

This 16-bit output is the load clock signal 253 (third
(see figure (i))) is taken into the shift register 323 in synchronization with the rising edge of the signal. The shift register 323 receives a shift clock signal 255 (line side operation clock signal, FIG. 3) supplied from the timing pulse generation circuit 233.
In synchronization with the rising edge of (see 1), the held data is shifted one bit at a time and output. In this way, the shift register 323 converts the 16-bit parallel data into serial data and outputs output data 257 (third
(See figure (m)).

The timing pulse generation circuit 233 generates, for example, two types of pulses (load pulse 361 (
3(j)) and a load pulse 363 (see FIG. 3(k))) to the selection unit 351, the 0 phase comparator 235 compares the latch clock signal 251 and the load clock signal 253, and compares the latch clock signal 251 and the load clock signal 253, If the signals are close to each other, the selection unit 351 performs control to change the output load clock signal 253. In accordance with this control, the selection unit 351
Either the load pulse 361 or the load pulse 363 is output as the load clock signal 253.

■ Connect the P/S converter 219 to the D-FF 321 in this way.
and shift register 323, D-FF
321 and shift register '32
By asynchronously reading data from 3, it is possible to configure a speed conversion circuit that does not use an E$ memory on the transmitting side, so the circuit scale can be reduced.

Furthermore, since the ES memory can be omitted, integration becomes easier and costs can be reduced.

■, Note that in the embodiment of the present invention described above, two D-FFs 311 are used to hold 16-bit parallel data.
and 313, but when converting 8-bit parallel data into serial data, data may be supplied directly from the bus to the P/S converter.

In addition, in ``correspondence between Examples and Figure 1'',
Although the correspondence between the present invention and the embodiments has been described, those skilled in the art can easily imagine that the present invention is not limited to this and that there are various modifications.

〔Effect of the invention〕

As described above, according to the present invention, the ES memory can be omitted by converting parallel data synchronized with the first clock signal into serial data synchronized with the second clock signal using the holding means and the conversion means. Since the circuit scale can be reduced by using this method, it is extremely useful in practice.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of the speed conversion circuit of the present invention;
The figure is a block diagram of the configuration of a speed conversion circuit according to an embodiment of the present invention, FIG. 3 is a timing diagram of operation, and FIG. 4 is a configuration diagram of a conventional example. In the figure, 111 is a first timing generation means, 113 is a holding means, 115 is a second timing generation means, 119 is a conversion means, 211 is a receiving section, 213 is a synchronization circuit, 215.513 is an ES memory, 217 is an S/ P conversion unit, 219.511 is a P/S conversion unit, 221 is a transmission unit, 231.233, 515, 517 is a timing noise generation circuit, 235.519 is a phase comparator, 251 is a latch clock signal, 253 is a Load clock signal, 255 is a shift clock signal, 257 is output data, 351 is a selection section, 361.363 is a load pulse, 521 is CPU. 523 is a ROM, and 524 is a RAM.

Claims (1)

[Claims] (1) In a speed conversion circuit that converts parallel data introduced based on a first clock signal into serial data based on a second clock signal asynchronous with the first clock signal, a speed conversion circuit that outputs the first clock signal. 1 timing generation means (111); holding means (113) for holding the parallel data in synchronization with the first clock signal; second timing generation means (115) for outputting the second clock signal; The holding means (11
3) converting means (119) for taking in parallel data held by the converter, converting it into serial data, and outputting the converted data;