JPH02212945A - Software logic simulator - Google Patents

Abstract

PURPOSE:To simulate even a large-scale logical circuit model at high speed by providing a multiprocessor with logical function evaluation process and event evaluation and event propagation process and an interprocess data transferring means. CONSTITUTION:After the logical function evaluation process 1 evaluates the logical function of an element having changed in its input state value, it transfers logical function evaluation data (a) to the interprocess data transferring means 3, and further, sends an interruption processing signal (c) to start interruption processing to the event evaluation and event propagation process 2. The event evaluation and event propagation process 2 executes the transfer of event evaluation and event propagation and event propagation data to the interprocess data transferring means 3, and the interprocess data transferring means 3 executes interprocess data transfer between the logical function evaluation process and the event evaluation and event propagation process. Thus, the evaluation of a logical function, the evaluation of an event and the propagation of the event can be simultaneously executed in parallel, and the large-scale logical circuit model can be simulated at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a software logic simulator, and particularly to a software logic simulator that simulates a logic circuit model.

[Conventional technology]

Conventionally, this type of software logic simulator has sequentially executed a logic function evaluation means that evaluates a logic function, and an event evaluation and event propagation means that evaluates an event (change in signal value) and propagates the event. For example, see "Design of rVLsI", Rigaku Shiminireshin, pp. 191-220, published by Iwanami Shoten).

(Issue 11 to be solved by the invention) The conventional software logic simulator described above executes the logic function evaluation means and the event evaluation and event propagation means in sequential processing. The disadvantage is that a large amount of time is spent on training.

In view of the above-mentioned points, an object of the present invention is to develop a software logic system that can simulate large-scale logic circuit models at high speed by simultaneously performing evaluation of logical numbers, event evaluation, and event propagation in parallel. The goal is to provide a simulator.

[Means to solve the problem]

The software logic simulator of the present invention includes, in a multiprocessor, a logic function evaluation process that evaluates a logic function and transfers logic number evaluation data to an interprocess data transfer means, event evaluation, event propagation, and event propagation data. an event evaluation and event propagation process that transfers data to an inter-process data transfer unit; and an inter-process data transfer unit that transfers inter-process data between the logical function evaluation process and the event evaluation and event propagation process. .

[Effect]

In the software logic simulator of the present invention, the logic function evaluation process evaluates the logic function and transfers the logic function evaluation data to the interprocess data transfer means, and the event evaluation and event propagation process performs event evaluation, event propagation, and event propagation. The data is transferred to the inter-process data transfer means, and the inter-process data transfer means transfers the inter-process data between the logical function evaluation process and the event evaluation and event propagation process.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the software logic simulator of the present invention.

The software logic simulator of this embodiment includes a logic number evaluation process 1, an event evaluation and event propagation process 2, and an interprocess data transfer means 3.

The logical function evaluation process 1 uses the inter-process data transfer means 3 to transfer the logical function evaluation data a to the event propagation and event transmission PI process 2 when the evaluation of the logical function is completed.

The event evaluation and event propagation process 2 transfers the event propagation data b to the logical number evaluation process 1 using the inter-process data transfer means 3 when the event propagation ends.

The logical function evaluation process 1 and the event evaluation and event propagation process 2 can be executed simultaneously by separate processors of the general-purpose multiprocessor, and each execution is repeated until the end of the simulation run.

Next, the operation of the software logic simulator of this embodiment configured as described above will be explained.

After evaluating the logic function of the element whose input state value has changed, the logic function evaluation process 1 transfers the logic function evaluation data a to the inter-process data transfer means 3, and further sends an interrupt process to the event evaluation and event propagation process 2. Sends interrupt processing signal C to be activated.

When the event evaluation and event propagation process 2 receives the interrupt processing signal C from the logic function evaluation process l, it activates an interrupt process that receives and receives the logic function evaluation data a from the interprocess data transfer means 3.

After sending an interrupt processing signal C to the event evaluation and event propagation process 2, the logic function evaluation process 1 successively evaluates the logic function of the next element whose input state value has changed, and repeats this until the end of the simulation.

Event evaluation and event propagation process 2 evaluates whether or not the output state value has changed with respect to logic function evaluation data a, and if the output state value has changed, propagates the event to the fan-out destination of the element. , event propagation data b to the inter-process data transfer means 3, and further sends an interrupt processing signal C to the logic function evaluation process 1 to start interrupt processing.

When the logical function evaluation process 1 receives the interrupt processing signal C from the event evaluation and event propagation process 2, it activates the interrupt processing for receiving and taking the event propagation data b from the interprocess data transfer means 3.

After the event evaluation and event propagation process 2 sends the interrupt processing signal C to the logic function evaluation process 1, it sequentially performs events and evaluations of the next elements, and returns to the end of the simulation.

FIG. 2 is a diagram showing an example of the temporal operation relationship between the logical function evaluation process 1 and the event evaluation and event propagation process 2. L+, Ls, Ls and L4 each represent the evaluation of a logic function for one element, and E,
, E! ,E! and E4 represent event evaluation and event propagation for one element, respectively.

At a certain time 1. , the logic function evaluation process l executes the evaluation of the logic function for the first element whose input state value has changed. Then, at another time t8,
Event evaluation and event propagation process 2 includes event evaluation and event propagation tl E for the first element.
The logic function evaluation process 1 evaluates the logic function for the next element whose input state value has changed, and executes the logic function evaluation process 2 simultaneously in parallel.

In this way, the logical function evaluation process 1 and the event evaluation and event propagation process 2 are executed simultaneously and in parallel in separate processors, and are repeated until the simulator 1 ends.

[Effects of the Invention] As explained above, the present invention provides a logical function evaluation process, an event evaluation and event propagation process, and an inter-process data transfer means in a multiprocessor, so that logical function evaluation, event evaluation, and event This has the advantage that propagation can be performed simultaneously and in parallel, and even large-scale logic circuit models can be simulated at high speed.

4. Explanation of the Drawings Figure 1 is a block diagram showing the configuration of an embodiment of the software logic simulator of the present invention, and Figure 2 shows the logic function evaluation process, event evaluation, and event propagation process in Figure 1. FIG.

In the figure, I...Logic function evaluation process, 2...Event evaluation and event propagation process, ・Inter-process data transfer means, ・Logic function evaluation data, ・Event propagation data, ・Interrupt processing signal, Lt, L3. L.

・Logic function evaluation, E! ,Es,Ea...event evaluation and event propagation, tl. t2
...It's the time.

３　・・ a - b・・・ C hard φ LL+ E.

Claims (1)

[Scope of Claims] In a multiprocessor, a logic function evaluation process that evaluates a logic function and transfers the logic function evaluation data to an interprocess data transfer means; an event evaluation and event propagation, and the interprocess data of the event propagation data. An event evaluation and event propagation process that performs transfer to a transfer means; and an inter-process data transfer means that transfers inter-process data between the logical function evaluation process and the event evaluation and event propagation process. A software logic simulator with special features.