JPH02213928A - Optical disk controller - Google Patents

Abstract

PURPOSE:To improve the processing speed in an optical disk controller by providing a parameter list storing means, a means which stores the commands given from an outside, and a means which carries out continuously plural types of processes to an optical disk by referencing to the plural parameters. CONSTITUTION:A parameter list storing means 29 can store the plural parameters to designate the process contents to an optical disk. A means 30 is added to store the commands given from outside together with a means 26 which carries out continuously the plural types of processes to the optical disk. A RAM 5 includes a parameter list area to store the details of contents of plural processes and a defect list area to store the information on the defective areas. Then the processes are continuously carried out based on the external commands while referencing to the parameter list area and the defect list area. Thus even the different types of processes can be carried out with no interruption since plural parameters are previously given. Then the processing speed in the optical disk controller is improved.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art (Figures 9 to 11) Problems to be Solved by the Invention Examples of Means and Actions for Solving the Problems Explanation of the Principles of the Invention (Fig. Fig. 1) An embodiment of the present invention (Figs. 2 to 8) Effects of the invention [Summary] Regarding the optical tisf controller, even if the processing is different, the processing can be executed without interruption, and the processing speed can be greatly improved. The purpose of the present invention is to provide an optical disk controller in which detailed information on processing contents can be reused. and a means 26 for sequentially performing a plurality of types of processing on the optical disc by referring to the plurality of parameters in accordance with the command.

[Industrial application field]

The present invention relates to an optical disk controller, and more specifically, the present invention relates to an optical disk controller.
The present invention relates to an optical disk controller that can collectively process processes using different processing methods.

The bit error rate of optical disks is 2 to 2 that of magnetic disks.
Since the numbers are 10-' to 10-5, which are three digits more, and the nature of the error is also different, a new method needs to be designed.

With magnetic disks, there are many reading errors due to poor S/N.
An effective method is to repeat the playback again to recover from the error. On the other hand, with optical discs, defects on the recording medium are the main cause of errors, so replaying means are not used. Error correction using signal processing, and replacement processing that checks the error situation during playback immediately after recording and records it in another location if there is a problem (or, just before recording, check the medium for defects with a playback light beam and find that there are too many defects. (in some cases, changing the recording location) is used in combination.

[Conventional technology]

As mentioned above, optical discs have many defects, so optical discs are usually provided with a user area in which data is continuously written, as well as a replacement area in which defective locations in the user area are replaced. If a defect is known beforehand at the factory shipment stage, the defective portion (sector) will be skipped and the sectors will be shifted one by one. Also, if a new defect occurs during use, the Write
If this sector is determined to be defective when it is verified (verified to see if it was written correctly) after that, the sector also becomes a defective sector. In this case, since writing has already been performed in another sector, it is not possible to shift the sector, and a replacement process is performed to replace the defective sector in the user area with a predetermined sector in the replacement area. Therefore, the order in which the data appears does not necessarily match the original order of the data, but the information on which sectors on the track are defective and where the contents of the defective sectors have been rewritten is stored in the optical disc as defect information. All the controlling optical disk control devices know this. Generally, the unit in which replacement processing is performed is the user area 2.
In many cases, the replacement area is 16 sectors compared to 56 sectors. In other words, if one group consists of 1 track and 17 sectors per round and 16 tracks, there are 16) in one group.
There are 272 sectors in rack X17 sectors, of which 256 sectors are used as a user area and the remaining 16 sectors are used as an alternate area. The replacement area is not used at all if there are no errors in the user area. Information about where the defect was and where it was skipped is written as map information in a predetermined map, which will be described later.When an optical disk is loaded into an optical disk device, the map information is immediately read and It is stored in the control device.

When reading data from an optical disc, first, 11]
It reads all the sectors that contain map information and stores them in memory that can be accessed by the microprocessor at any time. There are two types of maps: the primary map, which stores only defect information that initially deviated, and the grow map, which stores information about defects that deteriorate during use and where they were replaced. As shown in Figure (b), only the defect address that indicates what is wrong is stored, and the Growth map stores two pieces of information: the defect address and the replacement address that shows where the replacement is. There is. In any case, it is necessary to skip the parts that are pointed out as defects on the map in the series of processing, and if it is necessary to replace them (specifically, If there is a defective sector, the replaced location must be processed to fill in the missing data.

FIG. 9 is a diagram linearly representing sectors on an optical disk, showing sectors in the user area and replacement area in one group. P0 to PI3 in FIG. 9 indicate the physical addresses of sectors. As shown in the figure, on an optical disc, a number of sectors are treated as one group (20 sectors in the example in the figure), and one group is divided into a user area and a replacement area. Data is normally written only to the user area. However, if there is a defect in the user area, a replacement area is used. In addition, (2) in the same figure is an example in which data is written from a state where nothing is written in the user area. Here, LO-Li2 is a logical address of data.

In this example, since it was known in advance that sector P5 is a defective sector, sector P5 is skipped and subsequent data is slipped (shifted) one sector at a time. Furthermore, ■ in the same figure is an example where sector P7 becomes a new defective sector when the data in LO to L7 is updated after ■ (LO' to L7).
' indicates updated data). In this case, sectors P9~
Since P16 is not updated, data cannot be slipped. Therefore, data L that should be written to sector P7
6' is written to sector P17 in the replacement area.

As explained in Figure 9, when there is a defective sector on an optical disk, it must be recovered by data slip or replacement processing.For this purpose, a map is provided to manage the defect sector, and the map includes a map as shown in Figure 10. As shown in (b) and (c), there are two types of maps: a primary map indicating sectors subject to data slip and a growth map indicating sectors subject to replacement processing.

The primary map shows the physical address of the defective sector (P5 in the example of FIG. 9), and the growth map shows the physical address of the defective sector (P5 in the example of FIG. 9).
7) and a replacement sector (PI3 in the example of FIG. 9). Note that FIG. 10(a) shows the correspondence between physical addresses and logical addresses, and FIG. 10(d) shows the data buffer block address for storing data at the logical address Ln.

In the situation shown in Figure 10, the conventional optical disc system 1l
FIG. 11 shows the processing flow of the host MPU when performing verification (verification by reading and checking from the optical disc) after data in the data buffer is read from the optical disc using LsI. FIG. 11 is a flowchart showing a program for performing Write and Verify processing, and in the figure, 5TEPn
(n-1, 2,...) indicates each step of the program. When the program starts, first
5TEP 1 specifies batch processing of sectors PO to P4, issues a Write command, and 5TEP 2
Determine whether command execution has finished. When the command execution is completed, the processing of the sector P6 is specified in 5TEP 3, a Write command is issued, and it is determined in 5TEP 4 whether the command execution is completed. When the command execution is completed, 5TEP sets the batch processing of sectors P8 to P16 at 5, and also sets W.
A rite command is issued, and in 5TEP 6 it is determined whether the command execution has ended. When the command execution is finished, 5TEP'/ specifies the process for sector P17, and a Write command is issued, and 5TEP8 determines whether the command execution has finished, and when the command execution is finished, a series of - It is determined that the rite process has ended and the process moves to the Verify process of 5TEP 9 or less. Here, when issuing the -rite command for sector Pr7 and when issuing each Ver f f y command, the host 1-M
If the processing time of the PU is long, a rotation wait will occur.

5TEP 9 specifies batch processing of sectors po-P4, issues a Verify command, and 5TEP
Determine whether command execution is completed using IO. When the command execution is completed, the processing of sector P6 is specified in 5TEPII, a Verify command is issued, and it is determined in 5TEP12 whether or not the command execution is completed. When command execution is finished, specify batch processing of sectors P8 to P16 in 5TEP13, and
The erify command is issued, and it is determined in 5TEP14 whether or not the command execution has ended. When command/execution is finished, STI! P15 specifies the process for sector P17, issues a Verify command, and
When the command execution ends at EP16, it is determined that the Write and Verify processing has ended, and the current processing ends.

[Problem to be solved by the invention]

However, in such a conventional optical disk controller, the optical disk controller LS is
Since the configuration was such that instructions (commands) and parameters were sequentially given to I for each processing unit and executed, when a process with a different processing method was to be executed, the MPU waited for the previous process to finish and then issued a new command. There was a problem that parameters had to be given, which caused processing to be interrupted.

Furthermore, since the optical disk controller itself does not store old commands and parameters, the parameters cannot be reused, and the MPU has to give instructions each time, which is troublesome and does not improve efficiency.

For example, although conventional optical disk controller LSIs can process user areas continuously, they cannot continue to process replacement areas, and cannot skip defective sectors because they do not have information about defective areas. , the process up to one sector before the defective sector is first received as one command, and then the defective sector is skipped and a new command is received from the next point to perform the process. Similarly, if there is a defect, processing will be stopped and the next command will be received, which will increase the processing (load) on the host processor each time. Furthermore, even if instructions can be memorized, the number of instructions is limited to one or two, so it is necessary to immediately report that the instruction has been completed to the host processor, and the host processor can immediately execute the next instruction. If the disk is not removed, the corresponding sector will be overdue since the disk is rotating, and in some cases, there is a problem that a one-rotation wait may occur.

Therefore, the present invention can significantly improve the processing speed without interrupting the processing even if the processing is different.
The purpose of this invention is to provide an optical disk controller that enables parameter reuse.

[Means to solve the problem]

In order to achieve the above object, the optical disk controller according to the present invention includes a parameter list storage means 29 capable of storing a plurality of parameters specifying processing contents for the optical disk, and means 30 for storing commands given from the outside.
and means 26 for sequentially performing a plurality of types of processing on the optical disc by referring to the plurality of parameters according to the command.

[Effect]

In the present invention, a RAM is provided which has a parameter list area for storing details of processing contents of a plurality of processes, and a defect list area for storing information on defective areas, and a RAM is provided that has a parameter list area for storing details of processing contents of a plurality of processes. and the defect list area are referred to and processing is executed continuously.

Therefore, since a plurality of parameters are given in advance, the processing will not be interrupted even if the processing is different, and since the optical disk controller itself stores the parameter list, it is easy to reuse the parameters.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

Seed plate FIG. 1 is a diagram for explaining the basic principle of the present invention.

FIG. 1 is a diagram showing the main parts of the optical disk control device.
In this figure, 1 is an optical disk controller, and 2 is a host MPU for controlling the optical disk controller l.
, 4 is a data buffer, and the optical disk controller 1 includes a parameter list storage RAM 5 for storing a plurality of command parameters, and a command register 6 for starting commands.

In such a configuration, the host MPU 2 prepares one set of parameters for each processing method and uses the RA as many times as necessary.
After writing to M5, issue the command. and,
The optical disk controller 1 refers to the parameters and executes processes one after another.

Therefore, since a plurality of parameters can be given in advance, processing is not interrupted, and since the optical disk controller itself stores the parameters, the parameters can be reused.

Futaba ■ Figures 2 to 8 show the optical disk controller LS according to the present invention.
FIG. 1 is a diagram showing an embodiment of the present invention in an optical disk control device used for information processing, etc. 11L
This is an example applied to SI.

First, the configuration will be explained. FIG. 2 is a diagram showing an example of the overall configuration of the optical disk control device. In the figure, 11 is an optical disk control device, 12 is an interface between the optical disk control device 11 and the SCSI (Small Con1-
13.14 is an interface ModifiedE SDI (Enhan
ced Small Drfve Interface
), and the optical disk control device 11 includes an optical disk controller LS115 and an ECC processor 16 as an optical disk control LSI.
The optical disk controller LS115 and the ECC processor 16, which are composed of two chips, perform the following processing.

・Sending commands to the optical disk device 13.14 and receiving the status ・Formatting the data written to the optical disk ・Decoding the format of the data read from the optical disk and correcting errors ・Transferring between the optical disk device 13.14 and the data buffer 18 Data transfer/5C3I system? Data transfer between the 1LS 119 and the data buffer 18 The SC3I is used as an interface for connecting the computer 12 and peripheral devices, and the computer system is connected to the optical disk controller 11 through the 5C3I.

Further, the optical disk control device 11 is connected to optical disk devices 13 and 14 via ESDI, and the optical disk control device 11 controls the optical disk.

Figure 3.4 is a block diagram of the optical disk control LSI.
It shows SI. In addition, optical disk controller LS
115 and the ECC processor 16 do not necessarily have to be separate LSIs; the part surrounded by the broken line in the figure is one LSI.
It may also be an embodiment. In FIG. 3, the optical disk controller LS115 is connected to an MPU interface circuit 21 that sends and receives commands and the like to and from the host MPυ (microprocessor 17) via the MPU interface.
and a DMA control circuit 22 that controls DMA transfer via the 5C3I control 1Ls119 and the DMA interface.
and a data buffer/ECCP II that controls data transmission and reception via the data buffer 18 and ECC processor 16 and the data buffer/ECCP interface.
JJ! 1 circuit 23, a format encode/decode circuit 24 for encoding and decoding data, an ESDIl# control circuit 25, an internal processor 26, and FIFO memories 27 and 28, which are connected to each other by a predetermined internal bus. It is connected. Here, M
The PtJ interface circuit 21 has a parameter list storage RAM (hereinafter referred to as P-
(abbreviated as RAM) 29 and a command register 30 are built-in, and commands are activated using the command register 3.
The details of the processing are specified by the parameter list shown in FIG. 6. The optical disk controller LSI 15 has a built-in RAM 29 for storing a parameter list of 256 bytes, and the RAM 29 for storing a parameter list is read by -r-ite/from the host MPU (microprocessor 17). Furthermore, the parameter list storage RAM 29 and the command register 30 do not necessarily need to be built into the MPU interface circuit 21, and may be provided independently from the MPU interface circuit 21 as shown in FIG.

The MPU interface circuit 21 sends and receives commands and processing results to and from the host MPU (microprocessor 17), and has a built-in memory that stores parameters necessary for command execution, and allows the host MPU to read/write data buffers. If so, the data is transferred via this interface circuit 21. D
MA! The lI41 circuit 22 serves as a DMA bus master.
It performs handshake control and byte count control for MA transfer.

The data buffer/ECCP II 11 circuit 23 controls read/write and refresh of the DRAM for the data buffer 77 and controls data transmission/reception with the ECC processor 16, and also controls the host MPU, DMA control circuit 22, and format encode/decode circuit 24.
and data buffer/EC from internal processor 26
Arbitrates C processor access requests and controls time-sharing use of the data buffer bus. When writing to an optical disk, the format encode/decode circuit 24 performs parallel-to-serial conversion of the write data and modulates it into an RLL (2,7) code.
A synchronization pattern such as Re5ync is added and sent to ESDI.

Furthermore, when reading from an optical disk, the data pattern is decoded, the synchronization pattern and the data are separated, the data is demodulated, and serial-to-parallel conversion is performed. The ESD I control circuit 25 includes a register circuit for sending and receiving ESDI control signals, an interface abnormality detection circuit, etc., and controls for sending commands to the optical disk device and receiving status information etc. are sent to the internal processor 26 via this circuit 25. will do.

The internal processor 26 decodes commands given from the host MPU, reports processing results, and also controls continuous processing of multiple sectors and single processing. Also, EC
Issuing commands to the C processor 16, receiving processing results,
It also analyzes and corrects errors in the data in the data buffer.

On the other hand, the ECC processor 16 includes a data transfer control circuit 31 that sends and receives commands and the like via the optical disk controller LS115 and the optical disk controller interface, and an ECC/control circuit that generates ECC and syndromes.
A syndrome generation circuit 32, an ECC/syndrome buffer 33 that temporarily stores the ECC/syndrome generated by the ECC/syndrome generation circuit 32, and an error position/numeric value detection circuit 34 that detects the location/numeric value of an error.
It is composed of an internal processor 35 and a FIFO memory 36, which are connected by a predetermined internal bus.

The data transfer control circuit 31 is an optical disk controller LS
115, and controls data transfer between the ECC/syndrome generation circuit 32 and an external data buffer. The ECC/syndrome generation circuit 32 outputs C when writing to an optical disc.
RC (cyclic redundancy)
), error correction code E CC (error correct
The ECC/syndrome buffer 33 generates an error syndrome and CRC check data when reading from an optical disk.
This is a panzer memory that temporarily stores syndromes, and can store two sectors worth of ECC or syndromes. The error position/numeric value detection circuit 34 detects the error position and error pattern based on the syndrome when reading from the optical disc. The internal processor 35 decodes commands given from the optical disk controller LS115, reports processing results, and moves processed data within the ECC processor 16.

In such a configuration, when data to be written on an optical disk is sent from the computer 12 to the optical disk controller LS115 via the 5C3I control LS119, this data is temporarily stored in the data bath sofa 18 and the necessary data is extracted. Optical disk controller LSF
While processing in step 15, write to optical disk device 13 and 14.

When reading data, the data read from the optical disk device 13, 14 is temporarily stored in the data buffer 18, and when a certain amount of data has accumulated, the data is transferred all at once to the 5C8I control 1Ls11.
Send to 9. Optical discs have a very high error rate, so EC
When writing, the C processor 16 adds an error check code ECC so that the error can be corrected later, and when reading, it detects the location and type of error based on the ECC, and writes it to the data buffer 18. Correct the incorrect part above. As shown in FIG. 2, both the optical disk controller LS 115 and the ECC processor 16 have internal processors 26 and 35 in their chips, and all internal operations are under program control.

In addition, optical disk controller LS115 and ECC
Optical disk control device 11 including processor 16
The whole is program controlled by a microprocessor 17.

Therefore, an MPU interface circuit 21 is provided to communicate commands or processing results with the microprocessor 17, and the internal processor 26 communicates with the MPU interface circuit 21.
When a command is received from the PU interface circuit 21, the command is decoded to operate the data buffer/ECCP II control circuit 23 or the ECC processor 16.
or start. Further, the ECC processor 16 operates according to instructions from the optical disk controller LS115, and the ECC processor 16 operates as a data buffer/EC processor.
It intercepts the data transferred on the bus connecting the CP control circuit 23 and the data buffer 18 and generates an ECC based on the data, and generates a syndrome for determining the error position and numerical value when reading.

The internal processor 26 of the optical disk controller LS115 is specifically shown in FIG.

FIG. 5 is a schematic diagram of the internal processor 26 with a built-in emulation function, and the description of the data buffer/ECCP control circuit 23 and the like is omitted for the purpose of mainly explaining the functions of the internal processor 26. In this figure, the internal processor 26 has a program ROM 41 that stores programs for the internal processor 26 to operate, and a program ROM 41 that stores programs for the internal processor 26 to operate.
A sequence system 'a (sequencer)/ALU arithmetic unit 42 that reads a program from the M41 and operates according to its contents, and an emute mode signal and debugging that switch between normal mode and emulation mode by writing from the host MPU (microprocessor 17). , a debug control register 43 that outputs a single-step signal, an emulation register 44 into which any program code is written to perform debugging from the host MPU, and a debug control register 44 that outputs a single step signal. The multiplexer MPX45 switches between the output bus of the program ROM 41 and the program code output bus of the emulation register 44. Further, 46 is an internal bus, and the internal processor 26 gives instructions to each circuit via the internal bus 46, and receives and receives data from each circuit. For example, internal processor 26
operates the ECC/syndrome generation circuit 32 and reads data from the ECC/syndrome bumper 33 via the internal bus 46.

Generally, commercially available processors are equipped with a debugging device called an emulator for program debugging, and if you run the emulator instead of the processor, you can view the contents of the registers in the internal processor, which would normally not be possible. , or the contents of the program can be freely rewritten. However, if the internal processor 26 of the optical disk controller LS115 according to the present invention is incorporated into an LSI chip, it will not be possible to debug it at all. In this embodiment, this function is called an emulation mode, and the debug control register 43, emulation register 44, and multiplexer MPX45 have this function.

Normally (normal mode) the internal processor 26 operates according to the contents of the program ROM 41, and in emulation mode the internal processor 26 uses the contents of the emulation register 44 as the program code. Furthermore, writing to the emulation register 44 is performed by the host MPU as described above.
will do. Switching between the normal mode and the emulation mode is performed by the MPX cutting off one bus in response to an emulation mode signal from the debug control register 43 in response to an instruction from the host MPU. Note that although MPX is used in this embodiment, the present invention is not limited to this. For example, all "0"s are written in the θ address of the program ROM 41,
In the emulation mode, the output of the program ROM may be cut off by specifying this address.

The circuit according to this embodiment supports the following debugging functions.

- Halt - Stops the processor unconditionally.

・Address conveyor stop□Stops the processor when passing the specified address.

・Address conveyor interrupt □ Generates an interrupt to the MPU (host) instead of stopping the processor when the specified address passes.

・Address conveyor trigger □ Generates a trigger signal externally when passing a specified address.

- Single step □ When the processor is stopped, only one instruction is executed according to the contents of the program ROM 41.

・Emulate □ Give a program code to the internal processor 26 from the external host MPU and execute the arbitrary program code one step at a time.

Providing the emulation function described above has the following advantages.

■Although it is not possible to perform emulation while moving at the actual speed that is generally done, the internal processor 26
The internal processor 2 can be used without having to prepare an emulator for
6 debugging becomes possible.

- If a routine for emulating the internal processor is prepared in the host MPU program, it becomes possible to debug and analyze the internal processor 26 even on-board (product level).

Next, the parameter list and Def
The format of the ect (defect) list will be explained. Figure 6 shows -rite, Verify, Re
This is the harameter list format of the ad command.

The basic idea of the present invention is that all user areas are processed continuously, and only the areas to be skipped need to be told in advance.
115 is provided with a RAM 29 for storing a parameter list, and the RAM 29 stores all parameter lists and a defect list indicating the positions of defects as shown in FIG. Assuming that there are about 4000 primary defects and about 1000 growth defects per disk, the probability that defective sectors will occur in 256 sectors of the user area is calculated to be 2 to 3. Therefore, in this embodiment, the parameter list, Defect list and 1
The capacity is 28 bytes. If 128 bytes are prepared, 32 defects can be stored if the information for one sector is 4 bytes, so this value is considered to be sufficient for actual continuous processing. Details of the parameter list and defect list are as follows.

to be determined.

When the optical disk controller LS115 automatically processes a plurality of consecutive sectors, it becomes the leading safeter. In addition, the defect list specifies the physical address of the defective sector.

-5ector Count...Specifies the number of sectors to be processed. For example, if it is "1", l sectors will be processed, and if it is "255", 255 sectors will be processed. However, if it is "0", it is assumed that "256" has been specified. does not include "skip sectors due to rDefect".

-Buffer Address...Specifies the data buffer address. The unit is 512 bytes. For example, data read in the user area is normally entered sequentially, but if there is a defective sector registered in the Grotvth list in the middle, the address of only that part is skipped. Then, leave a blank flag (Flag D) and fill in the next sector one by one, and when the replacement area is read, data is filled in the vacant area. 5ector Count specification is “1”
Otherwise, it will be the first address. There is no need to specify it with the Vertfy command.

See defect list Specify whether it is necessary or not.

For example, I made the user area read In the event that the differential If the object is included, In the effect list, first of all, Write down the location of the hole. the 256 in this parameter list above It says to process a sector. Enter the instructions. That command is If so, is this the optical disk LSI? Skip that sector for the first time. processing the remaining correct sectors. I can do that. Day when 11" Refer to the fect list and set it to “0” Refer to the defect list when Doesn't light up.

・Identifier G: Distinguishes whether it is a primary defect that is simply shifted or a growth defect that has an alternate sector. “0
When it is '1', it is a primary defect, and when it is '1', it is a growth defect. In the case of a primary defect, the sector is simply skipped, but in the case of a Groth defect, the sector is skipped and the buffer address is advanced by one sector.

・When Identifier E='1'', D
Indicates the end of the effect list.

Next, the effect will be explained.

Using FIG. 7, the needle of the optical disk controller 15 -1t
Each operation of e, Read, and Verify will be explained.

Write 7 (a) Temporarily store the user data sent from the host computer through the SC3I etc. in the data buffer.

(1) Read one sector of user data stored in the data buffer, modulate it, and send it to the BSDI. At the same time, E.C.C.
The processor generates CRC and ECC.

■After completing the transfer of empty user data, the ECC processor 16
The CRC and ECC are output from the terminal, modulated, and sent to the ESDI.

Read data sent from the optical disk through Read (7Mb Reference ■ESD I) is demodulated and only the user data portion is written to the data buffer. At the same time, the ECC processor 16 calculates the error syndrome.

(2) Demodulating the CRC and ECC parts following the user data part and inputting them to the ECC processor to complete the error syndrome calculation.

■Detect and correct errors along with error syndromes. The ECC processor 16 calculates error positions and numerical values, and the optical disk controller 15 corrects data in the data buffer.

While error correction processing is being performed, processing of ■■ of the subsequent sector is performed.

(2) Read the corrected user data from the data buffer 18 and send it out from the DMA interface.

Verif (7(c)) Demodulates the read data sent from the optical disk, inputs it to the ECC processor 16, and calculates the error syndrome.

■EC that detects errors based on error syndromes
The C processor 16 determines whether the number of errors is within an allowable range and notifies the optical disk controller 15 of the determination. While the error number determination process is being performed, the process (■) of the subsequent sector is performed.

FIG. 8 shows that in the situation shown in FIG. 10, after writing the data in the data bus sofa 18 to the optical disk,
12 is a processing flowchart of the host MPU when performing erify, and corresponds to the conventional example shown in FIG. 11. If the program is Stuft, first, 5TEP
21 is RAM for storing parameter list (P-RAM)
29, write the effect list as shown in Figure 8(b), and write the effect list in P-RAM 29 at 5TEP22 as shown in Figure 8(b).
Write the parameter list as shown in .

Here, parameter 1 collectively instructs processing of sectors PO to P16, and defective sectors are notified using a defect list. Further, parameter 2 instructs processing of sector 17. Next, in 5TEP23, specify “2” as the parameter length (parameter length = 2), and
A rite command is issued, and it is determined in 5TEP24 whether or not the command execution has ended. When the command execution is finished, specify the parameter length = 2 in 5TEP25, issue the Verify command, and return to 5TEP2.
In step 6, it is determined whether or not the command execution has ended. When the command execution is completed, the current processing ends.

Therefore, in this embodiment, the processing of parameter 1 and the processing of parameter 2 are performed consecutively, so sectors PO to P
Each of the 17 processes is completed with one command and one rotation. Furthermore, since the parameters and defect list for the Verify command may be the same as those for the Write command, there is no need to write them to the P-RAM 29 anew. As a result, processing speed can be significantly improved compared to conventional devices in which processing is interrupted every time a defect occurs or processing is interrupted when going from the user area to the replacement area.

In this embodiment, the parameter list and the defect list are stored in the parameter list storage RAM 29, but they may be stored in a part of the data buffer 18. In this way, more processes can be specified.

〔Effect of the invention〕

According to the present invention, the processing speed can be significantly improved without interrupting the processing even if the processing is different.
In addition, it is possible to reuse parameters.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention, FIGS. 2 to 8 are diagrams showing an embodiment of the optical disk controller according to the present invention, FIG. 2 is an overall configuration diagram of the optical disk controller, and FIG. Figure 4 is a block diagram of the optical disc control LSI, Figure 4 is a block diagram of another optical disc controller 'aLS■, Figure 5 is a diagram of the internal processor with built-in emulation function of the optical disc controller LSI, FIG. 6 is a diagram showing the parameter list format, FIG. 7 is a diagram for explaining each operation of Wrtte 5ReadSVerify, FIG. 8 is a flowchart showing a program for performing the -rite and Verify processing, and FIG. Figure 11 is a diagram showing a conventional optical disk controller, Figure 9 is a diagram linearly representing sectors on the optical disk, and Figure 10 is a diagram showing the sectors, primary map, and grow.
FIG. 11 is a flowchart showing a program for performing the -rite and verify processing. 1... Optical disk controller, 2...
-Host MPU. 4...Data buffer, 5...RAM for storing parameter list, 6...
... Command register, 11 ... Optical disk control device, 12 ...
・Computer, 13.14... Optical disk device, 15...
...Optical disk controller LSI, 16...
ECC processor, 17...Microprocessor, 18...
・Data buffer, 19...5C3I; 1ll111LsI. 20...driver receiver, 21...MPU interface circuit, 22...
...DMA control circuit, 23... Data buffer/ECCP control circuit,
24...Format encode/decode circuit, 25...ESDI control circuit, 26...Internal processor, 27.28.36...FIF○ memory, 29・
...RAM for storing parameter list (P-RA
M), 30... Command register, 31... Data transfer control circuit, 32...
・ECC/syndrome generation circuit, 33...E
CC/syndrome buffer, 34...Error position/numeric value detection circuit, 35...Internal processor, 41...Program ROM. 42...Sequence control/ALU computing unit, 43
...Debug control register, 44...
Emission register, 45...multiplexer (MPX), 46...internal bus. 5.15 Figure 2: Host MPU 6: Command register Figure 5

Claims (1)

[Scope of Claims] Parameter list storage means (29) capable of storing a plurality of parameters specifying processing contents for an optical disc; means (30) for storing a command given from the outside; 1. An optical disc controller comprising means (26) for sequentially performing a plurality of types of processing on an optical disc by referring to the parameters.