JPH02214329A - Semiconductor integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit incorporating a clock generation circuit.

[Conventional technology]

For example, some one-chip CPUs require several M7 clocks, and require a low-speed clock such as 32 KHz for timekeeping during standby to reduce current consumption. When multiple types of clocks are required in this way, conventionally it has been necessary to use multiple oscillation circuits using multiple crystal oscillators.

Regarding this, for example, the description in "Electronic Information and Communication Handbook 1988J (published by Ohmsha)" edited by the Institute of Electronics, Information and Communication Engineers is helpful.

[Problem to be solved by the invention]

The above-mentioned conventional technology uses a plurality of expensive crystal oscillators, and it is necessary to allocate input/output terminals of the integrated circuit to connect to the oscillators, resulting in an increase in the price of the entire system.

The present invention has been made in view of the above circumstances, and its purpose is to solve the above-mentioned problems in the conventional technology, and to make it possible to generate as many types of locks as necessary with a simple configuration. Our objective is to provide semiconductor integrated circuits.

[Means to solve the problem]

The above object of the present invention is to provide a semiconductor integrated circuit including a synchronous digital circuit, which includes an oscillation circuit using one type of external resonant element and a plurality of internal oscillation circuits that operate based on the output of the oscillation circuit. A semiconductor integrated circuit characterized in that an internal oscillation circuit generates a plurality of clocks necessary for the operation of the semiconductor integrated circuit, and when a clock is no longer needed, the corresponding internal oscillation circuit is stopped. achieved by

[Effect]

In the semiconductor integrated circuit according to the present invention, by providing a necessary number of internal oscillation circuits in the semiconductor integrated circuit,
It becomes possible to obtain an arbitrary number of clocks with a ratio of N/M. That is, it is possible to reduce the number of external vibrators to one, thereby achieving the effect that the number of external connection terminals of the integrated circuit can be reduced.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an outline of a semiconductor integrated circuit which is an embodiment of the present invention. In the figure, reference numeral 1 indicates an oscillation circuit (IC) that connects a resonator such as a crystal resonator, 2 indicates an internal oscillation circuit unit to be described later, and 3 indicates a logic circuit unit that realizes the functions of an integrated circuit. Moreover, 4 is an external resonant element such as the above-mentioned crystal oscillator.

Digital semiconductor integrated circuits generally use clocks for circuit operation, and the logic circuit section 3 shown in FIG. 1 requires two types of clocks: a first clock and a second clock. Suppose that The first clock 11 is the oscillation circuit 1
, and is directly supplied to the logic circuit section 3.

Further, the second clock 12 is generated by the internal oscillation circuit section 2 using the above-mentioned first clock as a reference.

In the internal oscillation circuit section 2, the well-known P L
Using an L (Phase Locked Loop) circuit, the first frequency is N/M times (N, M are arbitrary integers)
generates a frequency of FIG. 2 shows a specific example of its configuration.

The internal oscillation circuit section 2 in FIG. 2 has a 1/N frequency divider 22°V.
CO (Voltage Controlled 0sc
illustrator) 23° 1/M frequency divider 241 phase comparator 25. L P F (Low Pa5sF 1lte
r) Consists of 26. Further, 21 is a terminal to which the above-mentioned first clock 11 is input, and 22 is a terminal to which the above-mentioned second clock 11 is input.
This is the terminal to which the clock 12 of .

The block shown in FIG. 2 constitutes a well-known PLL circuit, which receives a first clock 11 as an input and outputs a second clock 12 having a ratio of N/M. Further, this internal oscillation circuit section 2 is connected to the output 13 (of the logic circuit section 3).
(see Figure 1), the above-mentioned second
The generation of the clock 12 can be activated or stopped. Note that it is also possible to use a frequency discriminator instead of the phase comparator 25 in FIG.

According to the above embodiment, the logic circuit section 3 is supplied with the first clock 11 generated by the oscillation circuit 1 and the second clock 12 generated from the first clock by the internal oscillation circuit section 2. Logic circuit section 3
can operate normally. That is, a plurality of clocks can be obtained using only one external resonator, and an increase in the cost of the system can be prevented. Furthermore, since the number of external vibrators can be reduced to one, the number of external connection terminals of the integrated circuit can be reduced, and the price of the integrated circuit can be reduced.

FIG. 3 shows another embodiment of the present invention, and in the figure, symbols 1 and 4 indicate the same components as shown in FIG. 2a, 2b, . . . 2n indicate internal oscillation circuit sections similar to the internal oscillation circuit section 2 described above.

In this embodiment, there are a plurality of logic circuit sections 3A (n+1
of these clocks, the first clock is generated by the oscillation circuit 1 described above, and the second to (n+1)th clocks are as follows: Based on the first clock 11 described above, n internal oscillation circuit units 2 a, 2 b, . . .
2n. The operations of the above-mentioned n internal oscillation circuit units 2a, 2b, . . . 2n are controlled by control signals 31a, 31b, .
31n.

According to the above embodiment, the logic circuit section 3A receives the first clock 11 generated by the oscillation circuit 1 and the n internal oscillation circuit sections 2a, 2b, . . . from this first clock.
Second clocks 12a, 12b generated by 2n
, . . . 12n can be supplied, and the logic circuit section 3A can be operated normally. Furthermore, since the number of external vibrators can be reduced to one, there is also the effect that the number of external connection terminals of the integrated circuit can be reduced.

Note that by using the 1/N or 1/M frequency divider shown in the above embodiment as a programmable counter, the second . Third. ...The frequency of the nth clock is
It is also possible to set from the logic circuit 3 or the logic circuit 3A.6 [Effects of the Invention] As described above in detail, according to the present invention.

In semiconductor integrated circuits including synchronous digital circuits,
It has an oscillation circuit using one type of external resonant element and a plurality of internal oscillation circuits that operate based on the output of the oscillation circuit, and generates a plurality of clocks necessary for the operation of the semiconductor integrated circuit in the internal oscillation circuit. At the same time, the structure is configured to stop the corresponding internal oscillation circuit for clocks that are no longer needed, so it is possible to realize a semiconductor integrated circuit that can generate as many types of locks as necessary with a simple structure. This has a remarkable effect.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an overview of a semiconductor integrated circuit that is an embodiment of the present invention, FIG. 2 is a diagram showing a specific configuration example of the internal oscillation circuit section in FIG. 1, and FIG. FIG. 3 is a configuration diagram showing another embodiment of the invention. 1: Oscillation circuit (IC), 2, 2 a, 2 b, "2
n: internal oscillation circuit section, 3.3A: logic circuit section, 4: external resonant element, 11: first clock, 12, 12a. 12b,...12n: Second clock. Representative Patent Attorney Masatoshi Isomura Diagram

Claims (2)

[Claims] (1) A semiconductor integrated circuit including a synchronous digital circuit, which has an oscillation circuit using one type of external resonant element and a plurality of internal oscillation circuits that operate based on the output of the oscillation circuit; A semiconductor integrated circuit, characterized in that it is configured to generate a plurality of clocks necessary for the operation of the semiconductor integrated circuit, and to stop the internal oscillation circuit corresponding to the clock that is no longer needed. (2) The internal oscillation circuit is a PLL (PhaseLock)
2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is a clock generating means applying a clock generating means (edLoop).