JPH02214337A - Standby line switching control circuit - Google Patents

Abstract

PURPOSE:To attain the switching to a standby line with priority even when the abnormality of an active line desiring to use the standby line with priority takes place later by taking a late starting channel switching signal with priority when a code requesting priority changeover is detected while a channel switching signal is stored in a latch means. CONSTITUTION:When a late arriving priority code '00000010' being information requesting priority processing is inputted even when a CH 1 switching signal is outputted and is a later coming signal defined in advance, a priority CH switching detector 340b reserves a CH 1 switching signal during output into the inside, reset signals 1, 3 go to 'H' to reset corresponding latch circuits 330(1), 330(3). Moreover, the 'H' level of the output B to the latch circuit 330(2) is held as a CH 2 switching signal and the CH 2 switching signal is outputted. Thus, even when a switch back signal, the CH switching signal during operation is reserved and the request of the late starting priority processing is correspondent immediately.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a transmission device having a regular line and a protection line, and particularly relates to a control circuit that controls switching by giving priority to the protection line when the regular line that requests priority processing becomes abnormal. The purpose of the present invention is to provide a protection line switching control circuit that allows preferential use of the protection line when the protection line is in operation.Even if an abnormality occurs later on in the regular line, the protection line can be switched to the protection line with priority. When the switching information issued later from the switching control unit is a switching signal to another channel, after the latch means is cleared with a signal developed by the switching back decoder from the switching signal for the earlier channel switching signal. If the priority channel switching control means detects a signal requesting priority processing over the previous channel switching signal already held in the latch means, the priority channel switching control means switches the other channels to the protection line. The first channel switching signal held is held, the latch means clears the signal held, and the latch means holds and outputs a switching signal for switching the later channel to the protection line. .

[Industrial Field of Application] The present invention relates to a transmission device having a regular line and a protection line, and particularly relates to a control circuit that controls switching by giving priority to the protection line when the regular line that requests priority processing becomes abnormal. .

For example, in a transmission device where one protection line is prepared for every n regular lines, if one of the n regular lines becomes abnormal, that line is switched to the protection line, and the line is operated through the protection line. be done.

At this time, in order to switch back the line that was previously switched to the protection line back to the original regular line, the current control method requires that unless a switch-back command is issued, the other line becomes abnormal and the line is switched back to the backup line. Even if a switching command is issued, the switching cannot be handled.

Therefore, even if, for example, an important line becomes abnormal and requires priority processing, it will not be possible to switch over if the protection line is already in operation.

If such an important line becomes abnormal and requires priority processing,
It is necessary to be able to perform switching processing with priority even if the processing occurs later.

[Conventional technology]

FIG. 4 is a diagram explaining the issuing status of switching information to the protection line switching control circuit, FIG. 5 is a diagram explaining a conventional example of the protection line switching control circuit, and FIG. 6 is a diagram explaining the conventional example of the protection line switching control circuit. Figures illustrating examples of switching control are shown.

FIG. 4 shows an outline of the configuration of a transmission device in which n channels (CHI to CHn) are used as regular lines and one channel is installed as a protection line. The switch unit 1.2 is provided on the input and output sides of n regular lines and one protection line for signal transmission, and includes protection line switching control circuits 3a and 3b.
are each implemented.

On the other hand, the switching control unit 4 includes backup line switching control circuits 3a and 3b.
The on/off and switching of the switch section 1.2 is synchronously controlled via the switch unit 1.2, and alarms (ALMI to ALMn) that are issued when the regular line is unusable due to disconnection etc. are sent from a monitoring/alarm panel (not shown). Upon detection, a switching control command is issued to the protection line switching control circuits 3a and 3b within the switch section 1.2.

Note that this alarm (ALMI to ALMn) signal is an alarm issued for each regular line.

A protection line switching control circuit 3a in the switch sections 1 and 2.

3b and the switching control section 4 are connected by a bus, and the switching control information from the switching control section 4 to the backup line switching control circuits 3a and 3b has the same content.

That is, the switching control information consists of a chip select signal for selecting the switching CH, a clock CLK for specifying the switching timing, and an 8-bit serial code [phase] for specifying the switching CH.

The detailed configuration of the protection line switching control circuits 3a and 3b that receive such switching control information is shown in FIG. (hereinafter referred to as OR circuit) 34
and a switchback decoder 35.

Further, the serial/parallel conversion circuit 31 shown in FIG.
The decoder 32 converts the 8-bit serial code [phase] sent from the switching control section 4 shown in FIG. 4 into an 8-bit parallel code. parallel cord to C
The latch unit 33 develops the CH switching signal (CH1 switching signal to C) (n switching signal) that is developed by the decoder 32. In order to hold the output of the decoder 32, the OR circuit 34 logically adds the CH switching signals in the output state to the latch circuits 33(1) to 33() corresponding to the CHs forming the latch unit 33. n)
The reversal decoder 35 outputs an 8-bit serial code.
A cutback code for reversing switching to the protection line■
In this case, it is detected and developed into a signal @ for clearing the latch section 33.

Next, FIG. 6 shows details of the switch switching information outputted from the switching control section 4 to each protection line switching control circuit 3a, 3b having the above-described configuration.

That is, the 8-bit serial code [phase] output from the switching control section 4 is "O" shown in Examples 1 to 3 in FIG.
OO00001” or “00000010pa” or “1000
0000'' etc. After this serial code 0 is output, the chip select signal rises and selects the CH with I displayed in the serial code [phase].
The switching timing to the selected CH is clock CLK.
Specified by.

In addition, the serial code [phase] in this example sets CHI switching to “0”.
0000001", and the code that requests priority processing even when CH2 is switched and is a late arrival is "00000010".
Set the cutback code “1” to return from the protection line to the regular line.
0000000", codes that have no meaning other than codes for CH switching, failback, or no CH switching are set to "0000000".
This is the case where it is set to 00011n.

In addition, the switching signals CHI to CHn in the figure are connected to the backup line switching control circuit 3a shown in FIG.
3b is a signal that is expanded and output, and the rising edge indicates the output state.

Here, in example 1 of FIG. 6, the CHI switching code "0000"
The code “000” which has no meaning after 0001’”
Example 2 is a CHI switching code “oooooooo”.

CH2 switching code ゛0000001 that requests switching with priority over the first arrival (requests priority for the last arrival) after "f"
Example 3 is the case where CHI switching code "oooooo" is issued.

This is a case where the cutback code "1000σ000" is issued next to "1".

Next, as explained in FIG. 5, the holding signal 0 is for holding the CH switching signal in the output state, and indicates the output state at the rising edge.

From now on, the output state of a signal etc. will generally be indicated by "H11", and the non-output state or zero state will be indicated by "L"'.

For example, in a normal state where no abnormality has occurred, the backup line switching control circuits 3a and 3b are
o o o o o o o” serial code [
phase] is received.

Even if the decoder 32 develops this, the switching signals of each CHI~n will all be in the "L" state, and therefore the holding signal O, which is the output of the logical sum of these signals in the OR circuit 34, will also be "L". .

Each latch circuit 33 (1) to 33 (n) is an OR circuit 3
The output (corresponding to the clock) obtained by taking the logical sum of 4 is L''
In this case, the decoder 3 uses the 8-bit parallel code.
The CH switching signal developed in step 2 is output as is without switching.

Next, for example, when the CHI becomes abnormal and the protection line is unused, the serial code [phase] "ooooo" is sent as shown on the left side of Examples 1 to 3 in FIG.

01 is input to the protection line switching control circuits 3a and 3b, and the decoder 32 develops the CHI switching signal into 'H++ and outputs it.

In this case, if the protection line is in use, the corresponding latch circuit 33 (1
) is cleared by another CH switching signal, making it impossible.

Next, when the CHI switching signal is output at "°H", the output of the OR circuit 34 also becomes "H++", and the latch circuit 3
3(1) latches and holds the CHI switching signal.

While the CHI switching signal continues to be held in the latch circuit 33 (1), other switching command codes, such as the code "OO000010" which instructs to process the switching of CH2 shown in Example 2 of FIG. 6 with priority, are executed. , a switching instruction code, a switchback code, and a meaningless code that has no meaning other than a code indicating no switching (such as the following code in Example 1 in Figure 6)
ooooo.

011") is input, it is ignored and the CHI switching signal is continuously output.

Next, when the CHI returns to the normal state, the protection line switching control circuits 3a and 3b output the serial code [phase] "10oooooo".
Example 3 in FIG. 6 shows a state in which the decoder 35 receives the signal ``o'' and expands it by the switchback decoder 35.

That is, serial code (10) ” 10000000
``The serial/parallel conversion circuit 31 converts the code into a parallel code ■, which is detected by the switchback decoder 35.
The developed signal @ is outputted as °“HII, and this causes the latch circuit 33 (1) to 33 in the latch section 33 to
Clear all of (n).

Incidentally, since the decoder 32 develops "°L" at this time, the latch section 33 continues to operate until the CHI switching signal clears the latch section 33.

Next, since the latch circuit 33 (1) in the latch section 33 is cleared, the CHI switching signal and the holding signal [phase] of the OR circuit 34 return to "L", and the protection line is released from the operating state. The next CH switching instruction code can now be accepted.

Incidentally, in example 2 of FIG. 6, the serial code [phase] is "oo".

CH2 that requests last-arrival priority switching after “00001”
Even if the switching code “00000010” is issued from the switching control unit 4 shown in FIG.
0000000” is not expanded before that, so CH
This shows a state in which the CH2 switching signal cannot be switched to CH2, and therefore the CH2 switching signal is not output and the CHI switching signal is continuously output.

[Problem to be solved by the invention]

As mentioned above, the protection line switching control circuit 3a shown in FIG.
In the conventional example of 3b, if the protection line is in the operational state after switching to another channel, the switching to another channel is not possible unless the protection line is cleared in the operational state (“H” state) with a switchback signal. If you receive a code, ignore it.

That is, even if, for example, a regular line whose protection line is to be used preferentially becomes abnormal, if the protection line is in operation at that time, it will not be possible to switch to the protection line unless a switchback signal is detected.

To provide a protection line switching control circuit capable of preferentially using the protection line when the protection line is in an operating state and switching to the protection line with priority even if an abnormality occurs later on in the regular line. With the goal.

[Means to solve the problem]

FIG. 1 shows a diagram explaining the principle of the protection line switching control circuit of the present invention.

The principle diagram of the protection line switching control circuit 3' of the present invention shown in FIG. The above-mentioned latch means 330 holds the channel switching signal developed by the decoder 32, and the priority channel switching control means 340 holds one channel switching signal in the latch means 330. If a code requesting priority switching is detected as information requesting next channel switching while the channel switching is being performed, control is performed to give priority to the subsequent channel switching signal, and the system is equipped with such means. This is the only way to solve this problem.

[For production]

The decoder 32 develops channel switching information input from the switching control unit 4 that instructs switching from the regular channel to the backup channel, and while this is held as a CH switching signal in the latch means 330, the next Even if channel switching information is input, unless the switching back decoder 35 clears the latch unit 330, the next channel switching cannot be performed and the previous CH switching signal continues to be held in the latch unit 330.

On the other hand, if the next channel switching information is a later arriving priority processing signal that requests priority processing over the earlier channel switching signal,
The priority channel switching control means 340 that has detected this signal suspends the currently transmitted CH switching signal held in the latch means 330, and also switches the latch means 330 to the first channel switching signal.
The holding of the H switching signal is cleared, and the CH switching signal corresponding to the last arrival priority switching information is held and sent with priority.

Then, when the process corresponding to the last arrival priority switching process is completed, the priority channel switching control means 340
The H switching signal is set in the latch means 330 and the corresponding CH switching signal is sent out.

By performing the above-described processing, even if the protection line is in operation, when a signal for late-arrival priority processing is detected, it is possible to immediately prioritize and switch over.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a diagram illustrating an embodiment of the protection line switching control circuit of the present invention, and FIG. 3 is a diagram illustrating a time chart in the embodiment of the protection line switching control circuit of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

Protection line switching control circuits 3c and 3d of the present invention shown in FIG.
The embodiment is based on the protection line switching control circuit 3 explained in FIG.
A latch portion 330a is used as a latch means 330 constituting the
This is an example in which the priority channel switching control means 340 includes a priority CH switching control section 340a.

Note that the present embodiment shown in FIG.
In addition to 340a and 340a, a serial/parallel conversion circuit 31, a decoder 32, and a switchback decoder 35 are provided, which operate in the same manner as described in FIG.

In addition, this embodiment shown in FIG. 2 has three regular lines (CHI
.about.CH3) and one backup line. FIG. 3 shows the serial code [phase] and chip select signal instructed by the switching control section 4 shown in FIG. 4 in the above embodiment. The output states of the CH switching signals developed by the protection line switching control circuits 3c and 3d based on the serial code [phase] and the serial code [phase] are shown in three examples.

Further, Examples 1 to 3 in FIG. 3 are operation examples when the same serial code ■ as in Examples 1 to 3 explained in FIG. 6 is input from the switching control unit 4 shown in FIG. The serial code [phase] example also uses the same code.

Next, the reset signals 1 to 3 (D to F) in FIG.
0 (1) to 330 (3) output “L” or “H”
This is a signal for

The latch section 330a of this embodiment shown in FIG.
It consists of (1) to 330 (3).

In addition, the above-mentioned reset signals 1 to 3 (D-F) are the SR current type 797 forming the latch circuits 330 (1) to 330 (3).
It is sent to the reset terminal R of the 1207 circuit, and the output A-C developed by the decoder 32 is sent to the set terminal S.
sent to.

Normally, in an SR type flip-flop circuit, the set terminal S is “
When the reset terminal R is "H" and the reset terminal R is "L", the positive output Q outputs "H++", and when the reset terminal R is "H" and the set terminal S is "L", the positive output Q is “Lo”
Output.

Next, the priority CH switching control section 34 of this embodiment shown in FIG.
0a consists of a priority CH switching detection section 340b and a reset signal generation section 340c, and the priority CH switching detection section 340b
In this case, the decoder 32 outputs “H” for output B that requests priority switching.
”, this is detected and the CH switching signal that has been in the “H11 state” is suspended. Section 340b
The latch circuits 330(1) to 330(3)
) signal D-FC to make the output “L” or “Hu”
It creates and outputs reset signals 1 to 3).

From the serial code [phase] converted by the decoder 32 into a parallel code by the serial/parallel conversion circuit 31, a meaningless code "000" other than a code that requests switching for each CH or a code that does not request switching for each CH is generated.
00011'' is detected, its outputs A-C are developed so as to continue the CH switching signal up to that point.

On the other hand, the serial code [phase] is the code for switching CHI to the protection line, as shown in Examples 1 to 3 in Figure 3.
In the case of 00001°, the decoder 32 develops it into a CHI switching signal and makes the output A “H++”.

Then, when the chip select signal becomes “H”, the C
In order to select HI switching, a CHI switching signal (corresponding to output A) is latched into the latch circuit 330 (1) and output.

At this time, the reset signal generation section 340C
0 Latch circuits other than (1) 330 (2) 330 (3
) signals E and F are created to reset the output to "L" at the time of rising to the output.

However, before the code “OOOOOO001”, the latch part 3
For example, when latching the CH3 switching signal with 30a,
When the output C of the decoder 32 is "H", the reset signal generator 340C outputs it.

E becomes "H11" and the latch circuit 330 (1).

330 (2), the CHI switching signal cannot be held in the latch circuit 330 (1).

In addition, in this embodiment, the predefined switchback code "
10000000'' is input and the decoder 35 for switchback detects this, the signal ■ developed by the decoder 35 for switchback is the latch circuit 330 (1) to 330 (3
) all at the same time. The processing after clearing is the same as that described in FIG. 5.

Also, the time chart at this time is as shown in Example 3 in Figure 3, the CHI switching signal in the output state is cleared and changes from "H" to "Lo", and the reset signal 2.3 (outputs E, F) also becomes "L". ” becomes.

Next, the switching information input to the protection line switching control circuits 3c and 3d is applied to each C
A code “0” that has no meaning other than a code that requests H-compatible switching or a code that does not request CI-compatible switching
0000011", the outputs A-C of the decoder 32 become "L11" and are output.

Therefore, the C)11 switching signal held in the latch circuit 330 (1) continues to be sent.

Incidentally, at this time, the output E of the reset signal generation section 340C,
F becomes "H++" and the latch circuit 330 (2).

330 (3) Latch circuit 33 for heli-set
+1 L II for the output of 0 (2), 330 (3)
is retained.

Next, for example, as in Example 2 of FIG. 3, <Last Arrival Priority Code "00000", which is information that requests priority processing even for later arrivals defined in advance while the CHI switching signal is being output.
010'' is input, it is converted by the serial/parallel conversion circuit 31 and expanded by the decoder 32, and the result is output B.
is set to “H”.

The priority CH switching detection unit 3 detects that this output B has become H”.
When detected by the decoder 40b, the CHI switching signal being output is held internally and the output B of the decoder 32 is set to “Ho”.
is drawn into the reset signal generation unit 340C, and a reset signal 1 is generated based on the signal from the priority CH switching detection unit 340b.
．． 3 (output.

F) is set to "H" to reset the corresponding launch circuits 330(1) and 330(3).

On the other hand, the “H” level of the output B is sent to the latch circuit 330(2).
The CH2 switching signal is held as an H2 switching signal, and this CH2 switching signal is output.

Next, when the CH2 switching process of the priority processing request is completed, the output B of the decoder 32 becomes "L", so that the CH2 switching signal becomes "L".

The priority CH switching detection unit 340b, which was monitoring this CH2 switching signal, sends the held CHI switching signal to “H”.
The reset signal generation unit 340c creates a signal to make the output of the latch circuit 330 (1)
Reset it to "H" and output the CHI switching signal again.

As described above, as shown in Examples 1 to 3 of FIG. 3, the embodiment of the present invention suspends the CH switching signal in operation even if there is no switching back signal when there is a request for late priority processing. It becomes possible to immediately respond to requests for late priority processing.

〔Effect of the invention〕

According to the present invention as described above, even if the protection line is in operation, when the last arrival priority switching code is input, the protection line switching is capable of immediately switching the regular line compatible with the last arrival priority switching code to the protection line. A control circuit can be provided.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the protection line switching control circuit of the present invention, Fig. 2 is a diagram explaining an embodiment of the protection line switching control circuit of the invention, and Fig. 3 is a diagram explaining the protection line switching control circuit of the invention. 4 is a diagram illustrating the issuing status of switching information to the protection line switching control circuit; FIG. 5 is a diagram illustrating a conventional example of the protection line switching control circuit; 6 is a diagram illustrating an example of switching control of the protection line switching control circuit. In the figure, 1.2 is a switch section, 3a to 3d, 3' are a protection line switching control circuit, 4 is a switching control section, 31 is a serial/parallel conversion circuit, 32 is a decoder, 33.330a is a latch section,
33(1) to 33(n), 330(1) to 330
(3) is a latch circuit, 34 is an OR circuit, 35 is a decoder for switching back, 330 is a latch means, 340
340a is a priority channel switching control unit, 340b is a priority CH switching detection unit, and 340c is a reset signal generation unit. Fig. 1 Main gold a day 9 reservation account won P
Zfi Kero Time Now Yard Beggar 1 Child β Tsukizuro Figure 7 3
Figure 4

Claims (1)

[Scope of Claims] A switching control unit (4) that detects an unusable line among a plurality of regular lines and issues information for switching to a protection line, and receiving switching information from the switching control unit (4). a decoder (32) that develops a signal for switching to the protection line
and a protection line switching control circuit (3') having a cutback decoder (35) that detects a signal for switching back the protection line to the regular line, wherein the decoder (32) latch means (330) for holding the developed channel switching signal; and the decoder (32).
), a priority channel switching control means (340) performs control to give priority to the later channel switching signal when detecting a signal requesting priority switching over the earlier signal from the later developed signals. and when the switching information issued later from the switching control unit (4) is a switching signal to another channel, the switching control unit (4)
), the other channel is switched to the protection line only after the latch means (330) is cleared by a signal developed by the cut-back decoder (35), and the latch means (330) When the priority channel switching control means (340) detects a signal requesting priority processing over the previous channel switching signal already held, the priority channel switching control means (340) controls the latch means ( 330), and clears the signal held by the latch means (330), and transmits a switching signal for switching the later channel to the protection line. (330) A protection line switching control circuit characterized by holding and outputting to (330).