JPH04138728A - Active and reserve changeover system - Google Patents

Active and reserve changeover system

Info

Publication number
JPH04138728A
JPH04138728A JP26192790A JP26192790A JPH04138728A JP H04138728 A JPH04138728 A JP H04138728A JP 26192790 A JP26192790 A JP 26192790A JP 26192790 A JP26192790 A JP 26192790A JP H04138728 A JPH04138728 A JP H04138728A
Authority
JP
Japan
Prior art keywords
circuit
reserve
active
working
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26192790A
Other languages
Japanese (ja)
Inventor
Yoshihide Kuroda
黒田 芳秀
Hiroshi Takeda
浩 武田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Miyagi Ltd
Original Assignee
NEC Corp
NEC Miyagi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Miyagi Ltd filed Critical NEC Corp
Priority to JP26192790A priority Critical patent/JPH04138728A/en
Publication of JPH04138728A publication Critical patent/JPH04138728A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To change over the active and the reserve circuit without causing momentary interruption of a data by generating an active/reserve changeover control signal based on a generated reference clock and latching the changeover control signal with the reference clock so as to select the active circuit or the reserve circuit. CONSTITUTION:A timing clock 11 from a unified clock source 2 is fed respectively to a changeover control circuit 1, an active circuit 3 and a reserve circuit 4. When the active/reserve changeover is implemented by a prescribed method, the changeover control circuit 1 generates set signals 12, 14 synchronously with a falling point A of the timing clock 11 to output them to the active circuit 3 and the reserve circuit 4 respectively. The active circuit 3 and the reserve circuit 4 latch the set signals 12, 14 respectively at a succeeding rising point B of the timing clock and the active circuit 3 is switched to the reserve side and the reserve circuit 4 is respectively simultaneously changed to the active side.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はデジタル伝送装置の現用・予備切替回路に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a working/standby switching circuit for a digital transmission device.

〔従来の技術〕[Conventional technology]

従来、完全二重化の冗長構成を持ち複数の現用・予備回
路を一斉に切替えるデジタル伝送装置の現用・予備切替
え方式は、現用・予備切替制御信号を送出する切替制御
回路が具備するタイミングクロックに同期した切替信号
を生成し、切替えるべき複数の現用および予備回路に送
出していた。
Conventionally, the working/standby switching method of digital transmission equipment that has a fully duplex redundant configuration and switches multiple working/standby circuits at the same time is synchronized with the timing clock provided in the switching control circuit that sends the working/standby switching control signal. A switching signal was generated and sent to multiple working and backup circuits to be switched.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

この従来の現用・予備切替方式は、切替制御回路が生成
する切替制御信号と現用・予備回路が扱っているデータ
のフレーム同期とが非同期であるため、現用・予備切替
時にデータの瞬断が発生する欠点があった。
In this conventional working/protection switching method, the switching control signal generated by the switching control circuit and the frame synchronization of the data handled by the working/protection circuit are asynchronous, so instantaneous data interruption occurs when switching between the working and protection circuits. There was a drawback.

本発明の目的は、データの瞬断がない現用・予備切替方
式を提供することにある。
An object of the present invention is to provide a working/standby switching system that does not cause instantaneous data interruption.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の現用・予備切替方式は、生成した基準クロック
をもとに現用・予備の切替制御信号を生成し、この切替
制御信号を前記基準クロックでラッチして現用回路と予
備回路とを切替えるもので、基準クロックを生成する基
準クロック発生手段と、この基準クロック発生手段が出
力する基準クロックを受け現用・予備切替制御信号を生
成する切替制御信号生成手段と、この切替制御信号生成
手段の出力する切替制御信号と前記基準クロックとを受
け、この基準クロックにより前記切替制御信号をラッチ
し、そのタイミングで現用回路と予備回路とを切替える
現用・予備切替手段とを備えている。
The working/protection switching method of the present invention generates a working/backup switching control signal based on the generated reference clock, and latches this switching control signal with the reference clock to switch between the working circuit and the protection circuit. a reference clock generating means for generating a reference clock; a switching control signal generating means for receiving the reference clock outputted by the reference clock generating means and generating a working/standby switching control signal; The circuit includes working/standby switching means that receives the switching control signal and the reference clock, latches the switching control signal using the reference clock, and switches between the working circuit and the standby circuit at that timing.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を示すブロック図、第2図は
切替動作を示すタイムチャートである。第1図の現用・
予備切替方式は、現用・予備切替手段号を出力する切替
制御回路1と、現用回路3および予備回路4が扱うデー
タに同期した統一クロックを切替制御回路1.現用回路
3.予備回路4に送出する統一クロック源2とから構成
される。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a time chart showing a switching operation. Current use in Figure 1
In the backup switching method, a switching control circuit 1 outputs a working/standby switching means signal, and a unified clock synchronized with data handled by the working circuit 3 and the protection circuit 4 is used in the switching control circuit 1. Current circuit 3. It consists of a unified clock source 2 that sends out to a backup circuit 4.

ここで現用回路3を予備に、また予備回路4を現用に切
り替えるとする。
Here, it is assumed that the current circuit 3 is switched to the backup circuit and the backup circuit 4 is switched to the current circuit.

第2図において統一クロック源2からタイミングクロッ
ク11が、切替制御回路1.現用回路3、予備回路4に
それぞれ供給されている。所定の方法で現用・予備切替
操作を行うと、切替制御回路1はタイミングクロック1
1の立下がりA点に同期したセット信号12および14
を生成して、現用回路3および予備回路4にそれぞれ出
力する。現用回路3および予備回路4は、タイミングク
ロックの次の立上がりB点でセット信号12および14
をそれぞれラッチし、現用回路3が予備側に、また予備
回路4が現用側にそれぞれ同時に切替わる。
In FIG. 2, a timing clock 11 is supplied from a unified clock source 2 to a switching control circuit 1. It is supplied to the current circuit 3 and the backup circuit 4, respectively. When the working/standby switching operation is performed in a predetermined manner, the switching control circuit 1 switches to the timing clock 1.
Set signals 12 and 14 synchronized with falling point A of 1
is generated and output to the current circuit 3 and backup circuit 4, respectively. The current circuit 3 and the backup circuit 4 receive set signals 12 and 14 at the next rising edge of the timing clock at point B.
are latched, and the working circuit 3 is switched to the standby side, and the standby circuit 4 is switched to the working side at the same time.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、現用・予備回路を切替え
るためのMal信号が扱うデータのフレームヘッドと同
位相となるため、データの瞬断を起すことなく現用・予
備回路の切替えができる効果がある。
As explained above, the present invention has the effect that the Mal signal for switching between the working and backup circuits is in the same phase as the frame head of the data handled, so that the switching between the working and backup circuits can be performed without causing a momentary data interruption. be.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すブロック図、第2図は
その動作を示すフローチャートである。 1−・・切替制御回路、2・・・統一クロック源、3・
・−現用回路、4・・・予備回路。
FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG. 2 is a flow chart showing its operation. 1-...Switching control circuit, 2...Unified clock source, 3-...
- Working circuit, 4... Reserve circuit.

Claims (1)

【特許請求の範囲】 1、完全二重化された冗長構成をもつデジタル伝送装置
の現用・予備切替方式において、生成した基準クロック
をもとに現用・予備の切替制御信号を生成し、この切替
制御信号を前記基準クロックでラッチして現用回路と予
備回路とを切替えることを特徴とする現用・予備切替方
式。 2、基準クロックを生成する基準クロック発生手段と、
この基準クロック発生手段が出力する基準クロックを受
け現用・予備切替制御信号を生成する切替制御信号生成
手段と、この切替制御信号生成手段の出力する切替制御
信号と前記基準クロックとを受け、この基準クロックに
より前記切替制御信号をラッチし、そのタイミングで現
用回路と予備回路とを切替える現用・予備切替手段とを
有することを特徴とする前記請求項1記載の現用・予備
切替方式。
[Claims] 1. In a working/standby switching system for a digital transmission device with a fully duplex redundant configuration, a working/standby switching control signal is generated based on the generated reference clock, and this switching control signal is A working/standby switching method characterized in that the working circuit and the standby circuit are switched by latching the signal with the reference clock. 2. a reference clock generation means for generating a reference clock;
A switching control signal generating means receives a reference clock output from the reference clock generating means and generates a working/standby switching control signal; 2. The working/standby switching system according to claim 1, further comprising working/standby switching means for latching the switching control signal using a clock and switching between the working circuit and the standby circuit at that timing.
JP26192790A 1990-09-28 1990-09-28 Active and reserve changeover system Pending JPH04138728A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26192790A JPH04138728A (en) 1990-09-28 1990-09-28 Active and reserve changeover system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26192790A JPH04138728A (en) 1990-09-28 1990-09-28 Active and reserve changeover system

Publications (1)

Publication Number Publication Date
JPH04138728A true JPH04138728A (en) 1992-05-13

Family

ID=17368647

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26192790A Pending JPH04138728A (en) 1990-09-28 1990-09-28 Active and reserve changeover system

Country Status (1)

Country Link
JP (1) JPH04138728A (en)

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