JPH022145A - Semiconductor device - Google Patents

Abstract

PURPOSE:To avoid the increase of a metal wiring length caused by detouring and improve the performance of a semiconductor device by a method wherein a priority is given to the wirings for polycrystalline silicon terminals in a same cell row and, further, the lengths of the polycrystalline wirings having relatively high electric resistances are limited. CONSTITUTION:First, the metal terminal m3 of a cell row l1 is connected to the polycrystalline silicon terminal P3 with a metal first layer wiring 3a and a polycrystalline silicon wiring 5a through a through-hole 6. In the same way, the wirings in cell rows l2 and l3 are provided. If the summation of the lengths of the polycrystalline silicon wirings 5a, 5b, 5c and 5d reaches a predetermined polycrystalline silicon wiring length, the other wirings in the same cell row are discontinued. It is not necessary to consider the position relations between the wirings in the cell rows and between the mutual cell rows and, further, it is not necessary to provide detour wirings in the wirings of the metal first layer and the metal second layer, so that the wiring length can be reduced.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor device realized by automatically wiring signal terminals of standard cells based on a predetermined wiring design, the present invention relates to a semiconductor device that limits the polysilicon wiring length and reduces the metal wiring length. A cell row (l) formed by arranging a plurality of cells (2) for the purpose of providing a semiconductor device with improved performance by reducing
In a semiconductor device having a plurality of cell rows (, 11), metal terminals (l) or polysilicon terminals (P) formed at equal potential are automatically wired at predetermined positions on both sides of the cell array direction, The polysilicon terminal (P) on one side of the same cell row (l) is wired preferentially using the metal first layer wiring (3) and the polysilicon wiring (5), and is used as a lead wiring from the polysilicon terminal fP). When the total length of the polysilicon wiring (5) reaches a predetermined length, wiring within the same cell column (l) is stopped, and unwired metal located on the opposite side of the cell column (l) is discontinued. 1m wiring possible for metal 11th wiring (8) from terminal (n+) and polysilicon terminal (P)
A lead wire is formed at position (y), and the lead wire is connected by a second metal layer wire (8) to provide wiring between cell columns.

[Industrial application field]

The present invention relates to a semiconductor device that is realized by automatically wiring Shingetsu terminals of standard cells based on a predetermined wiring design.

In recent years, a so-called standard cell method has been adopted as one method for designing semiconductor devices with higher density and smaller area. In this standard cell method, a standard cell is prepared in which several types of cell rows formed by arranging multiple cells are arranged on a semiconductor substrate in advance, and each cell row is arranged based on given logic design specifications. A semiconductor device is realized by wiring signal terminals between cell columns.

[Conventional technology]

Normally, the shape of a standard cell is as shown in FIG. 5, in which a cell row O is made up of cells 2 arranged on a semiconductor substrate 1, and metal terminals m and A polysilicon terminal P is formed. As shown in FIG. 6, the wiring of the metal terminal m and the polysilicon terminal P is as shown in FIG.
The first metal layer wiring 3 is used, the metal first layer wiring 4 of the same layer is used to lead out from the metal terminal In to the metal first layer wiring 3, and the lead out from the polysilicon terminal P to the metal first layer wiring 3 is as follows. This is done by connecting the polysilicon wiring 5 as the lead wiring and the first metal layer wiring 3 through a through-hole 6 (not shown). Further, wiring passing above the cell row 1 is performed by a metal second layer wiring 8 connected to the metal first layer wiring 3 through a through hole 7 (not shown).

Figures 7 to 9 show metal terminal m and polysilicon terminal P.
FIG. 7 is an explanatory diagram showing a conventional wiring array, and first, in FIG. 7, the metal terminals In,
Polysilicon terminals p, p; polysilicon terminals p, p of cell row 1, metal terminals m1, m31 of cell row.
A predetermined wiring including a metal first layer wiring 3, a polysilicon:1-layer wiring 5, and a metal second layer wiring 8 is formed on the In4 and polysilicon terminal P2. °In this case, metal second
The wiring of the layer wiring 8 is limited to the line y1 to y5 in the figure, and has a predetermined wiring interval d. Therefore, the through pole 7 for connecting the first metal layer wiring 3 and the second metal layer wiring 8 must be provided on the line y1 to y5 in the figure.

Next, as shown in FIG. 8, the remaining signal terminals, namely metal terminals m 1 and m 3 of cell row j1, polysilicon terminals P 1 and P , and metal terminal I of cell row 12
n, m2 + m3, polysilicon terminal P1゜P
2; Metal terminal m2 and polysilicon terminals P and P3 of cell row g3 are connected to metal first layer wiring 3.2; They are connected by predetermined wiring including polysilicon wiring 5 and metal second layer wiring 8. As a result, wiring as shown in FIG. 9 is formed.

[Problem to be solved by the invention]

However, polysilicon wiring has a larger electrical resistance than metal wiring, and if the length of the polysilicon wiring becomes long, it causes a decrease in the performance of the semiconductor device, but in conventional semiconductor devices, there is a limit to the ability to shorten the length of the polysilicon wiring. In addition, in order to avoid curved wiring, it is sometimes necessary to use metal wiring that takes a detour, which unnecessarily increases the length of metal wiring and hinders the performance improvement of semiconductor devices. That is, polysilicon wiring 5a in FIG.

5b and 5c are other wirings (metal first layer wiring 3a).

3b, 3c), it is necessary to make the polysilicon wiring length longer than the normal polysilicon wiring length (half the distance between each cell column 1), and the polysilicon wiring length of cell column g2;
The length of the wiring between the contact terminal P3 and the metal terminal In3 must be significantly increased in order to bypass the metal first layer wiring 3d, 3e and the metal second layer wiring 8a that have already been provided.

An object of the present invention is to provide a semiconductor device whose performance is improved by limiting the length of polysilicon wiring and reducing the length of metal wiring.

[Failure to solve the problem]

The present invention has a plurality of cell rows (, 11) formed by arranging a plurality of cells (2), and each cell row (l) is formed at a predetermined position on both sides of the cell arrangement direction at an equal potential. In a semiconductor device in which metal terminals (ln) or polysilicon terminals (P) are automatically wired, one side of the polysilicon terminals (P) in the same cell row (l) is connected to the metal first layer wiring (3).
and polysilicon wiring (5), and when the sum of the lengths of the polysilicon wiring (5) as lead wiring from the polysilicon terminal (P) reaches a predetermined length, the same cell column The wiring in (l) is discontinued, and the unwired metal terminal (Im
), from the polysilicon terminal (P) to the metal second layer wiring (8
), and the lead wires were connected by second layer metal wires (8) to provide wiring between the cell columns.

[Effect]

Polysilicon wiring on one side of the same cell row in the cell arrangement direction: Prioritize wiring within the same cell row using polysilicon wiring and metal first layer wiring for the 1-pin terminal, and when the polysilicon wiring length reaches a predetermined length. , pull out the unwired polysilicon terminals and metal terminals on the opposite side of the cell row to a position where the metal second layer wiring can be wired, and connect this drawn wiring to the metal second layer wiring.
A semiconductor device is formed by interconnecting cell columns by layer wiring.

Such semiconductor devices have short polysilicon wiring,
In addition, an increase in metal wiring length due to bypassing the first metal layer wiring and second metal layer wiring of the song is prevented.
Performance will be significantly improved.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing one row of cell row layers formed on a semiconductor substrate 1, and each cell row, Il (in the illustrated example, 11 to j3
) is formed by arranging predetermined cells 2, and each cell 2
Metal terminals m and polysilicon terminals P are arranged at predetermined positions on both sides in the cell arrangement direction so that they have equal potential (
Cell row J11 has metal terminals m1 to 1n3 and polysilicon terminals P1 to [); cell row 1 has metal terminals m1 to f
n3, voltage: 1-terminals P1-P5; cell row j3 has metal terminals m1-1n4, polysilicon terminals P1-P
3 are arranged respectively).

In the present invention, wiring of polysilicon terminals 1n in each cell column I11 to j3 is first performed.

In FIG. 2, one side of cell row j11 in the cell arrangement direction +l
! The metal terminal m3 and the polysilicon terminal P3 of II (lower side of the figure) are wired by connecting the metal first layer wiring 3a and the polysilicon wiring 5a through the through hole 6. Similarly, between the metal terminal 1n of the cell row 12 and the polysilicon terminal P1, between the metal terminal m3 and the polysilicon terminal 23, and between the metal terminal In of the cell row I13 and the polysilicon terminal 23, the metal first layer wiring 3b, 3c,
3d, and are connected by polysilicon wirings 5b, 5c, and 5d, respectively. In this case, the polysilicon wiring drawn out from each polysilicon terminal P does not have to take into consideration the wiring position of the metal second layer wiring 8, which will be described later, so the minimum length of the polysilicon wiring is sufficient. Then, when the sum of the lengths of the polysilicon wirings 5a, 5b, 5c, and 5d reaches a predetermined polysilicon wiring length, wiring in other same cell columns is stopped.

Next, as shown in FIG. 3, unwired metal terminals 1n (m, ln2 of cell row 1;
1n1 of cell row 13; m 1 and m 3 of cell row 13.

m ) and polysilicon terminals P (P1p, p of cell row j1
; P, P4 of cell column 1. P5; P, P2 of cell column 1
) is formed with a lead wiring for wiring using the metal second layer wiring 8. Here, since the metal second layer wiring 8 is wired only at the wiring possible positions y to y5 with the interval d, in order to wire with the metal second layer wiring 8,
Is it necessary to pull it out to a position where it can be wired as shown below?

That is, the metal terminal In is pulled out by the metal first layer wiring 3 to a position where it can be wired to the nearby metal second layer wiring 8, forming a through pole 7, and making it possible to wire with the metal second layer wiring 8. be done.

Further, the polysilicon terminal P is drawn out to a position where the nearby metal 21f7J wiring 8 can be wired by the polysilicon wiring 5 and the metal first layer wiring 3, and a through hole 7 is formed to connect the metal second layer wiring. 8 wiring is possible.

In this case, the minimum length of the polysilicon wiring drawn out from each polysilicon terminal P is sufficient because it is not necessary to avoid wiring within the same cell column in FIG.

Next, as shown in FIG. 4, a second metal layer wiring 8 is formed at a predetermined position so as to be connected to the first metal layer wiring 3 through the formed through hole 7.

As described above, in a semiconductor device in which wiring is performed that gives priority to polysilicon terminal wiring within the same cell column, the polysilicon wiring length of the wiring within the same cell column is limited, and the wiring within the same cell column is Since there is no need to consider the positional relationship of the wiring between other cell columns, the length of the polysilicon wiring 5 extending from the polysilicon terminal P can be minimized, and the distance between the first metal layer wiring 3 and the Metal 2nd
In the wiring using the layered wiring 8, since there is no need to provide a wiring that detours around other wiring, the wiring length can be reduced. Furthermore, by simplifying the wiring, the third layer metal wiring can be used effectively.

〔Effect of the invention〕

As described above, according to the present invention, priority is given to the wiring of polysilicon terminals in the same cell row, and the length of the polysilicon wiring is limited by limiting the length of the polysilicon wiring with relatively large electrical resistance. Or short, also other metal first
An increase in the metal wiring length due to detouring the layer wiring and the metal second layer wiring is prevented, and the performance of the semiconductor device can be improved, and the metal third layer wiring can also be effectively used.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a cell arrangement in an embodiment of the present invention, FIG. 2 is a diagram showing wiring within the same cell in the cell arrangement of FIG. 1, and FIG. 3 is a diagram showing the metallization of the cell arrangement of FIG. FIG. 11 is a diagram showing the wiring of the cell array in FIG. 1, FIG. 5 is an explanatory diagram of the cell array, FIG. 6 is a schematic perspective view without showing the wiring state, Figure 7 is a diagram showing the first stage wiring of a conventional semiconductor device 1π, Figure 8 is a diagram showing the second stage wiring of a conventional semiconductor device: j, and Figure 9 is a diagram showing the completed wiring of a conventional semiconductor device. figure. DESCRIPTION OF SYMBOLS 1...Semiconductor substrate, 2...Cell, 3.11...Metal first layer wiring, 5...Polysilicon wiring, 6.7...Through; Metal second layer wiring, 1...Cell row, m...Metal terminal, P...Polysilicon terminal, y1 to y5... Wiring possible positions of metal second layer wiring. 0 ・Metal; Takako m Wiring 5 - Metal first layer wiring 3 φ--1゛ Meta A second! Wiring possible σMy+-y
5 Exit wiring diagram to metal 2nd layer wiring Figure 3 0 Metal terminal m (Polysilicon wiring) Through hole 6 --- Polysilicon wiring 5 Metal 1st layer wiring] East 3 Within the same cell row Q: Metal end hole, polysilico) end 3p through hole 6.7 --- Self 1. to polysilicon. Izumi 5 - Metal No. 1.1 Placement Elephant 3 -- Metal No. 2! Wiring 8 One implementation of the present invention? Fig. 4: Explanation of the cell arrangement Fig. 5: 0, metal to high-layer m Fig. 11 Wiring 3 -・-Metal 2nd and 1st arrangement 8 Conventional semiconductor length 1 first stage arrangement diagram 0 Metal terminal m Diagram, Poly silicon terminal number ρ O° through hole 6.7 --- Polysilicon Arrangement spring 5 Metal I layer arrangement, 3 -・- Metal second bending arrangement 8 Arrangement of the second stage of the proposed semiconductor surface arrangement! i figure 0 Metal terminal m figure Polysilico''/V height p O, through hole 6.7 --- Polysilicon wiring 5 -, Metal first skin 1 M trap 3 Metal No. 271 Green pattern 8 Conventional half 1 A diagram of the arrangement of the length of the body

Claims (1)

[Claims] A cell row (l) formed by arranging a plurality of cells (2)
In a semiconductor device which has a plurality of cell rows (l) and is formed by automatically wiring metal terminals (m) or polysilicon terminals (P) formed at equal potentials at predetermined positions on both sides of the cell arrangement direction of each cell row (l), the same The polysilicon terminal (P) on one side of the cell row (l) is connected to the metal first layer wiring (3) and the polysilicon wiring (5).
When the total length of the polysilicon wiring (5) as the lead wiring from the polysilicon terminal (P) reaches a predetermined length, the wiring in the same cell column (l) is routed with priority. Then, lead wiring is drawn from the unwired metal terminal (m) and polysilicon terminal (P) located on the opposite side of the cell row (l) to the wiring possible position (y) of the metal second layer wiring (8). form,
A semiconductor device characterized in that the lead wiring is connected by a metal second layer wiring (8) to provide wiring between cell columns.