JPH022147A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH022147A JPH022147A JP14583788A JP14583788A JPH022147A JP H022147 A JPH022147 A JP H022147A JP 14583788 A JP14583788 A JP 14583788A JP 14583788 A JP14583788 A JP 14583788A JP H022147 A JPH022147 A JP H022147A
- Authority
- JP
- Japan
- Prior art keywords
- hole
- current
- semiconductor device
- electromigration
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の概要]
半導体装置の製造方法、特に半導体装置のホール部(開
口部)における配線のエレクトロマイグレーション(e
lectromigration)耐性を向上させるホ
ール部の設計方法に関し、
従来のホール部のマスクパターンでは十分な耐エレクト
ロマイグレーションが得られなかったところを、ホール
部のマスクパターンの形状によって解決する方法を提供
することを目的とし、半導体装置のホール部のマスクパ
ターンの形成において、任意の位数のヒルベル!−(I
lilbert)曲線に相似なグラフに有限幅を与え、
または任意の位置のヒルベルト曲線に幾何学的変形を施
し、ボール部の単位長当り周辺部から流入する電流量を
屈曲のないホール部の場合よりも少なくすることを特徴
とする半導体装置の製造方法を含み構成する。[Detailed Description of the Invention] [Summary of the Invention] A method for manufacturing a semiconductor device, particularly electromigration (e) of wiring in a hole (opening) of a semiconductor device.
Regarding a hole design method for improving electromigration resistance, the present invention aims to provide a method that solves the problem of insufficient electromigration resistance with conventional hole mask patterns by changing the shape of the hole mask pattern. For the purpose of forming a mask pattern for a hole in a semiconductor device, Hilbel of any order! -(I
(libert) give a finite width to a graph similar to the curve,
Alternatively, a method for manufacturing a semiconductor device is characterized in that the Hilbert curve at an arbitrary position is geometrically deformed so that the amount of current flowing from the peripheral part per unit length of the ball part is smaller than that in the case of a hole part without bending. Contains and composes.
本発明は半導体装置の製造方法、特に半導体装置のホー
ル部(開口部)における配線のエレクトロマイグレーシ
ョン(electromigration)耐性を向上
させるホール部の設計方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for designing a hole (opening) of a semiconductor device to improve electromigration resistance of wiring in the hole (opening).
〔従来の技術]
近年の半導体装置の微細化に伴い、ホール部での配線の
エレクトロマイグレーションが問題になってきている。[Prior Art] With the recent miniaturization of semiconductor devices, electromigration of wiring in hole portions has become a problem.
エレクトロマイグレーションとは、例えば配線をアルミ
ニウム(A l )で形成した場合、どの配線に電流を
流したときに八lの原子の移動が発生し、配線の一部で
へl原子の数が少なくなりそこで配線が断線する現象を
いう。Electromigration is, for example, when a wiring is made of aluminum (Al), when a current is passed through which wiring, eight atoms move, and the number of Al atoms decreases in some parts of the wiring. This is the phenomenon where the wiring breaks.
従来の半導体装置においては、ホール部のマスクデータ
は矩形、円形およびこれらの集合で作られていた。第3
図(a)と(b)はポール部の配線の一例を示す平面図
と断面図であり、1は例えば半導体基板、2は絶縁膜、
3は絶縁膜に形成されたポール部、4は上層配線となる
へ!配線で、この例で上層配線4は基板lに形成された
不純物拡散層とコンタク!・をとっている。ホール部の
形状はマスクパターンを用いて矩形に形成されるのであ
るが、マスクパターンは矩形に限定されるものでなく、
円形、矩形と円形の組合わせなどがある。In conventional semiconductor devices, mask data for hole portions are made of rectangles, circles, and sets of these. Third
Figures (a) and (b) are a plan view and a cross-sectional view showing an example of the wiring of the pole part, where 1 is a semiconductor substrate, 2 is an insulating film,
3 is the pole part formed in the insulating film, and 4 is the upper layer wiring! In this example, the upper layer wiring 4 is in contact with the impurity diffusion layer formed on the substrate l!・I am taking . The shape of the hole part is formed into a rectangle using a mask pattern, but the mask pattern is not limited to a rectangle.
There are circular shapes and combinations of rectangular and circular shapes.
近年の半導体装置の微細化に伴うホール部の配線の段差
被覆率の低下などによって、本来の配線部のみに限らず
、ホール部の配線でエレクトロマイグレーションが発生
するようになった。Due to the reduction in step coverage of wiring in hole portions due to the recent miniaturization of semiconductor devices, electromigration has started to occur not only in the original wiring portion but also in wiring in hole portions.
従来、配線部(ライン部)とホール部とは電流密度の基
準を設け、それに合致するように設計してきた。ところ
で、ホール部での電流の動きについては不明な部分が多
く、バイポーラトランジスタにおいて大電流を流す場合
に、ライン部だけでなくホール部でも断線が発生する例
がみられるようになった。ホール部では、第3図(b)
に矢印で示すようにホール部で電流がいわば滝のように
流れ落ちるのであるが、ホール部での^!配線4の厚さ
が薄くなっているとごろで断線が発生し、微細化→高密
度化が進むと、ライン部とホール部とで平行的に配線が
エレクトロマイグレーションに敏感になってきた。とこ
ろで、ライン部ではそれをどう設計するかは計算上出し
やすいのであるが、ホール部では、電流の流れの方向と
かどの方向にどれだけの電流が流れるか未だ十分に解明
されていなくて、すべてのホール部についての耐エレク
トロマイグレーションの評価が難しい。Conventionally, wiring portions (line portions) and hole portions have been designed to meet current density standards. By the way, there are many unknowns about the movement of current in the hole section, and when a large current is passed through a bipolar transistor, there are cases where disconnection occurs not only in the line section but also in the hole section. In the hall part, Fig. 3(b)
As shown by the arrow in , the current flows down like a waterfall in the hole section, but in the hole section ^! Disconnection occurs when the thickness of the wiring 4 becomes thinner, and as miniaturization and higher density progress, the wiring becomes sensitive to electromigration in parallel between the line portion and the hole portion. By the way, in the line part it is easy to calculate how to design it, but in the hole part, the direction of current flow and how much current flows in which direction have not yet been fully clarified. It is difficult to evaluate the electromigration resistance of the hole part.
そこで本発明は、従来のホール部のマスクパターンでは
十分な耐エレクトロマイグレーションが得られなかった
ところを、ホール部のマスクパターンの形状によって解
決する方法を提供することを目的とする。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method that solves the problem in which sufficient electromigration resistance cannot be obtained with the conventional hole mask pattern by changing the shape of the hole mask pattern.
(課題を解決するだめの手段〕
上記課題は、半導体装置のホール部のマスクパターンの
形成において、任意の位数のヒルベルト(lIilbe
rL)曲線に相似なグラフに有限幅を与え、または任意
の位置のヒルベルト曲線に幾何学的変形を施し、ホール
部の単位長当り周辺部から流入する電流量を屈曲のない
ホール部の場合よりも少なくすることを特徴とする半導
体装置の製造方法によって解決される。(Means for Solving the Problem) The above problem is to solve the problem in forming a mask pattern of a hole portion of a semiconductor device.
rL) By giving a finite width to a graph similar to the curve, or by geometrically deforming the Hilbert curve at an arbitrary position, we can calculate the amount of current flowing from the periphery per unit length of the hole compared to the case of a hole with no bend. This problem is solved by a method of manufacturing a semiconductor device, which is characterized by reducing the amount of damage.
第2図(a)と(b)は、本発明の原理説明図で、図中
、11は上層金属、12はホール部(下層金属は図示し
ていない)、aはホールの一辺、bはaと直交するホー
ルの一辺、a、+b、+a、+b0+a、はaと対向す
る屈曲したホールの一辺を示す。11から12を通して
下層金属(半導体基板を含む)へ電流が流れるもので同
図(b)では各部に流れる電流量を矢印の太さで表現し
記号をつけた。2(a) and (b) are diagrams explaining the principle of the present invention. In the figures, 11 is the upper layer metal, 12 is the hole portion (the lower layer metal is not shown), a is one side of the hole, and b is the One side of the hole perpendicular to a, a, +b, +a, +b0+a, indicates one side of the bent hole facing a. Electric current flows from 11 to 12 to the lower metal layer (including the semiconductor substrate), and in FIG. 3(b), the amount of current flowing through each part is expressed by the thickness of the arrow and marked with a symbol.
本発明では、第2図(b)の如くA→A′方向へと上層
金属11中を電流が流れる際、ホール部12を通って下
へ流れる電流の内、a 、+ a 、部で全体のかなり
の部分(“2xao”)が流れ込み、次いでa、部に“
a1″だけ流れ込む。更に、2つのす。部にそれぞれ“
bo”ずつ流れ、残りが2辺すから“b”ずつ入り込む
。この場合、−辺a(ao+at+atに相当)で受け
とめる場合より、2xbo分ホールの周辺部が増えるた
め、単位長あたりに周辺部から流れ込む電流量は、屈曲
のない場合よりも少な(なり、エレクトロマイグレーシ
ョン耐性が向上する。In the present invention, when a current flows through the upper metal layer 11 in the direction A→A' as shown in FIG. A significant portion of (“2xao”) flows in, and then “
A1" flows into each of the two parts.
The remaining two sides flow in by "b". In this case, the peripheral part of the hole increases by 2xbo compared to the case where it is received by - side a (corresponding to ao + at + at), so the flow from the peripheral part per unit length increases. The amount of current that flows is smaller than in the case without bending, and the electromigration resistance is improved.
また、一番弱い(一番条件の苛酷な)ao、a2部で断
線が起きた場合にも2つの50部が存在するために電流
の流れる径路は依然として確保されており、単に周辺長
が伸びるという一次的効果以上に不良に至るまでの時間
は延長する。従来のようにa−辺で支えて断線が生じる
と残りの2辺すから流入せざるを得なくなり、完全な断
線に至る前にコンタクト不良として顕在したような事象
が本発明では発現しにくくなる。In addition, even if a disconnection occurs in the weakest (the most severe conditions) ao and a2 parts, the two 50 parts exist, so the path for the current to flow is still secured, and the peripheral length simply increases. Beyond this primary effect, the time it takes for the product to become defective is extended. If a break occurs when the wire is supported on the A-side as in the past, it has no choice but to flow from the remaining two sides, and the present invention makes it difficult for the phenomenon that manifests as a contact failure before the wire breaks completely to occur. .
以下、本発明を図示の実施例により具体的に説明する。 Hereinafter, the present invention will be specifically explained with reference to illustrated embodiments.
第1図(a)は本発明の一実施例構成図であり、半導体
装置のホール部を示し、図中、第2図で示したものと同
一のものは同一の記号で示してあり、11は上層金属、
12はホール部、aはホールの一辺、bはaと直交する
ホールの一辺、ao+bo+a+十す、+a、はaと対
向する屈曲したホールの一辺を示す。FIG. 1(a) is a block diagram of one embodiment of the present invention, showing a hole portion of a semiconductor device. In the figure, the same parts as shown in FIG. 2 are indicated by the same symbols. is the upper layer metal,
12 is a hole part, a is one side of the hole, b is one side of the hole perpendicular to a, ao+bo+a+ten, +a is one side of the bent hole opposite to a.
第1図(b)は、同図(a)のホール部12のマスクデ
ータ (同図(a)に斜線を付して示す。)の幅を無視
し線分で等価なパターンに表わしたもので、データが複
雑になるので以下の実施例は特に断わりのない限りこの
表現で表わす。FIG. 1(b) shows the mask data for the hole 12 in FIG. 1(a) (shown with diagonal lines in FIG. 1(a)), which is expressed as an equivalent pattern by line segments, ignoring the width. Since the data becomes complicated, the following embodiments will be expressed in this manner unless otherwise specified.
第2の実施例を第1図(C)に示す。この実施例では、
主な電流経路がA−+A′となるように配置すると効果
が大きい。A second embodiment is shown in FIG. 1(C). In this example,
It is highly effective if the main current path is arranged as A-+A'.
第3の実施例は第1図(d)に示す。この場合もA→A
′方向に電流が流れるようにすると効果が大である。A third embodiment is shown in FIG. 1(d). In this case too, A→A
The effect is great if the current flows in the ′ direction.
第4の実施例は第1図(e)に示す。この例においても
電流はA−+A’方向に流した方がよい。A fourth embodiment is shown in FIG. 1(e). In this example as well, it is better to let the current flow in the direction of A-+A'.
第5の実施例は第1図(f)に示す。これは、同図(e
)の例の左半分の大きな2ブロツクに回転を加えて全体
を閉ループにしたもので、第1図(a)から同図(b)
への手順を逆に施したものと見ると、同図((1)の例
の変形例で、A#A’ と両方向の電流に強いパターン
となる。A fifth embodiment is shown in FIG. 1(f). This is shown in the same figure (e
), the two large blocks on the left half of the example are rotated to make the whole into a closed loop.
When viewed as a modification of the example shown in (1) in the same figure, it becomes a pattern that is strong against currents in both directions, A#A'.
こ\で、第1図(b)の例は位数1の、同図(C)の例
は位数2の、同図(d)の例は位数3の、同図(e)の
例は位数4の、同図(f)の例は同図(e)の例の変形
のそれぞれ1lilbert曲線となっており、実際の
マスクパターンは!filbert曲線に有限幅を持た
せたものと見做すことができ、任意の位数の旧1ber
t曲線(及びその幾何学的変形物)と相似なグラフに有
限幅を持たせることによって本発明の実施例となる。t
lilbert曲線を採用する理由は、同曲線が平面内
に最稠密に埋め込みうる曲線であることが数学の定理に
より証明されているからで、与えられた領域内に総延長
最長のパターンになり、電流の流入経路が最大となるか
らである。Here, the example in Figure 1(b) is of order 1, the example in Figure 1(C) is of order 2, the example in Figure 1(d) is of order 3, and the example in Figure 1(e) is of order 1. The example is a 1libert curve of order 4, and the example in figure (f) is a modification of the example in figure (e), and the actual mask pattern is! It can be regarded as a filbert curve with a finite width, and the old 1ber curve of any order
The present invention is implemented by giving a graph similar to the t-curve (and its geometric variations) a finite width. t
The reason why the Lilbert curve is adopted is that it is proven by a mathematical theorem that this curve can be embedded most densely in a plane, and it becomes the longest pattern in total extension within a given area, and the current This is because the inflow route of is the maximum.
第1図(a)〜(f)は本発明実施例構成図、第2図(
a)と(b)は本発明の原理説明図、第3図はホール部
の図で、その(a)は平面図、(b)は断面図である。Figures 1 (a) to (f) are configuration diagrams of embodiments of the present invention, and Figure 2 (
(a) and (b) are explanatory diagrams of the principle of the present invention, and FIG. 3 is a diagram of the hole portion, of which (a) is a plan view and (b) is a cross-sectional view.
図中、
11は上層金属、
12はホール部、
as aos al、d2、b、はホール辺縁部、A、
A’は電流の流れる向き、
を示す。In the figure, 11 is the upper layer metal, 12 is the hole part, as aos al, d2, b is the hole edge part, A,
A' indicates the direction in which the current flows.
以上説明した様に本発明によれば、エレクトロマイグレ
ーションに強いホール部形状を系統的に決定し、最適配
置を得ることが可能になり、半導体素子の微細化及び信
頼度向上に寄与するところが大きい。As explained above, according to the present invention, it is possible to systematically determine the shape of a hole portion that is resistant to electromigration and to obtain an optimal arrangement, which greatly contributes to miniaturization and improved reliability of semiconductor devices.
Claims (1)
において、 任意の位数のヒルベルト(Hilbert)曲線に相似
なグラフに有限幅を与え、または任意の位置のヒルベル
ト曲線に幾何学的変形を施し、 ホール部(12)の単位長当り周辺部(b、b_0)か
ら流入する電流量を屈曲のないホール部の場合よりも少
なくすることを特徴とする半導体装置の製造方法。[Claims] In forming a mask pattern for a hole portion (12) of a semiconductor device, a graph similar to a Hilbert curve of an arbitrary order is given a finite width, or a Hilbert curve at an arbitrary position is given a geometric shape. A method for manufacturing a semiconductor device, characterized in that the amount of current flowing from the peripheral portion (b, b_0) per unit length of the hole portion (12) is made smaller than that in the case of a hole portion without bending by performing a chemical transformation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14583788A JPH022147A (en) | 1988-06-15 | 1988-06-15 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14583788A JPH022147A (en) | 1988-06-15 | 1988-06-15 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH022147A true JPH022147A (en) | 1990-01-08 |
Family
ID=15394254
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14583788A Pending JPH022147A (en) | 1988-06-15 | 1988-06-15 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH022147A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011503841A (en) * | 2007-11-02 | 2011-01-27 | アイピーディーアイエイ | Multilayer structure and manufacturing method thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6079748A (en) * | 1983-10-06 | 1985-05-07 | Sanyo Electric Co Ltd | Multilayer interconnection structure for semiconductor integrated circuit |
-
1988
- 1988-06-15 JP JP14583788A patent/JPH022147A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6079748A (en) * | 1983-10-06 | 1985-05-07 | Sanyo Electric Co Ltd | Multilayer interconnection structure for semiconductor integrated circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011503841A (en) * | 2007-11-02 | 2011-01-27 | アイピーディーアイエイ | Multilayer structure and manufacturing method thereof |
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