JPH02214960A - input/output system - Google Patents

Abstract

PURPOSE:To prevent the deterioration of the input/output speed due to the physical situation of a target buffer by providing a data transfer control means which controls the transfer of data to an intermediate buffer and the target buffer in terms of the data transmission unit and timing. CONSTITUTION:When a data reading request is issued to a disk device 11, a data transfer control means 16 divides an input/output request into the requests to the cylinders and performs the transfer of data to an intermediate buffer 12 from the device 11 via an inter-memory data transfer means 13 in response to the divided requests. When the transfer of data is through to a cylinder, the means 16 transfers data to a target buffer 14 from the buffer 12 via an inter-memory transfer means 15 by means of an idle time when the device 11 prepares to read the data on the next cylinder. As a result, the peripheral devices produce no rotation waiting state and therefore the overall deterioration is prevented for the input/output speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an input/output system for inputting and outputting data to peripheral devices in a computer system.

BACKGROUND ART FIG. 5 shows a block diagram of this conventional input/output system. 51 is a peripheral device such as a floppy disk, 62 is a target buffer for input/output, and 53 is a connection between the peripheral device and the target buffer. 54 is an address monitoring means that monitors the physical address of the target buffer and controls the data transfer means 3 and \-7.

In the conventional input/output system configured as described above, when an input/output request occurs, the address monitoring means 54 monitors the physical addresses of the target buffer 62, and the address monitoring means 54 monitors the physical addresses of the target buffer 62, Divide an input/output request into several partial requests for input/output. Next, the data transfer means 53 transfers data between the peripheral device 61 and the target buffer 52 according to the partial request divided by the address monitoring means 54.

Problems to be Solved by the Invention However, in the above configuration, one input/output request is divided into several partial requests depending on the continuity of the physical addresses of the target buffer (hereinafter referred to as physical continuity). Therefore, with peripheral devices such as floppy disks,
There is a problem in that a rotational wait occurs between one partial request process and the next partial request process, and the overall input/output speed decreases.

In view of this, an object of the present invention is to provide an input/output system in which the input/output speed does not decrease regardless of the state of physical continuity of the target buffer.

Means for Solving the Problems The present invention provides data for controlling data transfer to the intermediate buffers and the data transfer buffers with respect to the intermediate buffers that are continuous on physical addresses and the unit and timing of data transfer according to input/output devices. This is a Daikoku Ka system characterized by being equipped with a transfer control means.

According to the above-described configuration, when an input/output request occurs, the data transfer control means controls to transfer data of a size according to the characteristics of the input/output device to the physically continuous intermediate buffer. . Next, data is transferred between the intermediate buffer and the target buffer. By doing this, there is no need to wait for the rotation of peripheral devices such as floppy disks, so that it is possible to prevent a decrease in the input/output speed of five pages overall.

Embodiment FIG. 1 is a block diagram of an input/output system in a first embodiment of the present invention, and FIG. 2 is a flowchart showing an input/output procedure.

In FIG. 1, 11 is a disk device such as a floppy disk, 12 is a physically continuous intermediate buffer, and 13 is a DM.
14 is a target buffer which is the final data transfer target; 15 is a means for transferring data between peripheral devices and intermediate buffers using a controller (hereinafter referred to as DMAC); An inter-memory data transfer means for transferring data between the buffer 12 and the target buffer 14, and a memory-to-memory data transfer means 16 controls the inter-memory device transfer means and the inter-memory transfer means in synchronization with the data transfer in units of cylinders of the disk device. This is data transfer control means.

The operation of the input/output system of this embodiment configured as described above will be explained below.

Data read request 61 to disk device 11, -
Consider the case where 7 is issued. Input/output is performed as follows according to the flowchart in FIG.

The data transfer control means 16 divides the input/output request into requests for cylinders. Next, the data transfer control means 16 responds to the divided requests by the data transfer means 13 between memory devices.
Then, data is transferred from the disk device 11 to the intermediate buffer 12. When the data transfer for one cylinder is completed, the data transfer control means 16 transfers data from the inter-memory transfer means 15 to the intermediate buffer 12 to the target by using the free time when the disk device 11 prepares to read data from the next cylinder. The buffer 14 is caused to perform data transfer. The data transfer control means 16 repeats this cycle until it reads the last cylinder of data that satisfies the input/output request.

As described above, according to this embodiment, efficient input/output can be performed simply by preparing a buffer for one cylinder as an intermediate buffer.

FIG. 3 shows a block diagram of the input/output 7 beno system in the second embodiment of the present invention, and FIG. 4 shows the relationship between the physical continuity of the target bath sofa and the division of input/output requests. It is. In FIG. 3, 31 is a disk device such as a floppy disk, 32 is a physically continuous intermediate buffer, and 33 is a memory device data transfer means for transferring data between peripheral devices and the intermediate buffer using DMAC.
34 is a target buffer which is the final data transfer target; 35 is inter-memory data transfer means for transferring data between the intermediate buffer 732 and the target buffer 34 using DMAC; and 36 is data in units of cylinders of the disk device. Data transmission control means synchronizes the inter-memory transfer means 33 and the inter-memory transfer means 35 in synchronization with the transfer; 37 is an address monitoring means for monitoring the physical address of the target buffer and controlling the inter-memory transfer means 36; be.

The operation of the input/output system of the second embodiment configured as described above will be explained below.

Consider a case where a data read request to the disk device 31 is issued. The data transfer control means 36 divides the input/output request into requests for cylinders. Next, the data transfer control means 36 transfers the data from the disk device 31 to the intermediate buffer 3 in response to the divided requests.
2 to perform data transfer. When the data transfer for one cylinder is completed, the data transfer control means 36 uses the free time when the disk device 31 prepares to read data from the next cylinder to transfer the data to the inter-memory transfer means 35.
transfer data from the intermediate buffer 32 to the target buffer 34. At this time, the inter-memory transfer means 35
asks the address monitoring means 37 regarding the physical address of the target buffer, and the target buffer 34
Divide an input/output request into several partial requests so that the input/output is for parts with consecutive physical addresses within
(Divide as shown in Figures 4(a) to (b)). after that,
Performs multiple divided inputs and outputs to complete data transfer within the cylinder. This cycle is then repeated until the last cylinder of data that satisfies the input/output request is read.

As described above, according to the present embodiment, by transferring data between the intermediate buffer and the target buffer using DMAC, data transfer can be performed while saving CPU usage time.

As described in detail, according to the present invention, it is possible to prevent a decrease in input/output speed due to the physical condition of a target buffer, and its practical effects are significant.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an input/output system according to one embodiment of the present invention, FIG. 2 is a flowchart showing the input/output procedure of the same embodiment, and FIG. 3 is a block diagram of an input/output system according to another embodiment of the present invention. 4 is a diagram showing the relationship between physical continuity of target buffers and division of input/output requests in the same embodiment, and FIG. 5 is a block diagram of a conventional input/output system. 11... Disk device, 12... Intermediate buffer, 13... Data transfer means between memory devices, 1
4 target buffer, 15... inter-memory data transfer 10 \- transfer means, 16... data transfer control means, 31...
disk device, 32 ... intermediate buffer, 33
...Memory device data transfer means, 34...Target buffer, 35-...Memory data transfer means, 36...Data transfer control means, 37...Address monitoring means, 51. ...Peripheral equipment, 52...
...Target buffer, 53...Data transfer means, 64...Address monitoring means.

Claims (4)

[Claims] (1) an intermediate buffer that is continuous on physical addresses, and a memory device-to-memory device transfer means that transfers data between an input/output device and the intermediate buffer using physical addresses;
The memory-to-memory transfer means transfers data between the target buffer, which is the final data transfer target, and the intermediate buffer, and the memory-to-memory transfer means and the memory 1. An input/output system characterized by comprising a data transfer control means for performing control with an inter-interval transfer means. (2) An input/output system characterized in that the memory-to-memory transfer means according to claim 1 transfers data using a CPU. (3) The inter-memory transfer means according to claim 1 transfers data using a DMA controller, and further includes address monitoring means for monitoring the physical address of the target buffer and controlling the inter-memory transfer means. An input/output system characterized by: (4) An input/output system characterized in that the data transfer control means according to claim 1 performs data transfer control in synchronization with data transfer in units of cylinders of a disk device.