JPH02215207A - Digital type sinusoidal wave generator - Google Patents

Abstract

PURPOSE:To surely obtain a desired sinusoidal wave with simple constitution by adding or subtracting a timing pulse so as to output a digital data based on an addition signal and a subtraction signal generated at a border of a scheduled time for a half cycle. CONSTITUTION:An output at an output terminal (a) of an oscillator 10 is frequency- divided by a binary counter 21 and becomes an output at output terminals b-d. The output at the output terminal (b) has a frequency twice that at the output terminal (c), and the output at the output terminal (d) has a frequency of 2<m> (m>2) with respect to the output at the output terminals b,c, which is a sufficiently low frequency. A signal at the output terminal (d) is subject to 1/12 frequency division by a 12-adic ring counter 22 and each output at output terminals e-j of the counter 22 has a phase difference of pi/12. Outputs at output terminals m,n are synthesized by an AND circuit 27 via NOR circuits 25, 26 and NAND circuits 23, 24 and the resulting signal is inputted to an up-down counter 30 as a clock. The counter 30 receives a signal at the output terminal (j), receives a signal at an output terminal (o) and subtracts the signal at the terminal (o) from the sum at a point of time of pi/2, a digital data is obtained and a sinusoidal wave output is obtained via a D/A converter 40.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a digital sine wave generator that outputs sine wave digital data based on a clock signal.

“Conventional technology” Conventional digital sine wave generators include excavator and R
A device generally includes an OM and a D/A converter. At this time, a commercially available ROM is used, and its power supply voltage is 5V.

Furthermore, in general, when sine waves are synthesized without using a ROM, it is difficult to obtain a sine wave with a low distortion rate due to poor resolution.

"Problem to be solved by the invention" However, in such a conventional digital sine wave generator, the power supply voltage of the ROM is different from the power supply voltage of the operational amplifier of the excavator and the C-MOS of the D/A converter. In this case, it is necessary to interpose an interface between the ROM and the operational amplifier, etc., which complicates the configuration and increases the cost.In addition, if the power supply voltage of the operational amplifier, etc. is set to 5V, which is the same as the power supply voltage of the ROM, noise will be generated. There is a problem in that the margin becomes small and malfunctions occur, which becomes an obstacle to generating a desired sine wave.

The present invention has been made in view of these conventional problems, and provides a digital sine wave generator that can reliably obtain a desired sine wave with a simple configuration and low cost. The purpose is to

"Means for Solving the Problem" The gist of the present invention for achieving the above object is to generate pulses at predetermined timing during half cycles of a sine wave based on a clock signal from an excavator. a digital circuit capable of generating an addition signal and a subtraction signal respectively at scheduled times during the half cycle; and adding or subtracting the pulses based on the addition signal and the subtraction signal. and an up/down counter that outputs a group of digital data corresponding to the waveform of the half cycle.

"Operation" The digital circuit generates a pulse at a scheduled timing during a half cycle of the sine wave, and also generates an addition signal and a subtraction signal at the scheduled time between the half cycles.

The up/down counter adds pulses while the addition signal is being generated, and the successively added values become digital data at that point in time. When a subtraction signal is generated, the number of generated pulses is successively subtracted from the added value, and the successively subtracted value becomes the digital data at that point.

The digital data at each point in time becomes a digital data group corresponding to a waveform of a half cycle of a sine wave.

"Example" An embodiment of the present invention will be described below based on one drawing.

1 to 3 show one embodiment of the present invention.

As shown in FIG. 2, the sine wave is assumed to be a pseudo sine wave. Pseudo-sine wave in positive half cycle.

The interval from 0 to π14 has a slope of 3/π, the interval from π/4 to 5π/12 has a slope of 3/2π, and 5π/]
The interval from 2 to 7π/12 is 1.7π/12 to 3π1
The interval 4 has a slope of 13/2π, from 3π/4 to π
The interval is set to have a slope of -31π.

The negative half cycle is constructed by reversing the polarity of the positive half cycle.

2 and 3 respectively show a circuit diagram of a digital sine wave generator and a timing chart thereof.

In the digital sine wave generator, an excavator IO is connected to an up/down counter 30 via a digital circuit 20. Further, a D/A converter 40 that outputs a sine wave is connected to the up/down counter 30.

If the sine wave output frequency is fo, the frequency of the excavator 10 is selected to be rox izx 2"x 2" (n≧1).

An output terminal a of the excavator IO is connected to an input terminal of a binary counter 21 of the digital circuit 20.

One output terminal d of the binary counter 21 is connected to the hexadecimal ring counter 22, and the other two output terminals i and c are connected to NAN.
They are connected to the input ends of D circuits 23 and 24, respectively.

The hexadecimal ring counter 22 has six output terminals e to j, and each of the output terminals e to j is ON in response to a pulse for a continuous hole from the binary counter 21, and is turned ON for a pulse for the next continuous hole. It is OFF for pulses, and each output terminal 9 to j is turned ON and OFF in turn.
The intervals are shifted by one pulse.

Output terminals e and i are input to a NOR circuit 25, respectively. The output end of the NOR circuit 25 and the output end g are respectively input to the NOR circuit 26.

The output terminal g is input to the NAND circuit 23.

The output signal of the NOR circuit 26 is input to the NAND circuit 24. The output terminal m of the NAND circuit 23 is connected to the OR circuit 27 via the N07 circuit, and the output terminal n of the NAND circuit 24 is connected to the OR circuit 27 via the N07 circuit.

An output terminal 0 of the OR circuit 27 is connected to an up/down counter 30. That is, the output end m.

The output terminal 〇 of the OR circuit 27 is ON except when both n are ON.
The output is output to the up/down counter 30.

An up/down counter 30 is connected to a D/A converter 40. An output terminal j of the hexadecimal ring counter 22 is connected to an up/down counter 30 and also to a flip-flop 50. flip flop 50
The output terminal p of is connected to the D/A converter 40.

Next, the action will be explained.

The output of the output terminal a of the excavator IO is frequency-divided by the binary counter 21 and becomes the output of each output terminal S, c, and d. The output of the output terminal S is twice the frequency of the output of the output terminal C, and the output of the output terminal d has a sufficiently low frequency of 2''' (m > 3) with respect to the output of each output terminal S and C. .

In the hexadecimal ring counter 22, the signal at the output terminal d is divided by 12, and each output terminal e −j of the hexadecimal ring counter 22 is divided by 12.
The output is every π/12.

In the NOR circuit 25, both output terminals e and i are OFF.
Only when
In case 6, the output terminal or the output terminal turns ON only when both outputs of g are OFF.

In the NAND circuit 24, if both the output terminal intersection and the output terminal C of the binary counter 21 are other than ON, the output terminal n is ON.
Therefore, in the NAND circuit 23, when the outputs of the output terminal g and the output terminal S of the binary counter 21 are both other than ON, the output terminal m becomes ON.

In the AND circuit 27, each output of output terminals m and n is connected to output terminal 0.
The up/down counter 30
input as a clock.

At this time, the output of the output terminal j of the hexadecimal ring counter 22 is input to the up/down counter 30 as an addition signal and a subtraction signal, and if the addition signal is input, the output signal of the output terminal 0 is added. Then, at the point of π12, the addition signal is switched to the subtraction signal, and the output terminal 0 is output from the added value.
Subtract the output signal of .

In other words, the added or subtracted values become sequential sine wave digital data.

At the same time, the flip-flop 50 divides the output signal of the output terminal j of the hexadecimal ring counter 22, and divides the output signal of the output terminal p of the hexadecimal ring counter 22.
The output becomes a +, - sign conversion signal and is sent to the D/A converter 4.
It is input to 0. The D/A converter 40 converts the digital data into analog values and outputs a sine wave q.

For example, if the output of the output terminal p' shown in FIG. 3 is used,
A single-phase fully rectified waveform q is output from the D/A converter 40.

In the up-down counter 22, the input frequency as a group of digital data corresponding to a half cycle of a sine wave is
The interval from 0 to πHa is 2f, the interval from π14 to 5πHa2 is f, and the interval from 5π/12 to 7π/12 is 0.7πHa2
The interval from 3π/4 is f, and the interval from 3πc to π is 2f
It becomes.

A pseudo sine wave is output from the D/A converter 40, and this pseudo sine wave is expanded into a Fourier series to obtain a function y(t) of t.
Then, y(t)-Σ((sin nπ/4+5inSnπ/1
2) It can be expressed as 6cosnωLn=1/n"π") n-1,3,5-. Also, the amplitude value b of each nth harmonic
(n) is.

b(n)s+ (sin nfc/4+, 5in5nf
C/12)6/n"w".

The strain rate at this time is D”(b+3 ◆b(S)”◆b (?) ”◆ ++
+)l/1/b(,). The distortion rate determined from the above equation is D-1.6 (%), which is sufficient to be used as a pseudo sine wave.

In the above embodiment, the sine wave is a pseudo sine wave, and O~
Although the π-meter has been divided into five sections, it may be divided into even smaller sections.

According to the digital sine wave generator according to the embodiment,
When applied to sine wave PWM control, the peak part of the sine wave (
5π/12 to 7π/12) is flat, so the sine wave -
There is a practical advantage that the error in the extremely fine pulse portion of the peak portion that occurs during triangular wave comparison PWM control does not occur, and the P W M 1IIIil error is reduced.

"Effects of the Invention" According to the digital sine wave generator of the present invention, since the digital circuit is connected to the D/A converter via the up/down counter, a digital IC such as C-MOS is used in the digital circuit. It becomes possible.

Digital circuits can share a power supply voltage of 5V or higher, the same as D/A converters, etc., eliminating the need for an interface, simplifying the configuration, reducing costs, and improving noise margin. can be made large, and the desired sine wave can be reliably obtained.

[Brief Description of the Drawings] Figures 1 to 3 show an embodiment of the present invention, in which Figure 1 is a circuit diagram of a sine wave generator, Figure 2 is an explanatory diagram of a pseudo sine wave, and Figure 2 is an explanatory diagram of a pseudo sine wave. FIG. 3 is a timing chart of the sine wave generator. 10... Excavator 20... Digital circuit 30... Up/down counter 40... D/A converter C 1Q (hashi; ・N −1χ ε ζ (r

Claims (3)

[Claims] (1) Based on the clock signal from the excavator, a pulse can be generated at a predetermined timing during a half cycle of a sine wave, and the addition signal and subtraction can be performed at the scheduled time during the half cycle. and an up/down counter that outputs a group of digital data corresponding to the waveform of the half cycle by adding or subtracting the pulses based on the addition signal and the subtraction signal. A digital sine wave generator characterized by: (2) The digital data group is converted into an analog value by a D/A converter, and the sign of the analog value is reversed to obtain an analog value of a half cycle opposite to the half cycle of the sine wave. The digital sine wave generator according to claim 1, characterized in that: (3) One cycle of the sine wave is constructed by an analog value of a half cycle of the sine wave and an analog value of a half cycle opposite to the half cycle. wave generator.