JPH022155A - semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To facilitate predetermining the potential of a region having the same conductivity tape as a semiconductor substrate at a value independent from the potential of the substrate by a method wherein the region is isolated from the substrate by semiconductor layers having the different conductivity type provided around the region. CONSTITUTION:Well regions 12 and 13 are surrounded by an n<+>-type buried layer 11 and n<+>-type diffused layers 18 and 18 and isolated from a p<->-type semiconductor substrate 1 and p<+>-type diffused layers 19 and 20 in their neighborhood by p-n isolation. The well region in which an n-MOS 5 is formed is surrounded by the n<+>-type diffused layers 18, the n<+>-type buried layer 11 and the like to which the highest potential in a circuit employing a MISFET is applied and the potential of the well region can be predetermined at an arbitrary value lower than the potential of the respective layers 11 and 18 and the like and the potential difference between the well region and the semiconductor substrate 1 can be predetermined arbitrarily.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit such as old-CMO3 in which a bipolar transistor and a complementary insulated gate field effect transistor (CMOSFET) are formed on the same substrate.

[Conventional technology]

CMO3 (Complementary) is a basic logic circuit.
metal oxide semiconductor
) and bipolar transistors together to realize high-speed performance of the circuit, high-performance and fine bipolar transistors are formed on the same substrate as the CMO5.

FIG. 2 is a cross-sectional structural diagram showing a conventional semiconductor integrated circuit, in which bipolar transistors 3, p
MOS (p channel metal oxide
eselliconductor) 4,n MOS
(n channel met+Jloxide se
microconductor) 5 is formed.

A bipolar transistor 3 is connected to the semiconductor substrate 1.

A type buried layer 6 is provided, on which an n-type collector region 7 is formed by subsequent diffusion, and a p-type base region 8 is formed in the center of this collector region 7 by diffusion from the surface of the epitaxial growth layer 2. Further, an n° type emitter region 9 is formed in the center by diffusion, and the n° type buried layer 6, which constitutes the collector electrode, is formed by diffusion from the surface of the epitaxial growth layer 2 along the sides of the collector region 7. It is constructed by forming an n° type diffusion layer 10 that reaches 100 nm.

Further, 9MO54 and nMO55 are formed into small n-type regions 1 by expanding flk on the n° type buried layer 21 and the p type buried layer 22 provided on the semiconductor substrate 1, respectively.
2. Forming p-type well regions 13 in contact with each other,
P-type source and drain regions 14.14 are formed in the well region 12 by diffusion from the surface thereof, and n°-type source and drain regions 15.15 are formed in the well region 13.
are formed at required intervals, and the source and train regions 1
Gate electrodes 16 and 17 are formed between 4.14 and 15.15 with insulating layers interposed therebetween.

In the map, 19 is a p-type buried layer, and 20 is a buried layer 19 due to diffusion from the surface of the epitaxial growth layer 2.
22, and is formed between the bipolar transistor 3 and the 9MO34°nMOS 5 and on both sides thereof. nMOs 5 are separated from each other.

[Problem to be solved by the invention]

Incidentally, in such a semiconductor integrated circuit, in order to isolate the bipolar transistor 3, its n-type buried layer 6. Low type collector area7. n.

type diffusion layer 10 and p° type buried layer 19. A reverse bias is applied between the p'' type diffusion layer 20 and the p'' type semiconductor substrate 1.

Therefore, the semiconductor substrate 1 is given the lowest potential used in the circuit, and the p-well region 13 electrically connected thereto also has the lowest potential. Thus, for example, circuits with different logic values and supply voltages, e.g.
) When a logic circuit and a CMOS logic circuit are configured on the same substrate, the p-type semiconductor substrate 1 has a potential of, for example, 4.5μ, and the rl-type well region 12 in the 9MO 34 of the CMOS circuit has, for example, a source potential. On the other hand, since the p-type well region 13 constituting the nMOS 5 in the CMO 5 is electrically connected to the semiconductor substrate 1, the potential is biased to 4.5V.

As a result, when a potential of CMO5 logic level, for example, 5V, OV, is applied to the gate electrode 17 of nMO55,
The substrate potential of the old 5FET could not be set to the desired value, and due to the substrate bias effect, this nMOS5 was -4
, 5■ is applied, resulting in a problem that the dark value voltage increases and the drive current decreases.

The present invention has been made in view of the above circumstances, and its purpose is to apply a reverse bias for separating bipolar transistors, etc. even in regions having the same conductivity type as that of a semiconductor substrate. An object of the present invention is to provide a semiconductor integrated circuit which is not affected by the influence.

[Means to solve the problem]

A semiconductor integrated circuit according to the present invention includes a semiconductor substrate in which a region having the same conductivity type as that of the semiconductor substrate is separated from the semiconductor substrate by a semiconductor layer disposed around the region and having a conductivity type different from that of the semiconductor substrate. to form.

[Effect]

According to the present invention, it is thereby possible to set a potential independent of the potential of the semiconductor substrate even in a region having the same conductivity type as that of the semiconductor substrate.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described below based on drawings showing embodiments thereof. FIG. 1 is a cross-sectional structural diagram of a semiconductor integrated circuit according to the present invention, in which, for example, an n-type epitaxial growth layer 2 is laminated on the surface of a semiconductor substrate 1 having a p-type conductivity type, and a bipolar layer is formed on this epitaxial growth layer 2. transistor 3
．． 9MO34 and nMOs5 are formed in this order.

The structure of bipolar transistor 3 is substantially the same as that in the conventional circuit shown in FIG.

That is, a low-type collector region 7 is formed on the buried layer 6 between the semiconductor substrate 1 and the epitaxial growth layer 2 by diffusion into the epitaxial growth layer 2, and a low-type collector region 7 is formed in the center of the collector region 7 from the surface of the epitaxial growth layer 2. A p-type base region 8 is formed by diffusion, and an n° type emitter region 9 is formed in the center of the base region 8 by expansion 11k from the surface of the epitaxial growth layer 2. On the sides of the collector region 7, in contact therewith, there is formed a diffusion layer 10 for an n'-type electrode that reaches the n'-type buried layer 6 by diffusion from the surface of the epitaxial growth layer 2.

pMOs 4. The nMOs 5 are an r-type well region 12 and an nMO35 for forming a pMO54 on an n-type common buried layer ll formed between a p-type semiconductor substrate l and an n-type epitaxial growth layer 2. A p-type well region 13 for forming a p-type well region is formed in contact with the p-type well region 13. In the well region 12, p° is diffused from the surface of the epitaxial growth layer 2 at a required interval.
Furthermore, n-type source and drain regions 15 and 15 are formed in the well region 13 by diffusion from the surface of the epitaxially grown layer 2 at a required interval. It is formed.

A gate electrode 16 is placed on the well region 12 with an insulating material between the source and drain regions 14.14, and a well region 13 is placed between the source and train regions 15+15.
A gate electrode 17 is provided above with an insulating material in between.

An n-type buried layer 11 is formed on both sides of the well region 12 and 13 by diffusion from the surface of the epitaxial growth layer 2.
This is done by forming the same n° type diffusion layers 18, 18, which are semiconductor layers reaching .

In other countries, 19 is a p-type buried layer, and 20 is a buried layer 1 due to diffusion from the surface of the epitaxial growth layer 2.
It is a p° type diffusion layer formed so as to reach 9, and is formed between the bipolar transistor 3 and the pMO 34 and on both outsides of the bipolar transistor 3 and the nMOS 5.
The bipolar transistor 3 is separated from the pMO 34 and nMO 55. As a result, the well regions 12 and 13 are formed with an n-type buried layer 11 surrounding the well regions 12 and 13.
and expansion 13. Surrounded by layer 18.18, p-type ゛I'
- P type diffusion layer 19, 20 in the conductor substrate 1 and its vicinity
This is a structure with p-n separation from .

In the circuit of the present invention, in order to isolate the bipolar transistor 3 from other regions, etc., a p-type buried layer 19. p” type expansion 11!!, layer 20 and p-
type semiconductor substrate 1 and an n-type collector region 7 in the bipolar transistor 3. n.

The buried layer 6, 11 of the type and the layer 10 of the n° type expansion 11.
If a reverse bias is applied to 18, the p-type semiconductor substrate l is thereby given the lowest voltage in the circuit.

On the other hand, the n-type well region 12 constituting the phos 4 is given the highest potential in the circuit using the old SF[iT. For this reason, the n-type scattering layer 18 the n-type buried layer 11
Also, the potential is the same as that of the n-type well region 12.

As a result, the well region where nMO35 is formed is the old S
The n-type scattering layer 18 given the highest potential in the circuit using F E'r is surrounded by the n-type buried layer 11, etc., and the potential is changed to each of these layers 11゜■8
etc., and it is possible to set it to an arbitrary voltage with respect to the semiconductor substrate 1.

As a result, for example, when an IECL logic circuit and a CMO5 logic circuit are formed on the same substrate, the p-type semiconductor substrate 1 is biased to, for example, -4,5■ as described above.
Furthermore, when the n-type well region 12 in the pMO 54 of the CMOS circuit is biased to, for example, 5■, the potential of the well region 13 where the nMO 35 of the CMOS circuit is formed can be set to its source potential, for example, Ov. Therefore, when P and CL open-circuit CMOS circuits are mixed, it is possible to prevent performance deterioration of the CMOS circuit due to the substrate bias effect of the nMOS 5.

Although the above-mentioned embodiment has been described with respect to a configuration using a semiconductor substrate 1 having a p-type conductivity, it is of course applicable to a case where a semiconductor substrate having an n-type conductivity is used.

〔Effect of the invention〕

As described above, in this invention, for example, even if circuits having different logic values and power supply voltages are configured on the same substrate, each substrate potential can be independently set to a desired value. The present invention has excellent effects such as not affecting the performance of the circuit.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional structural diagram of the circuit of the present invention, and FIG. 2 is a cross-sectional structural diagram of a conventional circuit. ■...Semiconductor substrate 2...Epitaxial growth layer 3
...Bipolar transistor 4...p MOS5
... nMO56 ... n-type half layer 7 ... collector region 8 ... heath region 9 ... emitter region 1
0...n'' type diffusion layer 11...n'13...p'n region 19...p+ It should be noted that: type buried layer 12...n- type well region type well region 14.15 ...Source, drain 18...n° type diffusion layer

Claims (1)

[Claims] 1. A region of the same conductivity type as that of the semiconductor substrate,
A semiconductor integrated circuit characterized in that it is formed separated from a semiconductor substrate by a semiconductor layer of a conductivity type different from that of a semiconductor substrate disposed around the semiconductor integrated circuit.