JPH0221635A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce processing time by a method wherein a frame is defined on the boundary between the higher hierarchy and the lower hierarchy, a pattern invading from the lower hierarchy to the higher hierarchy is cut by the frame to make it the higher hierarchy pattern, and a pattern invading from the higher hierarchy to the lower hierarchy is cut by the frame to eliminate the overflowed part. CONSTITUTION:When 'D', 'B', 'A' show a basic cell, a cell and a chip, respectively, a frame (hierarchy-difining frame) to show a hierarchy boundary is defined in each hierarchy, other than mask pattern data in the stage of layout design. Layout is performed so as not to generate overlap (or slit). As to the library processing of patterns between hierarchies, the folling operations are performed by computer processing, from the lower hierarchy to the higher one across several hierarchies; that is, the pattern invading from the lower hierarchy to the higher one across the frame is cut by the frame to make it the higher hierarchy pattern, and the pattern invading from the higher hierarchy to the lower one across the frame is cut to eliminate the protruding part. Thereby, the generation of overlapped-exposure and slits can be prevented, and processing time and exposure data amount can be reduced by performing resizing processing.

Description

Detailed Description of the Invention Industrial Field of Application Prior Art (Figures 3 to 6) Problems to be Solved by the Invention Examples of Means and Actions for Solving the Problems One Embodiment of the Present Invention (Chapter 1.2) Figure) Effects of the invention [Summary] A method for manufacturing a semiconductor device that can perform enlargement and reduction processing (hereinafter referred to as resizing processing) on hierarchical data so that multiple exposures and slits do not occur. The purpose of this method is to specify the internal cells that make up the logic block of an LSI chip for each layer, and create layer patterns and connection relationships between layer patterns in all layers of the cell as layered graphic data. In a method for manufacturing a semiconductor device, a frame is defined at the boundary between an upper layer and a lower layer, and a pattern that crosses the frame and enters from a lower layer to an upper layer is cut at the frame to become an upper layer pattern, and a pattern from the upper layer is A pattern of entering a lower layer across the frame is cut by the frame and the protruding portion is discarded.Hereafter, the above operation is performed from the lower layer to the upper layer over a predetermined layer.

[Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which resizing processing is performed on hierarchical graphic data.

With the recent increase in the scale and density of LSIs, the amount of exposure data and the processing time for graphic processing required are increasing, leading to an increase in the cost of LSI development.

This is because the conventional method of performing graphic processing after expansion processing is no longer able to cope with an increase in the number of graphics to be processed. For example, if processing is performed as usual with the current puller, in the case of 4M memory, the P (poly) layer will have approximately 80 million patterns, which will be 30 in MT.
It will be a huge volume. Moreover, the processing time required to process it by computer is becoming enormous. In particular, in the case of memory products, as shown in Figure 3(b), the original design data may include repeating cells, etc. arranged in an array. By making good use of the structure and processing in hierarchical units, and by giving the exposure data itself a hierarchical structure, it becomes possible to significantly shorten the processing time 11h and reduce the amount of data to be processed in the memory cell section.

[Conventional technology]

In the case of actual exposure, the amount of data is enormous, so for example, in the case of IM DRAM, as shown in Fig. 3 (b).
) The memory cell "'B" 1+11 (128Kbit
) and another 128 Kb that mirrors it.
Exposure data for IT cells and peripheral circuits of the cells was created, and placement processing was performed on the exposure equipment side. but,
In this way, the exposure files are separated, so when scaling is performed, a slit (s 1
or multiple exposure (over 1ap) may occur.
) may occur.

Because of this problem, it is desired to compress and store exposure data.

[Problems to be Solved by the Invention] However, in such a conventional method of manufacturing a semiconductor device, the following problems occur when graphic data processing is attempted in hierarchical units.

(I) When enlargement processing (plus shift) is performed on graphic data that is connected between layers, as shown in Figure 4, the connection points between layers or between cells or between cells and peripheral circuits are Overlap occurs, resulting in multiple exposure. Also,
When reduction processing (minus shift) is performed, slits are generated between layers as shown in FIG. Therefore, when there is an overlap, when drawing is performed using a vector scanning electron beam lithography system, the overlap area may swell and come into contact with the wiring, or
If the slit is empty, an LSI element cannot be formed.

In other words, when processing graphic data, scaling and sizing are currently performed, so even if the design data is created without slits or multiple exposures, over-resizing may occur. Due to size and undersize processing, multiple exposures and slits occur during this time.

(■) Therefore, if you try to remove multiple exposure by searching for a pattern of connection points between layers, you will also have to look at the connections between the layer you are currently processing and other layers, which will take a lot of effort. would become unnecessary and impractical. for example,
To explain the case of negative shift using FIG. 6 as an example: 1) A cannot understand how to handle the connection point pattern unless he finds a pattern that arranges and connects all B's. →It takes a lot of time to process.

1i) For B, the pattern shape differs depending on where it is placed in A, and various variations occur from B. →Data management becomes impossible.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that can perform resizing processing on hierarchical data so that multiple exposure, slits, and scratches do not occur.

(Means for Solving the Problems) In order to achieve the above object, the method for manufacturing a semiconductor device according to the present invention specifies internal cells constituting the logic block of an LSI chip for each layer, and In a method for manufacturing a semiconductor device in which hierarchical patterns and connection relationships between hierarchical patterns are created as hierarchical graphic data, a frame is defined at the boundary between an upper layer and a lower layer, and a frame is entered from the lower layer to the upper layer by crossing the frame. The pattern is cut in this frame and is the pattern of the upper layer, and the pattern that enters from the upper layer to the lower layer by crossing this line is cut in the frame and the protruding part is discarded. A method for manufacturing a semiconductor device, characterized in that the steps are performed over a predetermined hierarchy.

(Operation) In the present invention, a frame is defined at the boundary between the upper layer and the lower layer, and a pattern that crosses the frame and enters from the lower layer to the upper layer is cut by the frame and becomes a pattern for the upper layer. A pattern that enters a lower layer across the frame is cut by the frame and the protruding portion is discarded.Then, the above operation is performed from the lower layer to the upper layer over a predetermined layer.

Therefore, even if the graphic data is connected between layers, the resizing process can be performed without causing multiple exposure or slits.

(Example〕 Hereinafter, the present invention will be explained based on the drawings.

FIG. 1.2 is a diagram showing an embodiment of the method for manufacturing a semiconductor device according to the present invention.

First, the 114 configuration will be explained. FIG. 1 is a diagram for explaining a frame definition method based on comparison with a conventional example, and FIG. 2 is a diagram for explaining inter-layer pattern registration processing.

(1) In Fig. 1, "I" indicates a basic cell, "11B II" indicates a cell, and "A" indicates a chip. First, in the layout design stage, data other than mask pattern data is added to each layer. A frame (hierarchy definition frame) indicating the boundary of the hierarchy as shown in the solid line in FIG. 1(b) is defined. Then, the frames are laid out so that no overlap (or slit) occurs in the frames. Incidentally, in the conventional example, such a frame is not defined at the boundary between layers, as shown by the broken line in FIG. 1(a), and only mask pattern data is manually input.

(II) Next, the following is performed by computer processing as inter-layer pattern registration processing. A pattern that crosses frames and enters from a lower layer to an upper layer is cut at the frame and lifted to the upper layer as an upper layer pattern).
For a pattern that enters from an upper layer to a lower layer across frames, an operation of cutting the frame and discarding the protruding portion is performed from the lower layer to the upper layer over several layers (three layers in this embodiment). Hereinafter, this inter-layer pattern registration process will be specifically explained with reference to FIG. 2.

-← [Eni L position - tone - layer towaka's 1st layer J - Φ9 Furi 2nd
As shown in Figure (a), first, the basic cell pattern is logically processed to remove multiple exposures and slits therein. Then, by performing OR processing on the cell pattern and AND processing with the frame, the pattern (2) that protrudes from the frame is cut by the frame and used as a pattern to be lifted up to the middle layer. Since these processes are performed using graphical processing, they can be performed as a series of processes.

(2) Putter 7+ cut out in the process (1) of (schedule) is ORed with [a and the pattern that originally exists in the middle layer (see figure (b))]. Eliminate multiple exposures. At this time, all the patterns inside the frame created by ORing the lower frames are deleted as shown in the broken line part in (c) of the same figure, and the patterns that go outside from the middle frame are cut out and the same process as in (1) above is performed. Then, the pattern is to be lifted up to a higher level.

(3) Upper (The pattern lifted to the upper part of the chip is ORed with the pattern originally in the upper position to remove multiple exposure. At this time, the pattern entering the middle frame is the part shown in the broken line (d) in the same figure. As shown in (2), the data is deleted as in the process (2).

By the way, normally in the case of memory cells, the wiring does not extend towards the inside of the cell, but always near the edges.
Since the connection is made from the top to the bottom, no problem will occur even if the pattern is cut and deleted as in this embodiment when the pattern is entered from the upper layer to the lower layer.

(I) When the processing in (II) is completed, shift processing (undersize and oversize) and reduction (scaling) are performed next. When executing this shift, it is sufficient to perform it for each layer. That is, (I) above,
Assuming that the processing in (II) has been completed, you can process it layer by layer by processing it so that it does not jump out of the frame the next time you oversize it, and you can also process multiple exposures and slits. does not occur.

For example, if you shift the pattern in a positive direction (oversize), you can shift it so that it does not jump out of the frame that corresponds to 8, and when you shift it in a negative direction (undersize), you can shift it so that it does not leave the frame. Processing is possible, and multiple exposures and slits do not occur.

By executing the processes (1), (II), and (III) above, pattern overlap at the connection points between layers is completely removed. Further, the pattern cutting/lifting process in the inter-layer pattern registration process involves at most three layers, and the time required for this process is not so much of a problem.

Specifically, in the layout design of 4MD-RAM, the frame layout was designed by associating 8-bit basic memory cells with the lower layer, 32-bit I memory cells with the middle layer, and chips with the upper layer. 1, and the manufacturing data is created using hierarchical manufacturing data processing using the inter-layer pattern registration process described in this example, as described in 1), ii), and 1ii) below. It had a great effect.

) Multiple exposures can be completely eliminated.

11) Since processing can be performed in hierarchical units, computer time can be significantly reduced (to about T--T).

111) Since it can be processed layer by layer, the amount of exposure data can be reduced to 0.
．． It can be compressed to 0.01 to 18.55% or less. In this example, about 90 million patterns of a 4M poly layer are used for about 15
It became possible to significantly compress the pattern to 00,000 patterns.

〔effect〕

According to the present invention, a frame is defined at the boundary between an upper layer and a lower layer, and a pattern that crosses the frame and enters from a lower layer to an upper layer is cut at the frame to become an upper layer pattern, and from the upper layer to a lower layer. Patterns that enter across the frame are cut at the frame and the protruding parts are discarded, so even if the graphic data is connected between layers, it can be reproduced without multiple exposure or slits. Sizing processing can be performed, and processing time and exposure data amount can be significantly reduced.

[Brief explanation of the drawing]

Figure 1.2 is a diagram showing an embodiment of the method for manufacturing a semiconductor device according to the present invention, Figure 1 is a diagram for explaining the method of defining the frame, and Figure 2 is the hierarchy thereof. Figures 3 to 6 are diagrams showing a conventional semiconductor device manufacturing method, Figure 3 is a diagram for explaining its hierarchical structure, and Figure 4 is a diagram for explaining the hierarchical structure. FIG. 5 is a diagram for explaining multiple exposure, FIG. 5 is a diagram for explaining the slit, and FIG. 6 is a diagram for explaining the problem when negative shift is performed. Hierarchical structure of the traditional example of the Sui layer structure - diagram of pottery shown in Fig. 3 / -tlL/F' city ＼ Rumors between the cells and the surrounding companies are dead - Figure 4
Figure 7 Figure 7

Claims (1)

[Claims] A semiconductor in which internal cells constituting a logical block of an LSI chip are specified for each layer, and layer patterns and connection relationships between layer patterns in all layers of the cells are created as layered graphic data. In a device manufacturing method, a frame is defined at the boundary between an upper layer and a lower layer, and a pattern that crosses the frame and enters from a lower layer to an upper layer is cut at the frame to become an upper layer pattern, and a pattern from the upper layer to the lower layer is cut at the frame. A method for manufacturing a semiconductor device, characterized in that a pattern that extends across the frame is cut at the frame and the protruding portion is discarded.Hereinafter, the above operation is performed over a predetermined layer from a lower layer to an upper layer.