JPH0221659B2 - - Google Patents
Info
- Publication number
- JPH0221659B2 JPH0221659B2 JP58200390A JP20039083A JPH0221659B2 JP H0221659 B2 JPH0221659 B2 JP H0221659B2 JP 58200390 A JP58200390 A JP 58200390A JP 20039083 A JP20039083 A JP 20039083A JP H0221659 B2 JPH0221659 B2 JP H0221659B2
- Authority
- JP
- Japan
- Prior art keywords
- wire
- lead wire
- lead
- top surface
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/63—Vias, e.g. via plugs
- H10W70/635—Through-vias
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5524—Materials of bond wires comprising metals or metalloids, e.g. silver comprising aluminium [Al]
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置に関し、特に多数のリード
線が金属製基体に設けられた穴にガラス封着され
てなる半導体パツケージの構造に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to the structure of a semiconductor package in which a large number of lead wires are glass-sealed into holes provided in a metal base.
半導体装置には、金属製基体をベースとし、こ
の上に半導体素子を搭載して封止したものがあ
る。半導体素子の電極を外部に導出するためのリ
ード線は、金属製基体に設けられた穴にガラス封
着されて固定され、リード線の頂面にワイヤーが
ボンデイングされて半導体素子と結線される。 Some semiconductor devices are based on a metal substrate, on which a semiconductor element is mounted and sealed. A lead wire for leading an electrode of a semiconductor element to the outside is fixed by glass sealing in a hole provided in a metal base, and a wire is bonded to the top surface of the lead wire to be connected to the semiconductor element.
リード線のガラス封着部からワイヤーボンデイ
ングに供するリード頂面までの長さ（以下、イン
ナーリード長と呼ぶ）は各種のワイヤーボンデイ
ング方法で可能なように通常１mm以下で製造され
ている。インナーリード長さが３〜４mm以上にな
ると、超音波ボンデイングした場合、インナーリ
ード部での超音波エネルギーの吸収が生じ、全く
ワイヤが接続されないか、あるいは強度の弱い接
着しか行なうことができない。したがつて、例え
ば、半導体素子の冷却のために半導体素子と金属
ベースとの間に冷却装置を設ける等の設計上の都
合で、インナーリード長を長くする必要がある場
合は、ワイヤーボンデイングを適用できず、この
結果、他の接続方法、例えば、金属テープを半田
付する等の方法で半導体装置の組立を行なつてき
た。 The length from the glass-sealed part of the lead wire to the top surface of the lead used for wire bonding (hereinafter referred to as inner lead length) is usually 1 mm or less so that it can be used with various wire bonding methods. When the length of the inner lead exceeds 3 to 4 mm, ultrasonic energy is absorbed in the inner lead portion when ultrasonic bonding is performed, and the wire is not connected at all or only weak bonding can be performed. Therefore, if it is necessary to lengthen the inner lead length due to design reasons, such as installing a cooling device between the semiconductor element and the metal base to cool the semiconductor element, wire bonding is applied. As a result, semiconductor devices have been assembled using other connection methods, such as soldering metal tape.
本発明の目的は、インナーリード長が長くても
各種のボンデイング方式で容易にワイヤーボンデ
イングすることができた半導体装置を提供するこ
とにある。 An object of the present invention is to provide a semiconductor device that can be easily wire-bonded using various bonding methods even if the inner lead length is long.
本発明は、リードのボンデイング部近傍で絶縁
体により複数のリードが連結されていることを特
徴とする。 The present invention is characterized in that a plurality of leads are connected by an insulator near the bonding portion of the leads.
以下本発明をその実施例を示す図面に基づいて
詳細に説明する。 The present invention will be described in detail below based on drawings showing embodiments thereof.
第１図は本発明の一実施例を示す。リード線１
は、コバール、Fe−Ni合金等の金属から成り、
インナーリード部１−１の先端近くで円形フラン
ジ状の突出部１−２をもつよう加工されている。
アルミナセラミツク絶縁体２はリード線１が貫通
できる直径をもつた穴があけられており、穴の側
面には、第２図に示すように、Mo−Mn等の高
融点金属によるメタライズ層４が形成される。メ
タライズ層上にはNiメツキ処理が施される。各
リード線１はパツケージのベースとなる金属製基
体６の穴部でホウケイ酸ガラス等の金属封着用ガ
ラス７により1000℃の温度でガラス封着される。
ガラス封着されたリード線１の各々は、例えば３
本毎にアルミナ絶縁体２とAg−Cuロー５等によ
り、フランジ部１−２上部でロー付されて連結さ
れている。この場合ロー付雰囲気は金属−ガラス
の濡れが劣化しないようN2中のような中性雰囲
気中で行なうことが好ましい。最終的に金属部に
はAuメツキ等の処理を施す。 FIG. 1 shows an embodiment of the invention. Lead wire 1
is made of metal such as Kovar, Fe-Ni alloy, etc.
The inner lead portion 1-1 is machined to have a circular flange-shaped protrusion 1-2 near its tip.
The alumina ceramic insulator 2 has a hole with a diameter that allows the lead wire 1 to pass through, and a metallized layer 4 made of a high melting point metal such as Mo-Mn is formed on the side surface of the hole, as shown in FIG. It is formed. Ni plating treatment is performed on the metallized layer. Each lead wire 1 is glass-sealed at a temperature of 1000 DEG C. with a metal sealing glass 7 such as borosilicate glass in a hole in a metal base 6 that is the base of the package.
Each of the glass-sealed lead wires 1 has, for example, 3
Each book is connected by brazing at the upper part of the flange portion 1-2 with an alumina insulator 2 and an Ag-Cu solder 5 or the like. In this case, the brazing atmosphere is preferably carried out in a neutral atmosphere such as N 2 so as not to deteriorate the metal-glass wetting. Finally, the metal parts are treated with Au plating, etc.
半導体素子は例えば冷装装置（共に図示せず）
を介して金属基体６上に搭載され、このため、各
リード１のインナーリード部分１−１の長さは長
くなつている。半導体素子の各電極はワイヤでリ
ード線１の頂面にボンデイングされるが、第１図
で示したように、各リード線１は３本毎に絶縁体
２によつて相互に機械的に連結された形で固定さ
れる。したがつて、リード線１の頂面にアルミニ
ウム線３を超音波ボンデイングする際、構造的に
剛となつており、超音波エネルギーがボンデイン
グ接合界面に集中した状態でワイヤーボンデイン
グでき、強固なボンデイング接合強度を得ること
ができる。ボンデイングが終了すると、ガラスや
セラミツク等の絶縁体、又は金属キヤツプ等で外
界から封止される。 The semiconductor element is, for example, a cooling device (both not shown).
Therefore, the length of the inner lead portion 1-1 of each lead 1 is long. Each electrode of the semiconductor element is bonded with a wire to the top surface of the lead wire 1, but as shown in FIG. fixed in the shape. Therefore, when ultrasonically bonding the aluminum wire 3 to the top surface of the lead wire 1, the structure is rigid, and wire bonding can be performed with ultrasonic energy concentrated at the bonding interface, resulting in a strong bonding. You can gain strength. After bonding is completed, it is sealed from the outside world with an insulator such as glass or ceramic, or a metal cap.
本発明は、リード線がシングルインライン型、
デユアルインライン型あるいは同心状のいずれに
配置されていても、絶縁連結体を適切な形状にす
ることにより対応することが可能である。また、
連結するリード線の数は３本毎に限定されないこ
とは明白である。 In the present invention, the lead wire is a single inline type,
Whether dual-in-line or concentrically arranged, this can be accommodated by suitably shaping the insulating connections. Also,
It is clear that the number of connected leads is not limited to every three.
以上、本発明によれば、インナーリードが長く
従来ワイヤーボンデイングが適用できなかつたよ
うな半導体パツケージ基体でも、絶縁体によりリ
ード線相互を連結することによりワイヤーボンデ
イングを適用することができるので、組立工数が
著しく削減でき、その工業的実用価値は大きい。 As described above, according to the present invention, wire bonding can be applied to semiconductor package substrates with long inner leads to which conventional wire bonding could not be applied by connecting the lead wires with each other using an insulator, thereby reducing assembly man-hours. can be significantly reduced, and its industrial practical value is great.
第１図は本発明の一実施例を示す断面図、第２
図は第１図の部分拡大断面図である。
１……リード線、２……絶縁連結体、３……ボ
ンデイング線、４……絶縁連結体のメタライズ
層、５……ロ−材、６……パツケージ基体、７…
…封着用ガラス、１−１……インナーリード部、
１−２……フランジ突出部。
FIG. 1 is a cross-sectional view showing one embodiment of the present invention, and FIG.
The figure is a partially enlarged sectional view of FIG. 1. DESCRIPTION OF SYMBOLS 1... Lead wire, 2... Insulating connection body, 3... Bonding wire, 4... Metallized layer of insulating connection body, 5... Brazing material, 6... Package base, 7...
...Glass for sealing, 1-1...Inner lead part,
1-2...Flange protrusion.
Claims (1)
た第１の貫通孔を貫通して設けられ、前記リード
線はそれぞれ前記第１の貫通孔にガラス封着さ
れ、前記リード線の頂面にワイヤがボンデイング
され、前記リード線のガラス封着部から前記リー
ド線の頂面までの長さが３mm以上あり、前記リー
ド線の前記頂面近傍には突出部がそれぞれ設けら
れ、前記リード線は所定本数毎に異なる絶縁体に
前記頂面側がそれぞれ挿入され、前記絶縁体には
前記リード線の直径より大きく、前記突出部の直
径より小さい第２の貫通孔が設けられ、前記第２
の貫通孔にはメタライズが設けられ、前記リード
線及び前記突出部の上面と前記メタライズとはロ
ー付されていることを特徴とする半導体装置。1 A plurality of lead wires are provided to pass through a first through hole provided in the package base, each of the lead wires is glass-sealed to the first through hole, and a wire is attached to the top surface of the lead wire. bonded, the length from the glass sealing part of the lead wire to the top surface of the lead wire is 3 mm or more, a protrusion is provided near the top surface of the lead wire, and the lead wire has a predetermined number. The top surface side is inserted into a different insulator for each case, and the insulator is provided with a second through hole that is larger in diameter than the lead wire and smaller than the diameter of the protrusion, and
A semiconductor device characterized in that a metallization is provided in the through hole, and the metallization is soldered to the upper surface of the lead wire and the protrusion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58200390A JPS6092645A (en) | 1983-10-26 | 1983-10-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58200390A JPS6092645A (en) | 1983-10-26 | 1983-10-26 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6092645A JPS6092645A (en) | 1985-05-24 |
| JPH0221659B2 true JPH0221659B2 (en) | 1990-05-15 |
Family
ID=16423528
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58200390A Granted JPS6092645A (en) | 1983-10-26 | 1983-10-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6092645A (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5113611B2 (en) * | 1971-12-23 | 1976-05-01 | ||
| JPS568500B2 (en) * | 1973-05-25 | 1981-02-24 | ||
| JPS5733863B2 (en) * | 1974-11-27 | 1982-07-20 | ||
| JPS554929A (en) * | 1978-06-26 | 1980-01-14 | Hitachi Ltd | Semi-conductor device and the manufacturing method |
-
1983
- 1983-10-26 JP JP58200390A patent/JPS6092645A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6092645A (en) | 1985-05-24 |
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