JPH02216700A - Contents reference memory cell - Google Patents

Abstract

PURPOSE:To reduce the power consumption and to increase the operation speed by providing a retrieving circuit with third MOS transistors TRs of first conduction type and fourth MOS TRs of second conduction type and controlling conduction of these MOS TRs. CONSTITUTION:A retrieving circuit 4 has third MOS TRs 5 and 6 of first conduction type and fourth TRs 7 and 8 of second conduction type, and conduction of third MOS TRs 5 and 6 is controlled by the potential of the input/output terminal of an information holding circuit 1, and that of fourth MOS TRs 7 and 8 is controlled by the potential of bit lines. Potentials of respective bit lines preliminarily set before the retrieval operation of the retrieving circuit 4 for information stored in the information holding circuit 1 and information given to respective bit lines are equal to potentials of respective bit lines preliminarily set before the information write operation to the information holding circuit 1 and the read operation of information stored in this circuit 1. Consequently, it is unnecessary to change potentials of bit lines before the start of each operation. Thus, the power consumption is reduced and the operation speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to memory cells, and more particularly to content-referenced memory cells.

[Conventional technology]

FIG. 5 is a circuit diagram showing a conventional example of a CMOS static type memory cell used in an associative memory device. Details of this cell are r19B5, FFB I S S C
C(International 5oltd-5ta
te C1-rcuit Conference)
Page 45”.

The memory cell shown in FIG.
ive N0R) part EN.

The cell section S uses two CMOS inverter circuits connected to perform a flip-flop operation and an N-channel MO5 type transistor (hereinafter referred to as rNMO3 transistor) whose gate terminal is connected to the word line WL. Each inverter circuit and each bit line BL
, a transfer gate Sl that transmits information with the BT.
, S2. The exclusive NOR section EN is composed of NMo5 transistors connected in a wired AND manner.

In a content addressable memory device using memory cells configured in this way, when performing a search operation, which is a basic function of the content addressable memory device, the bit lines BL, BL, and
Set the wire B to low level and set the match wire ML to the power supply potential (
The search information and the inverted search information whose polarity is opposite to this information are supplied to the bit lines BL and BT which are precharged to the ground level (usually OV), respectively. And the bit line BL,
When the search information supplied to the B stone matches the memory information stored in the cell section S, the match line ML becomes ■l,
. The same information as the search information is stored in the memory cell connected to the match line ML, which is held at a potential.

Further, the information stored in the cell section S is transferred to the bit line BL,
When performing a read operation to B, the bit line is normally precharged to Vet+ potential before starting the read operation, and the bit line WBL is read.

After the precharging of Wl is completed, the transfer gates S1. By setting the word IWL connected to the gate terminal of S2 to a high level state, the transfer gate is activated.
S1, S2 become conductive, and this transfer gate S1. The information stored in the cell section S is transmitted to the focus lines BL and BL via S2 and read out.

[Problem to be solved by the invention]

In this way, the focus line BL before the start of the read operation
, BT are precharged to the vDD potential, but the bit lines BL and BL are precharged to the ground level before the start of the search operation. That is,
The bits iBL and BL are precharged and reloaded each time the operation mode of the content addressable memory device changes. For this purpose, this precharge,
The power and time required to perform bridischarge are
It was required each time the operating mode changed, and was an obstacle to reducing power consumption and increasing speed.

By the way, before starting the read operation, the focus lines BL, B
■ of τ. Even if the bit lines BL, BL are discharged to the ground level without precharging to the potential, the information stored in the cell section S can be read out.

However, for example, when high-level storage information is sent from the output terminal of the inverter circuit to the bit lines BL, BL via the transfer gates SL, S2, an NMO3 transistor is used as the transfer gate St, 32. When the bit lines BL, BL rise from the ground level (usually OV) to the potential (-VT) (VT is the threshold voltage of the NMO3 transistor), the transfer gates (St, S2) become non-conductive. In addition, as the source terminal potentials of transfer gates Sl and S2 rise, VT becomes thicker due to the bank gate bias effect.
will not rise to the potential required to perform a read operation with sufficient margin. Furthermore, bit lines BL, B
As the potential of the bit line BL1 increases, the potential difference between the source and drain of the transfer gates 31 and 32 becomes small (as a result, the rate of increase in the potential of the bit line BL1 becomes slower. Therefore, the via line from the cell part S) Sending of information to BL and BT is delayed,
This also slows down the read speed and causes deterioration in characteristics.

Therefore, the bit line BL before the start of the read operation.

bit line BL without precharging BL.

If the readout operation is performed with the device at ground level, there is no need to precharge the bit, IBL, and BL for each operation mode, but the design must take into account the deterioration of the characteristics described above, resulting in a large It becomes difficult to take an operating margin.

The present invention has been made in view of these points, and its purpose is to obtain a content reference memory cell that can reduce power consumption, increase speed, and perform read operations stably and reliably. There is a particular thing.

[Means to solve the problem]

To achieve this purpose, the content reference memory cell according to the present invention includes a first MOS transistor of a first conductivity type whose source or drain is connected to one bit line and whose conduction is controlled by the potential of the word line. , a second MOS transistor of the first conductivity type whose source or drain is connected to the other bit line and whose conduction is controlled by the potential of the word line, and the first and second MOS transistors of the first conductivity type. An information holding circuit that transmits information to one and the other bit lines and stores the information, and a comparison of the information stored in this information holding circuit and the information given to one and the other bit lines. and a search circuit that holds the potential of the match wire when the two pieces of information match and inverts the potential of the match line when the two pieces of information do not match. 3 MOS transistor and a fourth MOS transistor of the second conductivity type,
The third MOS transistor is controlled to be conductive by the potential of the input/output terminal of the information holding circuit, and the fourth MOS transistor is controlled to be conductive by the potential of the bit line.

[Effect]

In the content reference memory cell according to the present invention, the potential of each bit line is set in advance before the search circuit performs a search operation between information stored in the information holding circuit and information applied to each bit line. The potentials of the respective bit lines, which are set in advance before the operation of writing information to the information holding circuit and the operation of reading information stored in the information holding circuit, are the same, and each operation is started. There is no need to change the potential of the bit line every time the bit line is read.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of a content reference memory cell according to the present invention. This content reference memory cell has information holding circuit 1. 1st. Transfer gate 2.3 as a second MOS transistor, search circuit 4. Word line W
L, bit line BL.

Ding 1. It is composed of maxi lines ML. The information holding circuit 1 is connected to the bit line BL via a transfer gate 2, and is also connected to the bit line BL via a transfer gate 3. This information holding circuit 1 stores information given from the bit line BL during a write operation and information whose polarity is opposite to the above information given from the bit line "1". In circuit 1, during a read operation, information stored in information holding circuit 1 is sent to bits !IBL and BL via transfer gate 2.3.

An NMOS transistor is used as the transfer gate 2.3, and the transfer gate 2.3 is connected to the word vA.
Conduction and non-conduction are controlled by a signal applied from WL, and information is transmitted between information holding circuit 1 and bit lines BL, BL. The information holding circuit 1 is a CMO
The input terminal and output terminal of the S inverter are connected to each other.

The search circuit 4 is composed of both NMOS transistors and PMOS transistors. The NMOS transistor 5 as the third transistor has its gate terminal connected to the source terminal of the transfer gate 3, its source terminal connected to the ground, and its drain terminal connected to the PMOS transistor 5 as the fourth transistor. Connected to the drain terminal. The PMOS transistor has its gate terminal connected to the bit line IML, and its source terminal connected to the bit line IML.

The NMOS transistor serving as the third transistor has its gate terminal connected to the source 1 of the transfer gate 2, its source terminal is connected to the ground, and its drain terminal connects to the PMOS transistor serving as the fourth transistor.
It is connected to the drain terminal of transistor 8. P
MOS transistor 8 has its gate terminal connected to bit line B.
L, and its source terminal is connected to match wire ML.

Next, the search operation, write operation, and read operation of the content reference memory cell configured as described above will be explained. First, the search operation will be explained. Before the search operation is started, the bit lines BL and 101 are set to the power supply potential (
It is precharged to 5V (normally 5V). Thereafter, match line ML is precharged to power supply potential VCC. Also,
For example, information of “1” is stored in the information holding circuit 1 (node N1 is H
level, node N2 is at L level), the gate terminal of NMOS transistor 5 is at L level, the gate terminal of NMOS transistor is at H level, NMOS transistor 5 is in a non-conducting state, and NMOS transistor is at L level. It is in a conductive state.

In this way, the bit lines BL and BL are precharged,
With the match line ML precharged, search information is applied to the bit line BL, and inverted search information, which has the opposite polarity to this search information, is applied to the bit line BL, thereby performing a search operation. For example, bit line B
When applying an H level to L and an L level to bit line 1, P
The gate terminal of MOS transistor 7 is at L level, PMO
The gate terminal of S transistor 8 becomes H level, and PM
The O3 transistor OFF is in a conductive state, the PMO3 transistor 8 is in a non-conductive state, and the potential of the match line ML remains at the VCC potential.

On the other hand, bit line BL has L level search information, bit line π
When H level inversion search information is given to l, PMOS
The gate terminal of transistor 7 becomes H level, the gate terminal of PMO3 transistor 8 becomes L level, PMO3 transistor OFF becomes non-conductive state, PMO3 transistor 8 becomes conductive state, and PMO3 transistor 8. A current flows into the ground via the NMOS transistor 6, and the potential of the match line ML becomes the ground potential. Therefore, when the search information and the stored information stored in the information holding circuit 1 match, the potential of the match line ML is V
If the search information and the stored information do not match, the potential of the match line ML becomes the ground potential. In this way, a search operation is performed by searching for a storage cell in which information matching the search information is stored.

Next, the write operation will be explained. In the write operation, the bit lines BL and BT are precharged to the power supply potential (and the word line WL is set to the H level state, thereby making the transfer gate 2.3 conductive, and the write information is transferred to the bit line BL. At the same time, write inversion information whose polarity is opposite to that of the write information is applied to the bit line BL, and the write information is transferred to the transfer gate 2.
Also, the write inversion information is transferred to the transfer gate 3 via
The write information and the write inversion information are applied to the information holding circuit 1 via the information holding circuit 1.

Also in the read operation, the bit line BL is connected in advance.

The information stored in the information holding circuit 1 is sent to the bit lines BL, BL via the transfer gate 23, and output circuit (not shown) connected to the bit lines BL, BT. It is read out after

As explained above, since the MOS transistor of the search circuit 4 whose conduction is controlled by the bit line is PMO8,
It is possible to start a search operation, a read operation, and a write operation in a state where bits iBL and BL are precharged.

FIG. 2 is a circuit diagram showing a second embodiment of the invention.

The CMOS inverter of the information holding circuit 1 shown in FIG. 1 was replaced with a resistive load type inverter, and the transfer gates 2' and 3' were constructed with PMOS transistors. In addition, in the search circuit 4, M
The OS transistors are NMOS transistors 13 and 14, the MOS transistors whose conduction is controlled by the output terminal of the information holding circuit are PMO3 transistors 11 and 12, and the source terminals of the PMOS transistors 11 and 12 are connected to the power supply at the potential VCC. and their drain terminals are connected to the drain terminals of NMOS transistors 13 and 14, respectively. Also, NMOS transistor 13.14
The source terminal of is connected to the munch iM. Since the transfer gates 2' and 3' are PMOS transistors, stable reading can be performed by predischarging the bit lines BL and B to the ground potential (usually OV) before starting reading.

However, the word gWL must be set to L level when reading or writing. Also, when searching for content, the bins) fiBL and BL are pre-discharged, then the match line ML is pre-discharged, and the information to be referenced is given to the bit lines BL and BL. If they do not match, the potential of the mating wire is set to the power supply potential VCC.

Defects in the above embodiments (FIGS. 1 and 2) will be explained below using the embodiment shown in FIG.

When search information is applied to each of the bit lines BL and BT during a search operation, either PMOS transistor 7 or PMOS transistor 8 becomes conductive. For this reason, even if the search information and the stored information match, the charge accumulated in the match line ML, which is precharged before the start of the search operation, is transferred to the capacitor 9 via the conductive PMOS transistor, or It flows into the capacitor 10 via the PMOS transistor 8, and there is a possibility that the potential of the match line ML decreases and malfunction occurs. Capacity 9 and l
O is the drain terminal of the NMOS transistor 5 and the PMO
The connection point with the drain terminal of the S transistor and NM
This is a capacitance that is formed at the connection point between the drain terminal of the OS transistor 8 and the drain terminal of the PMOS transistor 8 during the manufacturing process of the MOS transistor.

FIG. 3 shows a circuit that eliminates the above problem. In the memory cell shown in FIG. 3, in order to prevent the potential of the match line ML from decreasing (increasing in some cases) when the above-mentioned search information matches the stored information, the source terminal is connected to the match line ML in the search circuit 4. The gate terminals of PMOS transistors 17 and 18 connected to ML are connected to nodes Nl and N, respectively.
2 and the source terminal is connected to ground.
By configuring the gate terminals of the MOS transistors 15 and 16 to be connected to the bit lines BL and B, for example, information of "1" (node N
1 is at H level and node N2 is at L level), the PMOS transistor 18 is in a conductive state, so when the match line ML is precharged, the capacitor 10 is also charged at the same time. . For this reason, even if H level information is given to bit line BL and L level information is given to bit line ■1, and the search information and stored information match, PM
No charge flows into the capacitor 9 via the O3I transistor I8, and the match line ML holds the power supply potential.

In FIG. 4, the search circuit 4 is constructed so as to prevent an increase in the potential of the match wire V when the transfer gate is an NMOS transistor. However, an example will be shown in which the on-resistance of an NMOS transistor is used as the load of the inverter section of the information holding circuit 1.

〔Effect of the invention〕

As explained above, in the present invention, by configuring the search circuit with both PMOS transistors and NMOS transistors, it is no longer necessary to change the potential of the bit line, which was conventionally performed, before starting each operation mode of read, write, and content search. This has the effect of reducing power consumption and increasing speed.

[Brief explanation of the drawing]

1 to 4 are circuit diagrams showing first to fourth embodiments of the present invention, and FIG. 5 is a circuit diagram showing a conventional content reference memory cell. 1... Information holding circuit, 2.3... Transfer gate, 4... Search circuit, 5, 6... NMOS transistor, 7, 8... PMO3I-transistor.

Claims (1)

[Claims] A first M of a first conductivity type whose source or drain is connected to one bit line and whose conduction is controlled by the potential of the word line.
an OS transistor, a second MOS transistor of a first conductivity type whose source or drain is connected to the other bit line and whose conduction is controlled by the potential of the word line, and first and second MOS transistors of the first conductivity type. an information holding circuit in which information is transmitted to and from one bit line and the other bit line and the information is stored; and the information stored in this information holding circuit and the information given to one and the other bit lines. and a search circuit that holds the potential of the match line when the two pieces of information match, and inverts the potential of the match line when the two pieces of information do not match,
The search circuit has a third MOS transistor of a first conductivity type and a fourth MOS transistor of a second conductivity type, and the third MOS transistor is controlled to be conductive by a potential of an input/output terminal of the information holding circuit. , a content reference memory cell characterized in that the fourth MOS transistor is controlled to be conductive by the potential of the bit line.