JPH02216903A - Current mirror circuit - Google Patents

Abstract

PURPOSE:To obtain a current mirror circuit which can be turned ON and OFF and current consumption 'niL' in an OFF state by connecting the common joints of the collector and the base of a transistor TR serving as an input to each other via a MOS TR in the case of a current mirror circuit consists of TRs. CONSTITUTION:In the case of a current mirror circuit consists of TR Q11-Q13, the common joints of the collector and the base of the TR Q11 serving as an input are connected to each other via a MOS TR M11. Thus the connection is cut by the TR M11 between the collector and the base of the TR Q11 serving as an input. As a result, the current mirror circuit is completely turned OFF and the pellet size is reduced. Then the pellet cost is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a current mirror circuit that can be turned on and off, and particularly to a current mirror circuit that consumes zero current when turned off.

[Conventional technology]

Conventionally, this type of current mirror circuit that can be turned on and off has been used primarily to stop circuit operation and reduce current consumption.

FIG. 4 shows a circuit diagram of a conventional current mirror circuit that can be turned on and off. Transistor Q41. is an NPN type transistor whose base and emitter are commonly connected. Q42.
Q43 constitutes a current mirror circuit. The common connection point of the emitter is connected to the ground terminal GND, and the common connection point of the base is connected to the collector of the transistor Q41, which becomes the input of the current mirror circuit.
42, Q43 have their respective collectors connected to output terminals 041.
It becomes 042. A positive voltage V is applied to the power supply terminal v0° with respect to the ground terminal GND. 0 is added to the power supply terminal V. A resistor R41 having a resistance value r is connected between the transistor Q41 and the collector of the transistor Q41. Also, N
It is assumed that the drain and source of the channel-type MOS transistor M41 are connected to the collector and emitter of the transistor Q41, respectively, the gate is connected to the control input I41, and the back gate is connected to the ground terminal GND.

The operation will be explained. First, hunt roll input I41
A case will be explained in which the potential is the same as that of the ground terminal GND. In this case, MOS transistor M41 is off and can be ignored. Therefore, the emitter current IE41 of the transistor Q41 is expressed by the following equation, assuming that the base-emitter forward voltage of the transistor Q41 is V□41 (approximately 0.7V).

Transistor Q41. Q42. Assuming that Q43 are exactly the same transistor, transistors Q42 .
Q43 respective emitter current IE42. IE43 is also I
The same current as F51 flows. Here, transistor Q4
1. Q42. If hFK of Q43 is sufficiently larger than 1, the emitter current and collector current of each transistor will be equal. Therefore, the output terminals 041 and 042 are
Suck current equal to IF42 and IF43.

Next, the potential of the input terminal 141 is the power supply terminal V. . The case where the potential is equal to the potential will be explained. In this case, MOS transistor M41 is turned on and drain current ID41 flows. The gate width of MOS transistor M41 is sufficiently large,
As the drain current ID41, ID41=V. Source-drain voltage VDS41 when a current of /r flows
is sufficiently smaller than the base-emitter forward voltage V□41 of the transistor Q41 (for example, 0.3v or less), the emitter current IE of the transistor Q41
41 does not flow, so the emitter currents IE41 and IF42
Since no current flows, the output terminals 041 and 042 no longer absorb current.

As described above, this current mirror circuit can be turned on and off depending on the potential of the control input I41.

[Problem to be solved by the invention]

The above-mentioned conventional current mirror circuit that can be turned on and off is mainly used to stop the operation of the circuit and reduce current consumption, but as mentioned above, even in the off state, the MOS transistor M41 ID on the drain
Since the drain current of 41 = V cc/r is consumed, the purpose of lowering the current consumption is not sufficiently achieved.

Furthermore, even if a drain current ID 41-vcc/r is passed, the source-drain voltage will be lower than the base-drain voltage.
In order to make the emitter and radial die pressure sufficiently lower than Vnx41, the size of MOS transistor M41 must be increased to a certain extent, and if this circuit is used in an integrated circuit, the pellet size will increase. However, the disadvantages were that the pellet cost increased and the yield decreased.

[Means to solve the problem]

In the current mirror circuit of the present invention that can be turned on and off,
If it is composed of transistors, connect the collector of the input transistor and the common connection point of the base to MO.
They are connected via an S transistor.

Further, when the current mirror circuit is composed of MOS transistors, a common connection point between the drain and gate of the MOS transistor serving as an input is connected via an M, O8 transistor.

In this way, in the present invention, in a current mirror circuit composed of transistors, the connection between the common connection point of the collector and base of the input transistor is
The current mirror circuit is turned off by disconnecting it using an S transistor.Also, in a current mirror circuit composed of MOS transistors, the common connection point between the drain and gate of the MOS transistor that is the input is The current mirror circuit is turned off by cutting off the connection using a MOS transistor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

They are NPN type transistors that are exactly the same.

Transistor Ql 1. Ql 2. Ql 3 is a MOS transistor M whose base and emitter are each commonly connected, the common connection point of the emitter is connected to the ground terminal GND, and the common connection point of the base is an Nch type.
Transistor Qll is connected between the source and drain of Qll.
is connected to the collector of this transistor Qll.
The collector of transistor Q12. becomes the input of the current mirror circuit. The respective collectors of Q13 become output terminals 011.012. Power terminal V. It is assumed that a positive voltage v0° is applied to C with respect to the ground terminal GND, and the power supply terminal V. A resistor R11 having a resistance value r is connected between C and the collector of the transistor Qll. It is assumed that the gate of the MOS transistor Mll is connected to the control input Ill, and the back gate is connected to the ground terminal GND.

The operation will be explained. First, input the Huntroll Ill
When the potential of the MOS is the same as that of the power supply terminal VCC, the MOS
Transistor Mll is turned on, and between the source and drain,
The transistor Ql becomes conductive.1. Ql 2. Ql
3 and operates as a current mirror circuit. In this case, in order to make the potential difference between both ends of the resistor R11 the same as in the conventional example, and to make the currents sucked by the output terminals 011 and 012 the same as in the conventional example, the potential difference between the source and drain of the MOS transistor Mll should be minimized. It has to be made smaller. MOS transistor Mll
The transistor Ql 1. Ql 2. The total base current of O13 is flowing. Now transistor Ql 1.
Ql 2. If the value of Ql3 is 100, and the power supply voltage v0° and resistance value r are set so that the collector current of transistor Qll is 1 mA, a current of 30 μA flows through MOS transistor Mll. There is. In the conventional example, if the collector current of the transistor Q41 is set to 1 mA when the potential of the control terminal I41 is equal to the ground terminal GND, then when the potential of the control terminal I41 is equal to the power supply terminal v0°,
A current of 1 mA or more will flow through the MOS transistor M41. In the case of this embodiment as well, if the source-drain voltage of the MOS transistor Mll is 0.3V, the train current is less than 1/30 compared to that of the conventional example, so the MOS transistor size is less than 1/30. Next, a case where the potential of the control input Ill is the same potential as the ground terminal GND will be described. In this case, MOS transistor Mll is off, and transistor Ql 1. Ql 2. Since no base current is supplied to Ql 3, the current mirror circuit is turned off. In this case, in the conventional example, even when the current mirror circuit is off, M
Although current was flowing through the OS transistor M41, the current consumption is completely zero in this embodiment. still,
When MOS transistor Mll is off, some leakage current may flow. In this case, this leakage current flows through the transistors Ql l, Ql 2 . Ql flows to the base of 3, and a collector current of so (7) h Fl times flows, and the current consumption no longer becomes zero. To prevent this, even if a current equivalent to the leakage current flows, the voltage drop across the transistor's base-emitter forward voltage (approximately 0.7
If a resistor that is sufficiently smaller than V) (for example, 0.3V) is inserted between the common connection point of the base and the ground terminal GND,
Current consumption can be reduced to zero. Further, in the above, the back gate of the MOS transistor Mll is connected to the ground terminal GND, but there is no problem even if the back gate is connected to the common connection point of the base.Furthermore, the potential of the MOS transistor Mll is As long as the potential is such that the MOS transistor Mll is turned off, or the voltage between the source and drain can take a sufficiently small value, it does not need to be equal to the ground terminal GND or the power supply terminal v0°.

FIG. 2 is a circuit diagram of a second embodiment of the invention.

This embodiment is the same as the transistor Ql of the first embodiment.

Ql2. The current mirror circuit composed of Ql3 is connected to Nch type MOS transistors M21, M22 .
It was replaced with M23.

The operation will be explained. When the control person crab 21 is at the same potential as the power supply terminal Vcc, the MOS transistor M
24 is turned on, and the MOS transistors M21. M22. M
The gate of each of the MOS transistors M23 is connected to the drain of the MOS transistor M21, and operates as a current mirror circuit. Also, the control input I21 is connected to the ground terminal GN.
If the potential is the same as that of M21.D, the MO3 transistor M24 is turned off, and the MOS transistors M21. M22. The charges accumulated in the respective gates of M23 and the source of the MOS transistor M24 are discharged through the resistor R22 and are discharged from the MOS transistor M24.
S transistor M21. The potential of each gate of M22°M23 becomes equal to the ground terminal GND, and the MOS transistors M21°M22. M23 is turned off and current consumption becomes zero.

In this embodiment, the value of the resistor R22 must be sufficiently larger than the on-resistance of the MOS transistor M24 in order to accurately obtain the current ratio of the current mirror circuit.

FIG. 3 shows a third embodiment of the invention. This embodiment uses the Nch type MOS transistor Ml of the first embodiment.
1 is replaced with a Pch type MOS transistor M31. Further, the back gate of MOS transistor M31 is connected to its source side, that is, transistor Q3.
It is connected to the 1st flap.

The operation will be explained.

When the potential of control input I31 is equal to power supply terminal VCC, MOS transistor M31 is turned off, transistors Q31. Q32. The base current is no longer supplied to Q33, and the current consumption of the current mirror circuit becomes zero. Next, when the potential of the control input I31 is the same potential as the ground terminal GND, the MOS transistor M
31 is turned on, and transistors Q31. Q32. A base current flows through Q33, and it operates as a current mirror circuit. In this case, the threshold voltage vT of the MOS transistor M31 must be lower than the base-emitter forward voltage (approximately 0.7V) of the transistor.
Since MOS transistor M31 is not turned on, the threshold voltage of MOS transistor M31 needs to be lower than the base-emitter forward voltage.

FIG. 5 is a circuit diagram of a fourth embodiment of the present invention.

Transistor Ql, which is an NPN type transistor and is exactly the same 1. Ql 2. The base and emitter of Ql3 are connected in common, and the common connection point of the emitter is connected to the ground terminal GND, and the common connection point of the base is connected between the source and drain of the Nch type MOS transistor Mll. The collector of the transistor Qll is connected to the collector of the transistor Qll, and the collector of the transistor Qll becomes the input of the current mirror circuit, and the collector of each of the transistors Ql2 and Ql3 is connected to the output terminal o11.
It becomes ゜012. Further, the common connection point of the base is connected to the ground terminal GND via the source-drain of the Nch type MOS transistor M12, and the gate of the MOS transistor Mll is directly connected to the control input Ill, and the MOS transistor The gate of M12 is connected to the control input Ill via the inverter INV, and a signal having the opposite phase to the control input Ill is applied to the gate of the MOS transistor M12. A resistor R11 having a resistance value r is connected between the power supply terminal v0° and the collector of the transistor Qll. It is assumed that the back gates of the MOS transistors M11 and M12 are connected to the ground terminal GND.

The operation will be explained. First, when the potential of the control input Ill is the same potential as the power supply terminal v0°, the MOS transistor Mll is turned on, and the MOS transistor M12
is turned off. When the MOS transistor Mll is turned on, the source-drain becomes conductive, and the transistor Q11°Ql2. It operates as a current mirror circuit by supplying -<-Sumi current to Ql3. In this case, in order to make the potential difference between both ends of the resistor R11 the same as in the conventional example, and to make the current sucked by the output terminals 011 and 012 the same as in the conventional example, the potential difference between the source and drain of the MOS transistor Mll should be made as small as possible. MOS transistor Mll must be connected to transistor Ql.
1. Ql 2. The sum of the base currents of Ql 3 is flowing. Now, transistor Q11°Ql2. Ql3 hFl
If l is 100 and the power supply voltage VCC and resistance value r are set so that the collector current of transistor Qll is 1 mA, a current of 30 μA, which is the sum of the base current of each transistor, flows through MOS transistor Mll. There is.

In the conventional example described above, if the collector current of the transistor Q41 is set to 1 mA when the potential of the control terminal I41 is equal to the ground terminal GND, then when the potential of the control terminal I41 is equal to the power supply terminal vc0, the MOS A current of 1 mA or more will flow through the transistor M41. In the case of this embodiment as well, assuming that the source-drain potential of the MOS transistor M11 is 0.3V, the train current compared to the case of the conventional example is as follows: Let us explain a certain case.

In this case, MO3 transistor Mll is off, and M
OS transistor M12 is on.

Therefore, transistors Ql l, Ql 2. Not only is no base current supplied to Ql 3, but the base potential is actively lowered to the same potential as the ground terminal GND, so the current mirror circuit is turned off.

At this time, in the conventional example, current flows through the MOS transistor M41, but in this embodiment, the current consumption is completely zero.

Incidentally, for some reason, the MOS transistor M12 becomes MOS transistor M12.
Leakage occurs in the S transistor Mll, and this leakage current flows through the transistor Ql1. Ql 2゜Becomes the base current of Ql3, the current mirror circuit works, and the role of preventing the current consumption from becoming zero, and when the current mirror circuit is turned off, the charge remaining in the base of each transistor It has the role of discharging quickly and speeding up switching time. Furthermore, although the back gate of the MOS transistor Mll is connected to the ground terminal GND in the above description, there is no problem in connecting the back gate to the common connection point of the base.

FIG. 6 is a circuit diagram of a fifth embodiment of the present invention.

This embodiment uses the transistor Q11゜Ql of the first embodiment.
2. The current mirror circuit composed of Ql3 is
MOS transistors M21, M22 . M2
3.

The operation is the same as the fourth embodiment.

FIG. 7 shows a sixth embodiment of the present invention. This embodiment is an Nch type MOS transistor Mll of the fourth embodiment.
is replaced with a Pch type MOS transistor M31, and nine gates of each of the MOS transistors M31 and M32 are directly connected to the control input I31. Further, the back gate of the MOS transistor M31 is connected to its source side, that is, the collector of the transistor Q31.

The operation will be explained. When the potential of control input I31 is equal to power supply terminal VCC, MOS transistor M31 is turned off, MOS transistor M32 is turned on, and transistors Q31. Since the base current is no longer supplied to the base of Q32°Q33 and the base potential becomes the same potential as the potential of the ground terminal GND, the current mirror circuit is turned off and the current consumption becomes zero.

Next, when the potential of the control input I31 is the same as that of the ground terminal GND, the MOS transistor M31 is turned on, the MOS transistor M32 is turned off, and the transistors Q31. Q32. A base current flows through Q33, and it operates as a current mirror circuit.

In this case, the threshold voltage V of the MOS transistor M31 must be lower than the base-emitter forward voltage (approximately 0.7 V) of the transistor.
Since MOS transistor M31 does not turn on, the threshold voltage of MOS transistor M31 needs to be lower than the base-emitter forward voltage.

〔Effect of the invention〕

As explained above, in the present invention, when the current mirror circuit is composed of transistors, the common connection point between the collector and base of the input transistor is connected to the MO
By connecting via an S transistor, or if the current mirror circuit is composed of MOS transistors, connect the common connection point of the drain and gate of the input MOS transistor via the MOS transistor. This makes it possible to obtain a current mirror circuit that can be turned on and off and consumes zero current when turned off.

In addition, when integrated circuits are used, the pellet area can be reduced compared to conventional on/off current mirror circuits, so the pellet cost can be lowered and the yield can be improved.

[Brief explanation of the drawing]

1 is a circuit diagram of a first embodiment of the present invention, FIG. 2 is a circuit diagram of a second embodiment of the present invention, FIG. 3 is a circuit diagram of a third embodiment of the present invention, and FIG. The diagrams are circuit diagrams of conventional examples, Figures 5 and 6.
4 and 7 respectively of the present invention. FIG. 7 is a circuit diagram of fifth and sixth embodiments. Agent: Susumu Uchihara, patent attorney Figure 3: 2. -Figure M4 Tofunjin name Ω4z Figure 7

Claims (4)

[Claims] (1) In a current mirror circuit composed of transistors, the common connection point of the bases of each transistor and the collector of the input transistor are connected via a MOS transistor, and a control input is given to the gate of this MOS transistor. A current mirror circuit featuring: (2) In a current mirror circuit composed of MOS transistors, a common connection point between the gates of each MOS transistor and the drain of the input MOS transistor are connected via another MOS transistor, and the gate of the other MOS transistor is A current mirror circuit characterized in that it provides a control input to. (3) In the current mirror circuit according to claim 1, another MOS transistor is provided between the common connection point of the base and the reference point, and the other MOS transistor and the MOS transistor are controlled as described above. A current mirror circuit that turns on and off in a complementary manner in response to input. (4) In the current mirror circuit according to claim 2, further another MOS transistor is provided between the common connection point of the gate and the reference point, and this further MOS transistor
A current mirror circuit characterized in that the S transistor and the other MOS transistor are turned on and off in a complementary manner in response to the control input.